Thesis Sachin Goyal - QUT ePrintseprints.qut.edu.au/26521/1/Sachin_Goyal_Thesis.pdf · 2010. 6....
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POWER NETWORK IN THE LOOP: SUBSYSTEM TESTING USING A SWITCHING AMPLIFIER A Thesis by Publication Submitted in Partial Fulfilment of the Requirements for the Degree of Master of Engineering Sachin Goyal B.Tech (Electrical Engineering) Faculty of Built Environment and Engineering School of Systems Engineering Queensland University of Technology Queensland, Australia February 2009
Transcript of Thesis Sachin Goyal - QUT ePrintseprints.qut.edu.au/26521/1/Sachin_Goyal_Thesis.pdf · 2010. 6....
POWER NETWORK IN THE LOOP: SUBSYSTEM
TESTING USING A SWITCHING AMPLIFIER
A Thesis by Publication Submitted in
Partial Fulfilment of the Requirements for the
Degree of
Master of Engineering
Sachin Goyal
B.Tech (Electrical Engineering)
Faculty of Built Environment and Engineering
School of Systems Engineering
Queensland University of Technology
Queensland, Australia
February 2009
ii
Dedicated to the lotus feet of
‘Sai’
iii
Acknowledgements
I take this opportunity to express my deep gratitude and regards to
Prof. Gerard Ledwich and Prof. Arindam Ghosh, my thesis supervisors, for their
incomparable guidance, supervision, constant encouragement and active participation
throughout the course of this research. Their meticulous and valuable suggestions
encouraged me to complete this work ahead of time. It has been a great privilege for
me to work with them.
I would like to acknowledge my sincere gratitude to Dr. Firuz Zare for his valued
suggestions and advices during the course of this research. The administrative and
technical staffs at the Faculty of Built Environment & Engineering, QUT, have
generously provided support and assistance during the course of my study.
Moreover, I wouldn’t have been able to complete this research without the financial
assistance provided by the Faculty of BEE.
Further thanks are due to many colleagues at the Faculty of BEE for their stimulating
discussions and friendly working environment, especially Mr. Ritwik Majumder,
Mr. Arash, Mr. Alireza Nami, Mr. Zafar, Mr. Manjula, Ms. Tania and Ms. An Le.
Achievements in life do not come alone by one’s own efforts, but by the blessings of
Omnipresent God and parents. I express my deep sense of reverence and profound
gratitude to my parents Mrs. Shakuntala Goyal and Mr. Yogesh Goyal and my sisters
for the pain and sufferings they have undergone to bring me up to this stage. I
acknowledge with utmost warmth their sacrifice, unconditional support, love and
affection.
I am indebted to my college teacher Dr. Rajesh Kumar who always encouraged me to
pursue a career in higher degree research. Also I am thankful to my friends especially
Mr. Aishwarya Bose, Mr. Mohit Gupta and Mr. Praveen Data for their constant
support and motivation.
Sachin Goyal
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Abstract
“Hardware in the Loop” (HIL) testing is widely used in the automotive industry. The
sophisticated electronic control units used for vehicle control are usually tested and
evaluated using HIL-simulations. The HIL increases the degree of realistic testing of
any system. Moreover, it helps in designing the structure and control of the system
under test so that it works effectively in the situations that will be encountered in the
system.
Due to the size and the complexity of interaction within a power network, most
research is based on pure simulation. To validate the performance of physical
generator or protection system, most testing is constrained to very simple power
network. This research, however, examines a method to test power system hardware
within a complex virtual environment using the concept of the HIL.
The HIL testing for electronic control units and power systems protection device can
be easily performed at signal level. But performance of power systems equipments,
such as distributed generation systems can not be evaluated at signal level using HIL
testing. The HIL testing for power systems equipments is termed here as ‘Power
Network in the Loop’ (PNIL). PNIL testing can only be performed at power level and
requires a power amplifier that can amplify the simulation signal to the power level.
A power network is divided in two parts. One part represents the Power Network
Under Test (PNUT) and the other part represents the rest of the complex network.
The complex network is simulated in real time simulator (RTS) while the PNUT is
connected to the Voltage Source Converter (VSC) based power amplifier. Two way
interaction between the simulator and amplifier is performed using analog to digital
(A/D) and digital to analog (D/A) converters. The power amplifier amplifies the
current or voltage signal of simulator to the power level and establishes the power
level interaction between RTS and PNUT.
In the first part of this thesis, design and control of a VSC based power amplifier that
can amplify a broadband voltage signal is presented. A new Hybrid Discontinuous
Control method is proposed for the amplifier. This amplifier can be used for several
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power systems applications. In the first part of the thesis, use of this amplifier in
DSTATCOM and UPS applications are presented. In the later part of this thesis the
solution of network in the loop testing with the help of this amplifier is reported. The
experimental setup for PNIL testing is built in the laboratory of Queensland
University of Technology and the feasibility of PNIL testing has been evaluated
using the experimental studies. In the last section of this thesis a universal load with
power regenerative capability is designed. This universal load is used to test the DG
system using PNIL concepts.
This thesis is composed of published/submitted papers that form the chapters in this
dissertation. Each paper has been published or submitted during the period of
candidature. Chapter 1 integrates all the papers to provide a coherent view of wide
bandwidth switching amplifier and its used in different power systems applications
specially for the solution of power systems testing using PNIL.
vi
Table of Contents
Acknowledgements .....................................................................................................iii
Abstract ....................................................................................................................... iv
Table of Contents ........................................................................................................vi
List of Figures ...........................................................................................................viii
List of Tables...............................................................................................................xi
Keywords ...................................................................................................................xii
List of Publications by Candidate .............................................................................xiii
Statement of Original Authorship .............................................................................xiv
CHAPTER 1 Introduction.......................................................................................1
1.1 Description of the Research Problem .............................................................1
1.2 Literature Review............................................................................................2
1.3 Account of Research Progress Linking the Research Papers .........................6
References ..............................................................................................................10
CHAPTER 2 A Hybrid Discontinuous Voltage Controller For DSTATCOM
Applications ..............................................................................................................15
2.1. Introduction...................................................................................................16
2.2. Voltage Control Structure .............................................................................17
2.2.1. The DSTATCOM model........................................................................18
2.2.2. The Reference generation.......................................................................19
2.3. Strategy for Hybrid Discontinuous Control..................................................20
2.4. Compensator Performance............................................................................26
2.5. Conclusions...................................................................................................36
Acknowledgement..................................................................................................37
References ..............................................................................................................37
CHAPTER 3 Active Power Flow Control In A Distribution System Using
Discontinuous Voltage Controller...........................................................................38
3.1. Introduction...................................................................................................39
3.2. Power Flow Control ......................................................................................41
3.2.1. The UPS model ......................................................................................41
3.2.2. Reference Generation.............................................................................42
3.3. Control Strategies..........................................................................................44
3.3.1. Hybrid Discontinuous Control ...............................................................44
vii
3.3.2 State Feedback Control .......................................................................... 52
3.4. UPS Performance Evaluation ....................................................................... 53
3.5. Conclusions................................................................................................... 62
Appendix - A.......................................................................................................... 63
References .............................................................................................................. 63
CHAPTER 4 Power Network In Loop: A Paradigm For Real-Time Simulation
and Hardware Testing ............................................................................................. 65
4.1 Introduction................................................................................................... 66
4.2. The Hardware-Software Concept ................................................................. 68
4.3. Amplifier Structure ....................................................................................... 69
4.4. Hybrid Discontinuous Voltage Control ....................................................... 71
4.5. Experimental Results ................................................................................... 75
4.6. Power Network In Loop Of A Complex System......................................... 84
4.7. Conclusions.................................................................................................. 90
References .............................................................................................................. 90
Appendix - B.......................................................................................................... 91
CHAPTER 5 Testing of A Distributed Generation System With A Virtual Grid
.................................................................................................................................... 94
5.1. Introduction................................................................................................... 95
5.2. The Concept.................................................................................................. 96
5.3. The Scheme................................................................................................... 98
5.3.1. The UPS Model.................................................................................... 100
5.3.2. The Amplifier Model ........................................................................... 102
5.4. Reference Generation ................................................................................. 102
5.5. Control Strategy.......................................................................................... 104
5.5.1. Control of UPS: Hybrid Discontinuous Control .................................. 104
5.5.2. Control of Current Amplifier (Universal load): ................................... 106
5.6. Conclusions................................................................................................. 114
References ............................................................................................................ 114
CHAPTER 6 Conclusions and Future Research .............................................. 116
viii
List of Figures
Figure 1. 1 Hardware-In-the-Loop Definition [40]......................................................3
Figure 2.1 Single-line diagram of shunt compensation of a load through a feeder. ..17
Figure 2.2. Compensator structure used in which three separate VSCs are supplied
from a common dc storage capacitor...................................................................18
Figure 2.3. VSC scheme to control capacitor voltage................................................21
Figure 2.4. Two zones for voltage control. ................................................................21
Figure 2.5. (a) Capacitor voltage and (b) Inductor current during DC tracking. .......23
Figure 2.6. Four regions of one cycle of a sinusoidal wave.......................................23
Figure 2.7. (a)Capacitor voltage and (b) Inductor current for AC voltage tracking. .24
Figure 2.8. (a) Capacitor voltage and (b) Inductor current for Example 2.1 .............25
Figure 2.9. Compensation of the unbalanced nonlinear load without precharged
capacitor...............................................................................................................28
Figure 2.10. Schematic diagram of the compensation scheme to pre-charge the dc
capacitor...............................................................................................................29
Figure 2.11. (a) DC capacitor voltage, (b) voltage angle at PCC, (b) PCC voltage and
(c) load currents when the dc capacitor is pre-charged. ......................................31
Figure 2.12. (a) PCC voltages, (b) voltage angle and (c) source currents for Example
2.3. .......................................................................................................................32
Figure 2.13. (a) PCC voltages and (b) voltage angle for Example 2.4. .....................33
Figure 2.14. (a) PCC voltages (b) voltage angle (c) and source currents for Example
2.5. .......................................................................................................................34
Figure 2.15 PCC Feeder switching scheme for Example 2.6.....................................35
Figure 2.16 (a) PCC voltage angle, (b) PCC voltages and (c) source currents for
Example 2.6. ........................................................................................................36
Figure 3. 1. Single-line diagram of the distribution system containing a UPS. .........41
Figure 3. 2. UPS structure containing three VSCs that are supplied from a common
source...................................................................................................................42
Figure 3. 3. VSC scheme to control capacitor voltage...............................................45
Figure 3. 4. The two zones voltage control scheme. ..................................................46
Figure 3. 5. Four regions of one cycle of a sinusoidal wave......................................46
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Figure 3. 6. (a) Capacitor voltage and (b) inductor current for Example 3.1............. 49
Figure 3. 7. Inductor current with diode state and VSI output voltage...................... 50
Figure 3. 8. Inductor current and switching. .............................................................. 50
Figure 3. 9. Three-level modulation with state feedback control. ............................. 52
Figure 3. 10. UPS performance during load transient with Mode-1 control.............. 55
Figure 3. 11. System performance at the time of asymmetrical sag in source voltage
for Example 3.3 ................................................................................................... 57
Figure 3. 12. Mode-2 control at the time of sag and swell in the source voltage for
Example 3.4......................................................................................................... 58
Figure 3. 13. Mode-2 control during power reference change................................... 59
Figure 3. 14. Control switching at the time of mode shifting. ................................... 59
Figure 3. 15. System performance during mode switching and load change. ........... 60
Figure 3. 16. System performance during islanding and reclosing............................ 61
Figure 4. 1 Conceptual hardware-software simulation diagram: Voltage control. .... 68
Figure 4. 2 Power amplifier Structure........................................................................ 70
Figure 4. 3. Simple network under study. .................................................................. 70
Figure 4. 4. Voltage controlled VSC amplifier connection with the test side. .......... 70
Figure 4. 5. The two zones voltage control scheme................................................... 71
Figure 4. 6. Four regions of one cycle of a sinusoidal wave...................................... 72
Figure 4. 7 (a) Voltages vp1 and vp2 and (b) voltage tracking error............................ 74
Figure 4. 8. (a) Currents i1 and i2 and (b) the error between these two currents........ 75
Figure 4. 9. The test circuit of Example 4.2............................................................... 76
Figure 4. 10. Schematic diagram of the hardware setup for Example 4.2. ................ 76
Figure 4. 11. Experimental and simulation result for PCC voltage (vp) .................... 77
Figure 4. 12. Experimental and simulation result for i l.............................................. 77
Figure 4. 13. Simulation result for i l .......................................................................... 78
Figure 4. 14. Experimental result for i l during capacitor switching........................... 78
Figure 4. 15. Circuit under test for two generators interaction. ................................. 78
Figure 4. 16. Current at network tearing point (i l). .................................................... 79
Figure 4. 17. Line current passing through R2 (i l1)..................................................... 80
Figure 4. 18. Phase difference between i l1 and v2. ..................................................... 80
Figure 4. 19. Tearing point (PCC) voltage vp. ........................................................... 80
Figure 4. 20. v1 and v2 with 20° phase difference. ..................................................... 81
x
Figure 4. 21. Current at network tearing point (i l). ....................................................81
Figure 4. 22. Tearing point (PCC) voltage vp.............................................................81
Figure 4. 23. Circuit under test for Example 4.4........................................................82
Figure 4. 24. Initial transients in is: (a) simulated waveform and (b) experimental
waveform. ............................................................................................................83
Figure 4. 25. Transients in is during power change: (a) simulated waveform and (b)
experimental waveform. ......................................................................................84
Figure 4. 26. The complex study system....................................................................85
Figure 4. 27. Voltage, current and their errors in Example 4.5..................................87
Figure 4. 28. Voltage, current and their errors in Example 4.6..................................88
Figure 4. 29. Voltage tracking of a complex system at the time of faults..................89
Figure 4. 30. The network considered for stability studies. .......................................91
Figure 4. 31. The test side current containing high frequency ripple components. ...92
Figure 4. 32. The distorted PCC voltage....................................................................92
Figure 4. 33. System structure with LPF....................................................................92
Figure 4. 34. Stable PCC voltage with LPF. ..............................................................93
Figure 5. 1 Conceptual hardware-software simulation diagram: Current control. (a)
The Un-torn Network (b) Torn Network.............................................................97
Figure 5. 2. Distributed Generation scheme under test ..............................................99
Figure 5. 3 Network Tearing Scheme ......................................................................100
Figure 5. 4. UPS structure used in which three separate VSCs are supplied from a
common dc storage capacitor. ...........................................................................101
Figure 5. 5 The Structure of Universal Load ...........................................................102
Figure 5. 6. VSC scheme to control capacitor voltage.............................................104
Figure 5. 7. The two zones voltage control scheme. ................................................105
Figure 5. 8 Performance of UPS in torn Network....................................................108
Figure 5. 9 Performance of UPS during load change in torn network .....................109
Figure 5. 10 Performance evolution during sag .......................................................110
Figure 5. 11 Performance evolution during Mode II operation ...............................111
Figure 5. 12 Scheme for utility feeder change .........................................................111
Figure 5. 13 UPS performance during utility feeder change....................................112
Figure 5. 14 Performance of torn network during mode change .............................112
Figure 5. 15 Fault evolution using torn network..................................................................113
xi
List of Tables
TABLE 1. 1 COMPARISION OF DIFFERENT AMPLIFIERS ................................ 7
TABLE 2. 1. SYSTEM PARAMETERS................................................................... 27
TABLE 3. 1. COMPARISON OF STATE FEEDBACK AND DISCONTINUOUS
CONTROL .......................................................................................................... 55
TABLE 3. 2. DATA SHEET OF TOSHIBA SILICON N CHANNEL IGBT,
MG400J1US51.................................................................................................... 63
TABLE 4. 1: SYSTEM PARAMETERS FOR EXAMPLE-4.3. .............................. 79
TABLE 4. 2: PARAMETERS OF THE SYSTEM OF FIG. 4.24. ............................ 85
xii
Keywords: DSTATCOM, Discontinuous Current, Hybrid Control, LC Output
Filter, UPS, Power Flow Control, Real-Time Simulator, Hardware-Software
Simulation, VSC, Harmonics, Bandwidth, Virtual Grid and Universal Load.
xiii
List of Publications by Candidate
The following publications have been produced as a result of this thesis:
Peer Reviewed Journal Papers
1. S. Goyal, A. Ghosh and G. Ledwich, “Active Power Flow Control in a
Distribution System Using Discontinuous Voltage Controller”, Electric
Power Systems Research, 2008. pp. 255-264.
Peer Reviewed International Conference Papers
1. S. Goyal, A. Ghosh, and G. Ledwich, "A hybrid discontinuous voltage
controller for DSTATCOM applications," in Power and Energy Society
General Meeting - Conversion and Delivery of Electrical Energy in the 21st
Century, 2008 IEEE, 2008, pp. 1-8.
Journal papers under Review
1. S. Goyal, G. Ledwich and A. Ghosh, “Power Network in Loop: A Paradigm
for Real-Time Simulation and Hardware Testing”, IEEE Transaction on
Power Delivery, 2008.
2. S. Goyal, A. Ghosh and G. Ledwich, “Testing of A Distributed Generation
System With A Virtual Grid”, Electric Power Systems Research, 2008.
(Expected Submission 7 November 2008)
xiv
Statement of Original Authorship
The work contained in this thesis has not been previously submitted for a degree or
diploma at any other higher education institutions. To the best of my knowledge and
belief, the thesis contains no material previously published or submitted for
publication by another person except where due reference has been made.
Signed:
(Sachin Goyal)
Date:
1
CHAPTER 1
INTRODUCTION
1.1 Description of the Research Problem
Most research has been based on pure simulation due to the size and the complexity
of interaction within a power network. To validate the performance of a physical
generator or protection system, most testing is constrained to a very simple power
network. This research examines a method to test power system hardware within a
complex virtual environment.
Integration of real-time simulation with physical system gives an opportunity to test
a small system interacting with large power network. According to this concept, a
complex power network is simulated in real time digital simulators and with the help
of a high bandwidth switching amplifier; the physical system is connected in the loop
with the simulation.
Digital computer simulations have been used extensively in power systems studies
for both design and testing. However, this form of evaluation tool is often not
suitable for testing of protective devices like relays or testing real life controllers. To
alleviate this problem, real-time digital simulators have been developed, which use
high speed parallel processors to simulate a complex power network within
microseconds. These simulators can be interfaced with a physical controller on-line
and this form of operation is often termed as “hardware-in-the-loop” (HIL) testing
The aim of this research is to broaden the “hardware in the loop” concept to include
testing of power network components. For the simulation of large systems, Kron’s
method of tearing the network into two or more segments offers possibilities to test
physical hardware system with real time simulation.
2
To interface the hardware model with a computer simulation and to transfer high
frequency disturbances of power network, a high bandwidth amplifier is required that
can transfer signals between simulated model and the hardware. This amplifier is
basically an inverter that can generate high frequency current or voltage component.
For testing of faults or transients, the amplifier must be capable of providing high
frequency current components.
The bandwidth of an amplifier can be increased using higher and variable switching
frequency. But variable frequency causes high switching losses and makes designing
of an output filter complex.
In this thesis, a method of amplifier control is proposed that amplifies the wide
bandwidth voltage signals with minimum number of switching events. The same
amplifier is used in DSTATCOM to supply harmonic current with large bandwidth.
Also, with the help of the amplifier, a UPS is designed that can supply a part of the
load power with power quality solution.
The main focus of this research is to provide a solution for HIL testing for power
systems which is termed here as ‘Power Network in the Loop’, with the help of high
bandwidth amplifier. Simulation and experimental studies of hardware-software
integration are shown. In the final part of this research a method is proposed to test a
distributed generation system with universal load which has the power re-generation
capacity.
1.2 Literature Review
Hardware in the loop: The terminology of “Hardware in the Loop” (HIL) is very
common in the automotive industry. The sophisticated electronic control units which
are used for vehicles are usually tested and evaluated using HIL-simulation [1-3].The
HIL testing leads to designs that function effectively in situations that will be
encountered by the electronic control unit. The concept of HIL testing for motor
controller is reported in [4, 5]. The interface of real-time controller with a simulated
circuit is reported in [6]. Controller output is sent to real time virtual test bed
3
(RTVTB) through an A/D card while the simulation output is sent to micro-
controller. Here, the communication occurs at low voltage. To test the power
electronics equipments HIL concept is used in [7]. In all of the above testing the
interaction between real time simulation and hardware is done at a low voltage level.
Therefore the hardware which is under test is directly connected to simulation output.
Figure 1.1 [40] shows the basic concept of HIL, in which an engine is simulated in
the digital simulator and a physical hardware controller is interfaced with the digital
simulator.
Figure 1. 1 Hardware-In-the-Loop Definition The concept of HIL testing opens the wide area of highly realistic testing for power
systems. But power systems equipments can not be directly interfaced with real time
simulation because of its high voltage level. A small testing of power system
equipment with the concept of HIL is reported in [8]. But it does not describe the
network tearing concept. To test the power systems network with HIL concept, the
total network is torn in two parts. One part is simulated in the real time simulator and
the hardware under test represents the second part of the network.
The network tearing aspect has been studied in a two part paper [9, 10]. In Part 1 [9],
different methods of tearing are presented and compared against their performance.
This paper discusses power hardware in loop (PHIL) concept through a two way
interaction. But it does not discuss the hardware feasibility. The frequency response
4
of different simulation/hardware interface schemes has been presented in [10].
However, it does not present the stability analysis aspects of the tearing.
As stated earlier, the power systems equipments can not be directly interfaced with
real time simulation. Therefore a power amplifier is required to interface power
equipment with real time simulation that can amplify the voltage or current signal of
the simulator to the level of the power equipment. An operational amplifier based
amplifier can not serve the purpose because of its power limitation. A voltage source
converter based amplifier is required to integrate the real time simulation with the
power equipment. The VSC is controlled in close loop to generate high voltage
reference signals. The control scheme of active power filters is helpful in designing
the control structure of power amplifier.
Active power filter: The primary objective of this part of literature review is to find
recent control techniques of Active Power Filters for both single and three phase.
Active Power Filters (APF) are power electronic inverters connected to the power
system for harmonic correction or to provide reactive power to correct the
fundamental voltage [11, 12]. In single phase APF, the H bridge voltage source
inverter is used and sliding mode close loop control was used to control the active
wave shaping function of the active filter[13]. This control methodology is able to
compensate for multiple nonlinear loads in parallel. But its switching frequency is
very high and not constant. This increases the switching losses and makes
suppression of switching frequency components difficult. For the three phase active
filter simple hysteretic current control is not suitable because the presence of LCL
filter generates stability issues [14-16]. It presents LQR and hysteresis control for
generating switching pulses, which is a stable control. Here, positive sequence of
fundamental Point of Common Coupling (PCC) voltage is calculated for reference
voltage. But in this case switching frequency is not constant, so it makes elimination
of this higher frequency component difficult. If switching frequency can be filtered
out, then the calculation of positive sequence of fundamental is not required.
Inverter Control: This section is to familiarise with the control techniques which
are used to control the inverter as an amplifier for active filter[17-19]. Different kind
of hysteresis current controls are discussed; based on the benefits and limitations of
5
each technique, a proper method can be determined. To reduce switching frequency
losses[20] and constant switching frequency operation[21], a variable band
Hysteresis Current Control [HCC] is presented [15, 22-24]. It provides constant
switching frequency operation of APF. But to filter out this switching frequency
component, a simple R-L type filter is used. For better suppression, a capacitor is
used. Because of this capacitor, a simple hysteresis control gives stability issues so a
close loop stable control is required. A simple method to achieve constant switching
frequency by adding auxiliary signal in error signal is presented[25, 26]. But using
this technique, low switching frequency can not be achieved. This is effective only at
high frequency. The impact of addition of low frequency auxiliary signal is not
presented. An optimal voltage vector based hysteresis current control method with
constant switching frequency for APF is presented[27]. However, in this case online
position on space vector is required that could increase computation. A three level
hysteretic current control is presented to reduce the switching frequency component
in output current and voltage[28]. These switching frequency component and
switching losses can be further reduced by five level hysteretic current control[29].
But this technique increases the number of switches in the power circuit. At a
constant switching frequency, if an inverter is able to supply higher order harmonic
current then there would be some phase lag in tracked current. That increases higher
order harmonic terms in error. Simple feed-forward method is presented to overcome
this issue [30, 31]. But if load is not known then in that case simple feed-forward
method can not be used to provide harmonic current to the load.
Passive Filter: To eliminate the switching frequency component from output voltage
and current, a passive filter is used at the output of the inverter[32, 33]. Type of this
filter may vary[34]. Simple R-L type filter needs simple control but can not filter the
high frequency switching components from output voltage and current. A LCL filter
eliminates switching frequency components effectively. But it requires advance
control to operate in stable condition.
Stability: When an inverter is used as an amplifier in active filter to supply harmonic
current, stability is one of the main concern. To operate system in stable condition at
different loads, a robust control is required[35]. Fuzzy controlled APF is presented in
[36]. A comparison of different controllers with PI controller is also presented[37,
6
38]. LQR control of active filter is described with hysteresis control [14, 39]. Study
of stability at resonance frequency of filter is required.
A solution for power systems equipments testing can be found using HIL concept
with the help of high bandwidth amplifier. An advance control is required for
amplifier control and the network tearing concept can be used for HIL testing for
power systems.
1.3 Account of Research Progress Linking the Research Papers
Hardware-In-the-Loop is a form of real-time testing. Hardware-In-the-Loop differs
from pure real-time simulation by the addition of a “real” component in the loop with
real time simulation. The purpose of a Hardware-In-the-Loop system is to provide all
of the electrical stimuli needed to fully exercise the hardware which is under test. In
effect, “fooling” the testing hardware into thinking that it is indeed connected to a
real plant. This concept has been used for controllers or relay testing for a long time.
Hardware can be connected to the real time simulation only if the voltage level of
both the signals (simulation and physical hardware) is same. But because of the
difference in voltage levels of simulation signal (5 volt) and power equipments (240
volt), this concept can not be used directly to test the power systems equipments. To
implement this concept in power systems testing, the simulation signal is amplified
to the level of physical hardware and the signal of physical hardware (voltage or
current) is scaled down to the level of simulation signal.
Current or voltage of physical power systems equipment can be easily scaled down
to the level of simulation signal with the help of current or voltage sensors. But to
amplify the simulation current or voltage signal to the level of physical equipment, a
power amplifier is required which can amplify the signal level to the power level.
There are some good quality analog amplifiers are available in the market that can
amplify the wide range of frequency signals. But these amplifiers can supply only
small amount of current, therefore they can not help in testing the power systems
equipments.
7
To solve this problem an inverter based wide bandwidth amplifier is designed. The
amplifier is made of a voltage source converter (VSC) and a filter. The filter is used
to filter out the switching frequency components from output current or output
voltage. A comparative study of different type of control and filter structures for
current amplifier has been performed. The comparison is made based on the
following criterion:
• The average error in output current should be less than 10% of the reference.
• Each Harmonic component in current error (FFT of error) should be less than
10% of the reference.
• Switching frequency components in output point of common coupling (PCC)
voltage should be less than 5% of the fundamental component.
• Switching events should be less than 200 in one fundamental cycle (0.02s).
Using the above criterion, the following outcome is noted for 5 types of amplifier
structures:
TABLE 1. 1 COMPARISION OF DIFFERENT AMPLIFIERS
Type Filter Type
Control Switching Edges per
cycle
Order of harmonic that can be amplified
1. L Simple Hysteretic Current
control 191
Fundamental (50 Hz)
2. LC 2 Level HCC with state
feedback control. 206 9th (450 Hz)
3. LC 2 Level adaptive band HCC with state feedback control.
200 11th (550 Hz)
4. LC Fixed frequency sampled
control 200
Fundamental (50 Hz)
5. LC 3 Level HCC with state
feedback control. 205 21st (1050Hz)
From the above comparison it is clear that an amplifier with LC filter and 3 level
HCC with state feedback control can amplify the maximum range signals. All control
schemes which are described above can be used for voltage amplifier as well. For
voltage amplifier, a new hybrid discontinuous control is proposed that gives better
performance than a 3-level hysteresis band control in terms of both switching and
tracking.
8
The design and control of the hybrid discontinuous controller is described in details
through chapters 2 and 3. This amplifier can be used for several power systems
applications. To investigate the efficiency of the hybrid discontinuous controller
based voltage amplifier, the amplifier is tested for the distribution static compensator
(DSTATCOM) application. Chapter 2 (A Hybrid Discontinuous Voltage Controller
For DSTATCOM Applications) describes the use of the hybrid discontinues voltage
controller in DSTATCOM application. The DSTATCOM controls PCC voltage.
Installation of a DSTATCOM at consumer premises is an effective solution to power
quality problems that originate in the distribution system.
Chapter 3 (Active Power Flow Control In A Distribution System Using
Discontinuous Voltage Controller) describes the use of hybrid discontinuous voltage
control methodology for a voltage source converter (VSC), which is used in a
Distributed Generation (DG) system which overcomes the power quality problem,
while supplying power from DGs at the same time. In case of emergency, when there
is no power from the grid, DG can supply the total load, due to this function, the total
DG system is termed as uninterruptible power supply (UPS) in this chapter. The UPS
controls the voltage at the point of common coupling (PCC). This UPS can
compensate the load at the time of sag or swell in source voltage. Also it can
compensate the load at the time of change in feeder load conditions.
The chapter 2 and 3 together describes the use of voltage amplifier in power systems.
In the later part of this thesis this amplifier is used for hardware in loop testing of
power system equipments which is termed here as ‘Power Network in the Loop’.
Chapter 4 and 5 demonstrate the feasibility of network in loop.
Chapter 4 (Power Network in Loop: A Paradigm for Real-Time Simulation and
Hardware Testing) discusses a new paradigm of real-time simulation of power
systems in which an equipment can be interfaced with a real-time simulator. The
physical system is driven by a voltage source converter (VSC) that is mimicking the
power system simulated in the real-time simulator. In this chapter, the VSC is
operated in a voltage control mode with the help of hybrid discontinuous controller
to track the PCC voltage supplied by the simulator. This type of splitting a network
into two parts and running a real-time simulation with a physical system in parallel is
9
termed here as a hardware-software simulation. This opens up the possibility of the
study of interconnection of one or several distributed generators to a complex power
network. The proposed implementation is verified through simulation studies using
PSCAD/EMTDC and through hardware implementation on a TMS320F2812 DSP.
After the successful experimental testing of “Power Network In the Loop”, a testing
method for distributed generation system (DGs) is proposed with the concept of
network in loop. Chapter 5 (Testing Of A Distributed Generation System With A
Virtual Grid) provides the solution for testing of a DGs with a computer simulated
grid. The computer simulated grid is referred as a virtual grid in this paper.
Integration of DG with the virtual grid provides a broad area of testing of power
supplying capability and dynamic performance of a DG. It is shown that a DG is
supplying a part of load power while keeping PCC voltage magnitude constant. To
represent the actual load, a universal load along with power regenerative capability is
designed with the help of voltage source converter (VSC) that mimics the load
characteristic for DG. The overall performance of the proposed scheme is verified
using computer simulation studies.
Altogether chapters 2, 3, 4 and 5 illustrate the concept of an amplifier with new
control structure which can be used for several power systems applications. This
amplifier is used to provide a solution for hardware in loop testing of power systems
applications.
This thesis is based on published/submitted papers as listed below:
Chapter 2: S. Goyal, A. Ghosh and G. Ledwich, “A Hybrid Discontinuous Voltage
Controller for DSTATCOM Applications”, IEEE PES General Meeting, USA, 2008.
Chapter 3: S. Goyal, A. Ghosh and G. Ledwich, “Active Power Flow Control in a
Distribution System Using Discontinuous Voltage Controller”, Electric Power
Systems Research, 2008.
Chapter 4: S. Goyal, G. Ledwich and A. Ghosh, “Power Network in Loop: A
Paradigm for Real-Time Simulation and Hardware Testing”, IEEE Transaction on
Power Delivery, 2008.
10
Chapter 5: S. Goyal, A. Ghosh and G. Ledwich, “Testing of A Distributed
Generation System With A Virtual Grid”, Electric Power Systems Research, 2008.
References
[1] S.Shaoyou, G. Feng ands. Ke, “Model of Intelligent Vehicle Cruise and
Hardware-in-the-loop Test”, IEEE International Conference on Vehicular
Electronics and Safety, 2006, PP. 329 – 332, 13-15 Dec. 2006.
[2]. E. F. Stefatos, T. Arslan, D. Keymeulen, and I. Ferguson, "Integrating the
Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an
Evolvable Hardware Architecture," in Field Programmable Logic and
Applications, 2006. FPL '06. International Conference on, 2006, pp. 1-4.
[3]. S. M. Shah and M. Irfan, "Embedded hardware/software verification and
validation using hardware-in-the-loop simulation," in Emerging
Technologies, 2005. Proceedings of the IEEE Symposium on, 2005, pp. 494-
498.
[4]. P. K. Gujarathi and M. V. Aware, "Hardware-in-Loop Simulation of Direct
Torque Controlled Induction Motor," in Power Electronics, Drives and
Energy Systems, 2006. PEDES '06. International Conference on, 2006, pp. 1-
5.
[5] S. Ayasun, S. Vallieu, R. Fischl, and T. Chmielewski, "Electric machinery
diagnostic/testing system and power hardware-in-the-loop studies," in
Diagnostics for Electric Machines, Power Electronics and Drives, 2003.
SDEMPED 2003. 4th IEEE International Symposium on, 2003, pp. 361-366.
[6] Z. Jiang, R, Leonard, R. Dougal, H, Figueroa and A. Monti, “Processor-in-
the-loop simulation, real-time hardware-in-the-loop testing, and hardware
validation of a digitally-controlled, fuel-cell powered battery-charging
station,” IEEE Power Electronics Specialists Conference, pp. 2251-2257,
Aachen, 2004.
[7] L. Bin, A. Monti, and R. A. Dougal, "Real-time hardware-in-the-loop testing
during design of power electronics controls," in Industrial Electronics
Society, 2003. IECON '03. The 29th Annual Conference of the IEEE, 2003,
pp. 1840-1845 Vol.2.
11
[8] M. Steurer, "PEBB based high-power hardware-in-loop simulation facility for
electric power systems," in Power Engineering Society General Meeting,
2006. IEEE, 2006.
[9] X. Wu and A. Monti, "Methods for partitioning the system and performance
evaluation in power-hardware-in-the-loop simulations. Part I," in Industrial
Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE,
2005, pp.251-256
[10] X. Wu and A. Monti, "Methods for partitioning the system and performance
evaluation in power-hardware-in-the-loop simulations - Part II," in Industrial
Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE,
2005, pp.257-262
[11] A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom
Power Devices: Kluwer Academic Publishers, 2002.
[12] B. Singh, K. Al-Haddad, and A. Chand b ra, "A Review of Active Filters for
Power Quality Improvement," IEEE Transactions on Industrial Electronics,
Vol. 46, pp. 960-971, 1999.
[13] D. A. Torrey and M.A.M.Al-Zamel, "Single-phase active power filters for
multiple nonlinear loads," IEEE Transaction on Power Electronics, Vol. 10,
pp. 263-271, May 1995.
[14] A. Ghosh and G. Ledwich, "Load compensating DSTATCOM in weak AC
Systems," IEEE Transaction on Power Delivery, Vol. 18, pp. 1302-1309,
October 2003.
[15] P.Rodriguez, R.Pindado, and J.Bergas, "Alternative topology for three-phase
four-wire PWM converters applied to a shunt active power filter," in IECON
02 2002, pp. 2939 - 2944
[16] B. Singh, K. Al-Haddad, and A. Chandra, "A New Control Approach to
Three-phase Activt: Filter for Harmonics and Reactive Power
Compensation," IEEE Transactions on Power Systems, vol. 13, pp. 133-138,
February 1998.
[17] G. Ledwich and P. Doulai, "Control techniques for active power filters," in
IEE International Conference on Advances in Power System Control,
Operation and Management, Hong Kong, 1991, pp. 582 - 58.
12
[18] X. Dianguo, G. Jianjun, L. Hankui, and G. Maozhong, "Improved Hysteresis
Current Control for Active Power Filter," in IEEE International Symposium
on Industrial Electronics, ISIE '03., 2003, pp. 836 - 840
[19] A. B. Rey, S. de Pablo, J. M. Ruiz, and J. A. Ravelo, "A novel current control
strategy for PWM inverters using the sliding mode techniques," in Power
Electronics Congress, 2000. CIEP 2000. VII IEEE International, 2000, pp.
276-279.
[20] S. Zabihi and Firuz Zare, "Active Power Filters with Unipolar Pulse Width
Modulation to Reduce Switching Losses," in International Conference on
Power System Technology: IEEE, 2006
[21] L. Malesani and P. Tenti, "A novel hysteresis control method for current-
controlled voltege-source PWM inverters with constant modulation
frequency," IEEE Transactions on Industry Applications, Vol. 26, pp. 88-92,
Jan/Feb 1990.
[22] H. Pinheiro, A. S. Martins, and J. R. Pinherio, "A sliding mode controller in
single phase voltage source inverters," in 20th International Conference on
Industrial Electronics, Control and Instrumentation, IECON '94, 1994, pp.
394-397.
[23] P. S. Ninkovic, "A Novel Constant-frequency hysteresis current control of
PFC converters.," in IEEE International Symposium on Industrial Electronics
( ISIE 2002), 2002, pp. 1059-1064.
[24] S. Buso, S. Fasolo, L. Malesani, and P. Mattavelli, "A Dead-Beat Adaptive
Hysteresis Current Control," IEEE Transactions on Industry Applications,
Vol. 36, pp. 1174-1180, July/Aug 2000.
[25] B. Nicolas, M. Fadel, and Y. Cheron, "Fixed-frequency sliding mode control
of a single phase voltage cource inverter with input filter," in IEEE
International Symposium on Industrial Electronics, (ISIE '96) 1996, pp. 470-
475.
[26] T. Noguchi, H. Kodachi, and I. Saito, "Performance improvement of current-
controlled PWM inverter by means of dithering," in Power Electronics and
Drive Systems, 2001. Proceedings., 2001 4th IEEE International Conference
on, 2001, pp. 390-395 vol.1.
13
[27] J. Zeng, C. Yu, Q. Qi, Z. Yan, Y. Ni, B.L.Zhang, S. Chen, and F. F. Wu, "A
novel hysteresis current control for active power filter with constant
frequency," Electric power systems research, vol. 68, pp. 75-82, 2 August
2003.
[28] G. H. Bode and D. G. Holmes, "Implementation of Three Level Hysteresis
Current Control for a Single Phase Voltage Source Inverter," in Power
Electronics Specialists Conference, 2000, pp. 33-38.
[29] F. Zare and G. Ledwich, "A hysteresis current control for single-phase
multilevel voltage source inverters: PLD implementation," IEEE Transaction
on Power Electronics, Vol. 17, pp. 731 - 738 September 2002.
[30] L.Malesani, P.Mattavelli, and P.Tomasin, "Improved constant-frequency
hysteresis current control of VSI inverters with simple feed-forward
bandwidth prediction," in Industry Applications Conference, Thirtieth IAS
Annual Meeting, IAS '95, 1995, pp. 2633-2640.
[31] L. Malesani, P. Mattavelli, and P. Tomasin, "High-performance hysteresis
modulation technique for active filters," IEEE Transaction on Power
Electronics, Vol. 12, pp. 876-884, September 1997.
[32] Z. Chen, F. Blaabjerg, and J. K. Pedersen, "A study of parallel operations of
active and passive filters," in Power Electronics Specialists Conference,
2002. pesc 02. 2002 IEEE 33rd Annual, 2002, pp. 1021-1026 vol.2.
[33] S. Bhattacharya, D. M. Divan, and B. B. Banerjee, "Control and reduction of
terminal voltage total harmonic distortion (THD) in a hybrid series active and
parallel passive filter system," in Power Electronics Specialists Conference,
1993. PESC '93 Record., 24th Annual IEEE, 1993, pp. 779-786.
[34] J. C. Das, "Passive filters-potentialities and limitations," in Pulp and Paper
Industry Technical Conference, 2003. Conference Record of the 2003
Annual, 2003, pp. 187-197.
[34] H. Komurcugil and O. Kukrer, "A robust current control strategy for single-
phase shunt active power filters," in Industrial Electronics Society, IECON
'03. , 2003, pp. 2277 - 2281.
[35] C.N.Bhende, S.Mishra, and S.K.Jain, "TS-fuzzy-controlled active power
filter for load compensation," IEEE Transaction on Power Delivery, vol. 21,
pp. 1459-1465, July 2006.
14
[36] A. Hamadi, K. Al-Haddad, S. Rahmani, and H. Kanaan, "Comparison of
Fuzzy logic and Proportional Integral ControlIer of Voltage Source Active
Filter Compensating Current Harmonics and Power Factor," in IEEE
International Conference on Industrial Technology (ICIT), 2004, pp. 645 -
650
[37] A. Jaya Laxmi, G. Tulasi Ram Das, K. Uma Rao, and K. Rayudu,
"Comparison of PI and ANN control strategies of unified shunt series
compensator," in Power India Conference India, 2006.
[39] E. Arango, J. Calvente, R. Giral, A. E. Aroudi, and L. Martínez-Salamero,
"LQR Control of an Asymmetrical Interleaved Dual Boost Converter
Working in Inherent DCM," in ISIE 2005, Dubrovnik, Croatia: IEEE, 2005.
[40] Hardware-In-the-Loop Definition, from the website,
"http://www.precisionmba.com/hardware_in_the_loop.htm" on 28 october
2008.
[41] F. Zare, "Multilevel Converter Structure and Control", PhD thesis,
Queensland University of Technology, Brisbane, Australia, 2001.
[42] L. Dawes, " Role of Soil Physical and Chemical Characteristics and
Landscape Factors in Defining Soil Behaviour Under Long Term Wastewater
Dispersal", Queensland University of Technology, Brisbane, Australia, 2006.
15
CHAPTER 2
A HYBRID DISCONTINUOUS VOLTAGE CONTROLLER FOR DSTATCOM APPLICATIONS
SACHIN GOYAL, ARINDAM GHOSH AND GERARD LEDWICH
School of Engineering Systems
Queensland University of Technology
Published: IEEE PES General Meeting, USA, 2008.
16
Abstract −−−− This paper proposes a hybrid discontinuous control methodology for a
voltage source converter (VSC) based distribution static compensator (DSTATCOM)
connected to a 3-phase distribution system. It is assumed that the DSTATCOM
controls the point of common coupling (PCC) voltage. An LC output filter is
connected at the output of the VSC. With the help of both filter inductor current and
filter capacitor voltage control, the voltage across the filter capacitor is controlled.
Based on the voltage error, the control is switched between voltage and current
control mode. In this scheme, an extra diode state is used that makes the VSC output
current discontinuous. This diode state reduces the switching losses because half of
the total switching occurs at nearly zero converter current. The effects of different
source conditions on voltage at PCC are studied. Voltage angle at PCC is controlled
using a PI controller. Simulation studies are performed using PSCAD to validate the
efficacy of the proposed controller.
Keywords − DSTATCOM, discontinuous current, hybrid control, LC output filter.
2.1. Introduction
Power quality is a concern for sensitive loads (consumers) like semiconductor
manufacturing plants, hospitals, financial institutes or food processing plants as a
voltage dip for even short duration can cost them a substantial amount of money.
Most of the power quality problems originate in distribution system. Installation of a
distribution static compensator (DSTATCOM) at consumer premises is an effective
solution of these problems [1]-[2]. A DSTATCOM is a voltage source converter
(VSC) based shunt device, usually supported by short-time energy stored in the dc
capacitor(s). Various kinds of structure and control methods are used for
compensators [3]. In this paper, voltage at point of common coupling (PCC) is
controlled and made balanced so that source current can be balanced, even when the
load is unbalanced and nonlinear. To prohibit the switching frequency components of
the VSC to the PCC voltage, an LC filter is connected at the output of VSC. A
simple hysteresis current control (HCC) will fail to track the capacitor voltage
reference. Hence a hybrid discontinuous feedback control law is proposed for the
combined VSC-LC filter system.
17
In this paper, the discussion is based on the structure and control of a DSTATCOM
that is suitable to compensate the load at the time of sag or swell in source voltage.
Also it can compensate the load at the time of feeder change. To control the power
flow from source, voltage angle at PCC is controlled using a PI controller. This angle
control gives a jump in voltage angle when compensator is connected to the grid. A
solution to avoid this jump is proposed in this paper.
The control strategy described in this paper uses both voltage and current controls. In
voltage control mode modified concept of 3-level HCC is used [4]-[5]. Generally in a
3-level HCC, the output of the inverter is either + Vdc, 0 or − Vdc. In the zero state, a
short circuit path is provided through inverter. In this paper the zero state is modified
by a diode state. In the diode state, all four switches of single phase inverter are
turned off. Filter inductor current is made zero with the help of diodes.
2.2. Voltage Control Structure
Figure 2.1 Single-line diagram of shunt compensation of a load through a feeder.
The scheme of DSTATCOM is shown in Fig. 2.1. In this system, a load that can be
active, passive, unbalanced or nonlinear is connected with a balance voltage source
(Vs) through a feeder. Resistance and inductance of feeder are R and L. A
DSTATCOM that contains a VSC and an LC filter at the output of VSC is used to
18
compensate the load. The VSC is supplied by the dc storage capacitor Cdc. The LC
filter inductance and capacitance are denoted by Lf and Cf respectively and the
resistance Rf indicates the circuit losses. It can be seen from Fig. 2.1 that the voltage
across the filter capacitor Cf is the PCC voltage vt. The aim of this scheme is to
balance the three phase PCC voltages.
2.2.1. The DSTATCOM model
Fig. 2.2 shows the structure of DSTATCOM. It contains three H-Bridge VSCs. All
three VSCs are connected to common DC storage capacitor Cdc. Each VSC is
connected to grid through single phase transformer and a capacitor. The three single
phase transformers are used to provide isolation [2]. Leakage inductance of
transformer Lf and the filter capacitor Cf constitute the LC filter for each phase. All
three transformers are connected in star and neutral point is connected to the neutral
of the load or it may be grounded if neutral point of load is not available.
Figure 2.2. Compensator structure used in which three separate VSCs are supplied from a common dc storage capacitor.
As far as structure of single phase converter is concern, it has four switches with
anti-parallel freewheeling diode. In the later part of this paper, we shell see that
output current of the converter, i.e., filter inductor current may be discontinuous. So
the diodes’ rating must be same as the IGBTs’ rating.
19
2.2.2. The Reference generation
The aim the scheme is to balance the PCC voltages. Note that the compensator
(DSTATCOM) is supplied by a dc storage capacitor, which can only provide
temporary ride through during transients. Hence the power demanded by the load and
the losses in the compensation circuit must be supplied by the source. The voltage
angle at PCC − δ is set in such a manner that the source supplies the total power and
loss requirements.
Let us define
δ−∠=°∠= 21 and 0 VVVV ts (2.1)
Then from Fig. 2.1, we get the following expression for the power entering the PCC
from the source
( )[ ]δδ sincos 121222 XVVVRXR
VP +−
+= (2.2)
where X = ωL. If V1 ≈ V2, the first term inside the bracket on the right hand side of
(2) is negative. However, its influence on the positive valued second term is
negligible as R << X. Now suppose a voltage sags occurs causing V1 to drop. If the
DSTATCOM holds V2 constant, the first term becomes more negative. Let us
stipulate that the power to the load must remain unchanged. Hence δ must increase
not only to offset the first term, but also to maintain the power flow constant.
Similarly during a voltage swell in V1, the angle δ must reduce in order to hold the
power constant.
For example, let us assume that V1 = V2 = 11 kV (L-L), R = 6.05 Ω, X = 36.2854 Ω
and δ = 20°. Then the three-phase power, calculated from (1.2) is 1.077 MW. Now
suppose a symmetrical sag in supply voltage reduces V1 to 9 kV (L-L). Then in order
to maintain the power flow constant, δ must be equal to 27.5°. Similarly if V1
becomes 12 kV (L-L), δ should be around 17.3° to hold the power constant.
20
Therefore in order to keep the power constant, δ must be controlled. If the power
flow is constant, the dc capacitor voltage Vdc remains constant since it is absorbing
the required amount of power to replenish the losses. A drop in the capacitor voltage
indicates as voltage sag as it tries to supply power to the load. The capacitor voltage
increases during a voltage swell as the increased power from the source is drawn by
the DSTATCOM. Therefore the power drawn from the source can be controlled by
regulating the capacitor voltage around its reference value. This gives the following
capacitor voltage control loop
∫+= edtKeK Ipδ (2.3)
where e = Vcref − Vdc, Vcref being reference voltage for the dc capacitor. Using this δ
and reference peak voltage at PCC (V2m), three phase reference voltages are
generated for voltage controller. These references are
( )( )( )
°+−=
°−−=
−=
120sin
120sin
sin
2
2
2
δωδωδω
tVv
tVv
tVv
mcref
mbref
maref
(2.4)
With the help of voltage controller, the voltage at the PCC is kept balanced.
2.3. Strategy for Hybrid Discontinuous Control
If our source voltages are balanced sinusoids and we make PCC voltage also balance
then source current will also be balance. The harmonic and unbalanced components
of the load currents will be supplied by compensator. However any unbalance or
distortion in the source voltages will be reflected in the source currents since the
PCC voltages will remain balanced sinusoidal. In this section, we shall introduce a
new control methodology to track the PCC voltage references (1.4). This control
requires fewer of switching events, thereby incurring lower switching losses
compared to hysteretic control.
This control is a combination of voltage and current control in which all the three
states (+ 1, − 1 and 0) of inverter are used. In + 1 and − 1 states, the output voltages
21
of inverter are + Vdc and − Vdc respectively and the 0-state is the diode state where all
four switches are turned off. In the diode state, with the help of diode, the inductor
current is forced to zero. This state introduces discontinuity in the converter output
current.
1S 2S
3S 4S
lkR cfv
Figure 2.3. VSC scheme to control capacitor voltage.
Let us consider a single phase H-bridge converter with an LC filter as shown in Fig.
2.3. The leakage in the capacitor is denoted by a high resistance Rlk. It is desired that
the VSC tracks a reference capacitor voltage with the help of current and voltage
control. For this, two zones are defined as shown in Fig. 2.4. If capacitor voltage is in
Zone 1, the VSC is operated in current control mode and if the voltage is in Zone 2
then it is operated in voltage control mode. Both these variables are controlled in
hysteresis bands. In Zone 1, a hysteresis band limit is set for the inductor current (i f)
and in Zone 2, hysteresis band is set for the capacitor voltage (vcf).
Figure 2.4. Two zones for voltage control.
DC Voltage Tracking: If the reference of the capacitor voltage is positive, then
switching in Zone 1 will be defined as
0 then If 41 =≥ −Shi if (2.5)
22
where hi is the current hysteresis band. This implies that if the current i f is greater
than or equal to hi, turn all the switches off. However, if this current is less than zero,
apply positive voltage at the VSC output, i.e.,
0 and 1 then 0If 3,24,1 =+=< SSi f (2.6)
Let the upper and lower voltage hysteresis bands be denoted by huv and hlv
respectively. Then for Zone 2, we have the following switching logic
0 then If 41 =+≥ −Shvv uvrefcf (2.7)
0 and 1 then If 3,24,1 =+=−≤ SShvV lvrefcf (2.8)
For example, let assume vref = 8 kV (dc), hi = 0.4 kA, huv = 0.02 kV and hlv = 0.1 kV.
Value of huv should be less then hlv because even if all four switches are turned off,
the capacitor voltage increase until i f becomes zero and the capacitor voltage
becomes more then vref + huv. If huv and hlv are same, a steady state error will always
be there. To eliminate this error huv should be less then hlv. Fig. 2.5 shows the
tracking of capacitor voltage when vref is positive. It can be seen that that when the
voltage rises to its reference, the control is in Zone 1, where the current is switched
rapidly. Once the voltage reaches the reference value, the control is switched to zone
2 to maintain the output voltage. During this time, the current switching will be
dependent on the leakage resistance of the capacitor. If the resistance is small, the
leakage will be more, resulting in higher current switching. The same scheme can
also be applied when vref is negative. This is not shown here.
AC Voltage Tracking: To track a sinusoidal capacitor voltage reference, one cycle
is divided in four parts as shown in Fig. 2.6. Regions 1 and 3 can be tracked using the
switching schemes explained above. However for Regions 2 and 4 separate
switching scheme needs to be implemented because the capacitor discharges in these
regions.
23
0 0.005 0.01 0.015 0.02 0.025 0.030
2
4
6
8
10
Time (s)V
olta
ge
(KV
)
Capacitor Voltage
Voltage control mode
Current control mode
(a)
0 0.005 0.01 0.015 0.02 0.025 0.03-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (s)
Cu
rren
t (K
A)
Inductor Current
(b)
Figure 2.5. (a) Capacitor voltage and (b) Inductor current during DC tracking.
0 0.005 0.01 0.015 0.02-1.5
-1
0
1
1.5
Time
Mag
. Region 1 Region 2
Region 3 Region 4
Figure 2.6. Four regions of one cycle of a sinusoidal wave.
Two zones are also defined for Regions 2 and 4 − one for current control and the
other for voltage control. For Region 2, switching in Zone 1 is
0 and 1 then 0If 4,13,2 =+=≥ SSi f (2.9)
0 then If 41 =≤ −Shi if (2.10)
The switching for Zone 2 are:
24
0 and 1 then If 4,13,2 ==+≥ SShvv lvrefcf (2.11)
0 then If 41 =−≤ −Shvv uvrefcf (2.12)
Fig. 2.7 shows the sinusoidal tracking of capacitor voltage and inductor current. The
tracking is discontinuous in nature.
Example 2.1: In this example, a passive load is connected to the VSC through an LC
filter. For a passive load, a diode state is required for all the regions shown in Fig.
2.6. In Regions 1 and 4, only + Vdc is required, while in Regions 2 and 3, only − Vdc
is required. Note that there is no need to utilize − Vdc in Regions 1 and 4 and + Vdc in
Regions 2 and 3 (load should not provide rapid discharging path to capacitor).
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-10
-5
0
5
10
Time (s)
Vol
tage
(K
V)
Reference and Capacitor Voltage
(a)
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-5
-2.5
0
2.5
5
Time (s)
Cu
rren
t (K
A)
Inductor Current
(b)
Figure 2.7. (a)Capacitor voltage and (b) Inductor current for AC voltage tracking. Hence the scheme described above produces very accurate tracking. However when
the load is active or when a passive load provide a rapid discharging path for the
capacitor, the − Vdc state may also be required in Regions 1 and 4 while the + Vdc
state may be required in Regions 2 and 3 depending on the relative phase difference
25
between the VSC output voltage and the system internal emf. This may increase the
switching frequency of the VSC and lead to continuous conduction mode of the
inductor current. Fig. 2.8 shows the load voltage and inductor current for a passive
load.
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-1.5
-1
-0.5
0
0.5
1
1.5
Time (s)
Vo
ltag
e (K
V)
Capacitor Voltage
(a)
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-4
-2
0
2
4
Time (s)
Cu
rren
t (K
A)
Inductor Current
(b)
Figure 2.8. (a) Capacitor voltage and (b) Inductor current for Example 2.1
For tracking in Region 1 with an active load, the switching control is defined as
follows. If capacitor voltage is in Zone 1, then
0 then If 41 =≥ −Shi if (2.13)
0 and 1 then 0If 3,24,1 ==< SSi f (2.14)
But if the capacitor voltage is in Zone 2, then
0 and 1 then If 3,24,1 ==−≤ SShvv lvrefcf (2.15)
0 then and If 41 =+<−> −Shvvhvv uvrefcflvrefcf (2.16)
26
1 and 0 then If 3,24,1 ==+≥ SShvv uvrefcf (2.17)
The switching for Region 3 will be the same as above except that − Vdc state will be
chosen instead of + Vdc state.
The switching for Region 2 is defined as follows. Switching in Zone 1 is
0 and 1 then 0If 4,13,2 ==≥ SSi f (2.18)
0 then If 41 =≤ −Shi if (2.19)
For Zone 2,
0 and 1 then If 4,13,2 ==+≥ SShvv lvrefcf (2.20)
0 then andIf 41 =−>+< −Shvvhvv uvrefcflvrefcf (2.21)
1 and 0 then If 4,13,2 ==−≤ SShvv uvrefcf (2.22)
Switching for Region 4 can be obtain in the same way as in Region 2, the only
difference being the capacitor discharges from negative to zero instead of positive to
zero.
2.4. Compensator Performance
Once the reference for PCC voltage is computed from (1.4), the PCC voltage can be
tracked using the controller described in Section III. This is illustrated with the help
of the following example.
Example 2.2: Consider the system shown in Fig. 2.1. The system and DSTATCOM
parameters chosen are given in Table 2.1. It is assumed that the source voltage is
balanced. The load is both unbalanced (passive RL) and nonlinear (three-phase
rectifier supplying an RL). The compensator is connected to grid at time t = 0. The
source currents, load currents, PCC voltages and the angle of the PCC voltage are
shown in Figs. 2.9 (a-d) respectively. The initial transient lasts about 0.1 s. During
this time, the dc capacitor charges. Once the dc capacitor voltage reaches its desired
27
level, the angle of the PCC voltage settles to its steady state level and the initial
transient dies out. This is evident from all the plots of Fig. 2.9.
TABLE 2. 1. SYSTEM PARAMETERS
System Quantities Values
Systems Frequency (ω) 100π rad/s (50 Hz)
Source voltage (Vs) 11 kV rms (L-L)
Feeder impedance (Rs + jXs) 6.05 + j36.26 Ω
Unbalanced Load
The subscripts a, b and c
denote the three phases.
Zla = 48.2 + j94.2 Ω
Zlb = 12.2 + j31.4 Ω
Zlc = 24.2 + j60.47 Ω
Nonlinear Load
Contains a three-phase
rectifier that supplies
100 + j31.4 Ω
DSTATCOM
Loss (Rf)
Filter capacitor (Cf)
Three single-phase
transformers are rated at
3 Ω
50 µF
1 MVA, 3 kV/11 kV,
leakage inductance (Lf)
of 2.5%
Capacitor Control Loop
DC capacitor
Reference voltage (vcref)
Proportional gain (KP)
Integral gain (KI)
10000 µF
3.5 kV
-0.7
0.1
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Curr
ent (K
A)
Three Phase Source Currents
(a)
28
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Curr
ent (K
A)
Load Currents
(b)
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2-10-9
-5
0
5
910
Time (s)
Volta
ge (K
V)
PCC Voltages
(c)
0 0.05 0.1 0.15 0.2 0.25-140
-120
-100
-80
-60
-40
-20
Time (s)
Deg
ree
PCC Voltage Angle
(d)
Figure 2.9. Compensation of the unbalanced nonlinear load without precharged capacitor.
Once the load and the compensator are connected to the grid at time t = 0, the PCC
voltage angle starts changing as shown in Fig. 2.9 (d). This angle changes
significantly in the transient period. Such a rapid change in angle may not be
desirable to some loads. To overcome this problem, the dc capacitor should be pre-
charged before connecting the DSTATCOM to the grid. To charge the dc capacitor,
the same VSC that is used as the compensator is used. At the time of pre-charging,
the controller is switched off and anti-parallel diodes of the VSC are used as an un-
controlled rectifier. This pre-charging scheme is shown in Fig. 2.10, which contains
29
two circuit breakers. The load is connected to the grid through the circuit breakers
CB1 and filter capacitor is connected to the rest of the DSTATCOM through CB2.
Initially controller is switched off to charge the dc capacitor. During this time, CB1
and CB2 are kept open. To limit the charging current of dc capacitor a resistance is
connected in series with dc capacitor. Once the capacitor voltage reaches the desired
value, the series resistance is bypassed (short-circuited) with the help of switch SC1
and CB1 and CB2 are closed subsequently.
Figure 2.10. Schematic diagram of the compensation scheme to pre-charge the dc capacitor.
Using the above pre-charging scheme, capacitor is charged for initial 0.35 s and
during this time CB1, CB2 and switch SC1 is kept open. It can be seen from the dc
capacitor voltage of Fig. 2.11 (a) that the capacitor voltage attains a near steady state
value at t = 0.35 s and hence further pre-charging is not possible. However once
CB1, CB2 and SC1 are closed, the capacitor voltage and PCC voltage angle settle
quickly without deviating much from their pre-charged values as evident from Fig.
2.11 (a) and ( b). During the charging, phase-a of the PCC voltage is shown in Fig.
2.11 (c). It can be seen that this voltage does not collapse during this period. Hence,
the loads that may be connected upstream from the PCC will not get affected much.
Also note that the output of the angle controller (1.3) changes rapidly from − 140°
towards its steady state value due to the controlled charging of the dc capacitor.
However since the PCC voltage is not controlled by the DSTATCOM during the pre-
charging time, the angle change does not have any effect on the load or the PCC
voltage. Once the breakers CB1 and CB2 are closed, the load currents start flowing
30
(Fig. 2.11 d) and the PCC voltages quickly attain its steady state magnitude (Fig.
2.11 c). The advantage of this pre-charging method is that it does not require any
extra hardware other than the switch SC1 and the resistor connected in series with
the dc capacitor. The presence of the resistor will increase losses. However it will not
have much consequence since the charging time is very small.
Example 2.3: To investigate the behavior of the controller at the time of a voltage
sag in the source voltage, let us consider the same system as given in Table 2.1. A
voltage sag occurs at t = 0.25 sec in which the source voltage drops to 7 kV (L-N,
peak) from the nominal value of 9 kV. The sag is removed at t = 0.45 sec. It is
desired that the PCC voltage is maintained at 8 kV (L-N, peak). The three-phase
PCC voltage is shown in Fig. 2.12 (a). It can be seen from this figure that there is no
appreciable change in the magnitude of the PCC voltage during the sag or its
removal. From (1.2), it is clear that if source voltage
Time (s)Capacitor Pre-chargingDSTATCOM Connection to Grid
0 0.1 0.2 0.3 0.35 0.4 0.5 0.6 0.70
0.5
1
1.5
2
2.5
3
Time (s)
Volta
ge (k
V)
DC Capacitor Voltage
Capacitor Pre-charging
DSTATCOM Connection to Grid
(a)
0 0.1 0.2 0.3 0.35 0.4 0.5 0.6 0.7-140
-120
-100
-80
-60
-40
-20
Time (s)
Deg
ree
Output of Angle Controller
DSTATCOM Connection Point
(b)
31
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-10
-5
0
5
10
Time (s)Volta
ge
(kV)
PCC Voltage (Phase A)
(c)
0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Cur
rent
(kA)
Load Currents
(d)
Figure 2.11. (a) DC capacitor voltage, (b) voltage angle at PCC, (b) PCC voltage and (c) load currents when the dc capacitor is pre-charged.
reduces then δ should increase to maintain the same level of power flow. Fig. 2.12
(b) shows the PCC voltage angle. It starts decreasing at t = 0.25 s, resulting in
increase in δ. The angle returns to its original value once the sag is removed. The
three-phase source currents are shown in Fig. 2.12 (c). It can be seen these currents
increase during the voltage sag to maintain the constant amount of power flow.
Example 2.4: The behavior of the system is investigated for a swell in the source
voltage, which occurs at t = 0.25 s. The swell is removed at t = 0.45 s. The same
system as given in Table 2.1 is considered here also. During the swell, the source
voltage rises to 11 kV (L-N, peak). It can be seen from Fig 2.13 that magnitude of
PCC voltage remains constant while its angle increases to maintain constant power
flow.
32
0.2 0.25 0.3 0.35 0.4 0.45 0.5-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)
Volta
ge
(KV
)
PCC Voltages
(a)
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6-120
-100
-80
-60
-40
-20
0
Time (s)
Deg
ree
Voltage Angle at PCC
Sag StartSag End
(b)
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Time (s)
Curr
ents
(K
A)
Three Phase Source Current
(c)
Figure 2.12. (a) PCC voltages, (b) voltage angle and (c) source currents for Example 2.3.
0.2 0.25 0.3 0.35 0.4 0.45 0.5-10
-5
0
5
10
Time (s)
Voltag
e (K
V)
PCC Voltages
(a)
33
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-100
-80
-60
-40
-20
0
Deg
ree
Voltage Angle at PCC
Swell EndSwell Start
Time (s)
(b)
Figure 2.13. (a) PCC voltages and (b) voltage angle for Example 2.4.
Example 2.5: Unsymmetrical sag/swell is a common occurrence in power systems.
In this example, we shall investigate the system behavior during such an occurrence.
Let us consider the same system as given in Table 2.1. However the peak of the
instantaneous source voltages are changed as 10kV, 9kV and 8kV (L-N, peak) for the
phases a, b and c respectively at t = 0.3s and 8kV, 9kV and 10kV (L-N, peak) for the
phases a, b and c respectively at t = 0.5sec. It is desired that the DSTATCOM
maintains the peak of the PCC voltage at 9 kV. These voltages are shown in Fig. 2.14
(a). The PCC voltage angle is shown in Fig. 2.14 (b). It can be seen that it almost
remains unchanged. Since the PCC voltages are held constant, the power requirement
of the load remains unchanged. Also since the changes in the source voltages are
symmetrical (the dip in one phase is equal to the rise in the other), the angle must
remain constant for constant power. The source currents are shown in Fig. 2.14 (c). It
can be seen that they are unbalanced in sympathy with the source voltages.
0.3 0.31 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4-10
-5
0
5
10
Time (s)
Voltag
e (k
V)
PCC Voltages
(a)
34
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6-55
-50
-45
-40
-35
-30
-25
-20
Time (s)
Deg
ree
PCC Voltage Angle
Voltage Change Points
(b)
0.3 0.31 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
Time (s)
Curr
ent (k
A)
Three Phase Source Currents
(c)
Figure 2.14. (a) PCC voltages (b) voltage angle (c) and source currents for Example 2.5.
Example 2.6: Let us now consider the case when there is a change in the feeder
impedance. To investigate this case, the system in Table 2.1 is altered by introducing
a 3-phase phase rectifier that is connected half between the source and the PCC as
shown in Fig. 2.15. This load is connected to the feeder through a circuit breaker
(CB1), which is closed at time t = 0.3 s. The results are shown in Fig. 2.16. With the
introduction of the rectifier load, some amount of power is supplied by the source to
it. However since the load power has to remain constant, the PCC voltage angle must
recede to maintain the power flow to the load. This is evident from Fig. 2.16 (a). The
magnitude of the PCC voltage remains constant as evident from Fig. 2.16 (b).
However the currents (is) supplied by the source are now distorted, but balanced due
to the rectifier load as shown in Fig. 2.16 (c).
35
Figure 2.15 PCC Feeder switching scheme for Example 2.6
0.2 0.25 0.3 0.35 0.4 0.45 0.5-100
-90
-80
-70
-60
-50
-40
-30
-20
Time (s)
Deg
ree
PCC Voltage Angle
Feeder Switch
(a)
0.25 0.3 0.35 0.4 0.45-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)
Volta
ge
(KV
)
PCC Voltages
(b)
36
0.48 0.482 0.484 0.486 0.488 0.49 0.492 0.494 0.496 0.498 0.5-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Time (s)
Cur
rent
(kA
)
Three Phase Source Currents
(c)
Figure 2.16 (a) PCC voltage angle, (b) PCC voltages and (c) source currents for Example 2.6.
2.5. Conclusions
This paper presents a new switching control strategy for voltage control in the
presence of an LC filter. The use of the LC filter removes the effects of switching
frequency components on the output voltage better than the traditional L filter.
However a simple hysteretic band control is not suitable in this situation as it will
lead to instability. To overcome this situation, a discontinuous hybrid control strategy
is proposed here which reduces the switching losses. Due to the use of the diode
state, half of the switching events occur when the inverter current is zero or nearly
zero, which makes half of the switching lossless. Because of this advantage, a higher
switching frequency can be chosen, which will result in better tracking of higher
frequency waveforms. Alternatively, the size of the inverter can be reduced.
This improved control strategy has been applied to a DSTATCOM operating in a
voltage control mode. The advantage of the proposed control method is that it is
robust to LC parameter variations and does not need a redesign for the changes in the
remainder of the power system, DSTATCOM parameters and operating conditions.
It has been shown that the DSTATCOM is able to hold the PCC voltage constant in
the face of various system disturbances and load changes. A simple angle control has
been used for the DSATACOM and a pre-charging scheme to avoid a phase jump
has been designed.
37
Acknowledgement
The authors thank the Australian Research Council (ARC) for the financial support
for this project through the ARC Discovery Grant DP 0774092.
References
[1] A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom Power
Devices: Kluwer Academic Publishers, 2002.
[2] A. Ghosh and G. Ledwich, "Load compensating DSTATCOM in weak AC
Systems," IEEE Transaction on Power Delivery, vol. 18, pp. 1302-1309, October
2003.
[3] B. Singh, K. Al-Haddad, and A. Chandra, "A Review of Active Filters for Power
Quality Improvement," IEEE Transaction on Industrial Electronics, vol. 46, pp.
960-971, 1999.
[4] G. H. Bode and D. G. Holmes, "Implementation of Three Level Hysteresis
Current Control for a Single Phase Voltage Source Inverter," in Power
Electronics Specialists Conference, PESC’00, pp. 33-38, 2000.
[5] F. Zare and G. Ledwich, "A Hysteresis Current Control for Single-Phase
Multilevel Voltage Source Inverters: PLD implementation," IEEE Transaction
on Power Electronics, vol. 17, pp. 731-738, September 2002.
[6] Z. Chen, F. Blaabjerg, and J. K. Pedersen, "A study of parallel operations of
active and passive filters," in Power Electronics Specialists Conference,
PESC’02, pp. 1021-1026, 2002.
[7] L. Malesani, P. Mattavelli, and P. Tomasin, "High-performance hysteresis
modulation technique for active filters," IEEE Transaction on Power Electronics,
vol. 12, pp. 876-884, September 1997.
[8] S. I. Hamasaki and A. Kawamura, "A Novel Method for Active Filter Current
Regulation Using Deadbeat Control," Electrical Engineering in Japan, vol. 145,
pp. 67-77, 2003.
38
CHAPTER 3
ACTIVE POWER FLOW CONTROL IN A DISTRIBUTION SYSTEM USING DISCONTINUOUS
VOLTAGE CONTROLLER
SACHIN GOYAL, ARINDAM GHOSH AND GERARD LEDWICH
School of Engineering Systems
Queensland University of Technology
Published: Electric Power Systems Research, 2008.
39
Abstract – This paper proposes a hybrid discontinuous control methodology for a
voltage source converter (VSC), which is used in an uninterrupted power supply
(UPS) application. The UPS controls the voltage at the point of common coupling
(PCC). An LC filter is connected at the output of the VSC to bypass switching
harmonics. With the help of both filter inductor current and filter capacitor voltage
control, the voltage across the filter capacitor is controlled. Based on the voltage
error, the control is switched between current and voltage control modes. In this
scheme, an extra diode state is used that makes the VSC output current
discontinuous. This diode state reduces the switching losses. The UPS controls the
active power it supplies to a three-phase, four-wire distribution system. This gives a
full flexibility to the grid to buy power from the UPS system depending on its cost
and load requirement at any given time. The scheme is validated through simulation
using PSCAD.
Keywords −−−− UPS, discontinuous current, hybrid control, LC output filter and power
flow control.
3.1. Introduction
The power quality issues such as harmonics, unbalancing, voltage sag/swell have
gained considerable attention over the last few years. In addition, the concern for
global warming has seen considerable development in the distributed generation
(DG) technology in the recent time. An uninterruptible power supply (UPS) can
provide solution for the power quality problem, while supplying clean power from
DGs at the same time.
Usually UPSs are used to provide battery back up to computers and other data
processing devices. They can be off-line type in which they remain idle until power
failure occurs and start supplying power thereafter. The on-line type UPS
continuously powers the protected load from its reserve while simultaneously
replenishing the reserve by drawing power from the utility supply. A bi-mode UPS
uses the ac-dc rectification for battery charging [1]. It then seamlessly picks up the
load once a power failure occurs. Various configurations of UPS are reported in [2].
40
In [3], the design of an LC filter that is connected at the output of the UPS is
discussed.
In this paper, the function of the UPS has been extended. It is assumed that the UPS
is supplied by a distributed generator. The DG can be a PV stack or fuel cell stack [4]
or battery which supplies the dc bus of the VSC connecting the UPS to the ac grid. It
is also possible to use PV or fuel cell to charge batteries that constitute the dc bus [5].
It is assumed that the UPS is connected at the point of common coupling (PCC) of
the utility and a major load center. The UPS is then can be controlled in two different
modes. In Mode-1, the utility supplies a constant power to the load and the remaining
power comes from the UPS. In Mode-2, the UPS supplies a constant power to the
load and the remaining power comes from the utility. An interchange between the
modes can occur instantaneously. However, in both the modes, the UPS provides a
balanced voltage at the PCC [6], thereby cancelling out any unbalance and harmonic
content of the load and therefore enhancing the power quality of the distribution
system.
Two different VSC control strategies are considered in this paper. The first strategy,
proposed in this paper, uses both voltage and current control modes. In the voltage
control mode, the modified concept of 3-level hysteretic current control (HCC) given
in [7, 8] is used. Generally in a 3-level HCC, the output of the converter is either +
Vdc, 0 or − Vdc. In the zero state, a short circuit path is provided through converter. In
this paper, the zero state is modified by a diode state. In the diode state, all four
switches of a single phase converter are turned off. Filter inductor current is made
zero with the help of the diodes. The switching between the current and voltage
control modes is based on the error in PCC voltage. If the error is large, the VSC
operates in the current control mode and it is switched to the voltage control mode as
the error reduces.
The performance of the proposed control strategy is compared with a 3-level state
feedback controller [9, 10] for comparison of total harmonic distortion (THD) of
PCC voltage, conduction and switching losses. Extensive simulation studies are
performed using PSCAD and some of the results are presented in the paper.
41
3.2. Power Flow Control
The single-line diagram of a distribution system containing the UPS is shown in
Fig. 3.1. For simplicity, it is assumed that the UPS is supplied from a battery with a
dc voltage of Vdc. The load is assumed to be unbalanced and nonlinear. The load is
connected at the far end of a feeder with an impedance of R + jωL, which is supplied
by a source (vs). An LC filter is connected at the output of VSC, the inductance and
the capacitance of which are denoted by Lf and Cf respectively, while the resistance
Rf indicates the circuit losses. The PCC voltage is denoted by vt.
Figure 3. 1. Single-line diagram of the distribution system containing a UPS.
3.2.1. The UPS model
Fig. 3.2 shows the structure of the UPS. It contains three H-Bridge VSCs. All three
VSCs are connected to common DC storage source Vdc. Each VSC is connected to
grid through single phase transformer and a capacitor. The three single phase
transformers are used to provide isolation [7]. Leakage inductance of transformer Lf
and the filter capacitor Cf constitute the LC filter for each phase. All three
transformers are connected in star and neutral point is connected to the neutral of the
load or it may be grounded if neutral point of load is not available. As far as structure
of single phase converter is concern, it has four switches with anti-parallel
42
freewheeling diode. In the later part of this paper, we shall see that output current of
the converter, i.e., filter inductor current may be discontinuous. So diodes’ rating
must be same as IGBTs’ rating.
The main purpose of the UPS is to maintain a balanced PCC voltage (vt) irrespective
of unbalance and distortion in the load currents. It also controls the magnitude of the
PCC voltage to a pre-specified value even when there is a sag or swell in the source
voltage. To control the power flow according to the modes described in the previous
section, the angle of the PCC voltage must be controlled. Therefore the reference for
the PCC voltage contains a pre-specified magnitude and an angle that is based on
power requirements. The VSC then will have to track this reference voltage in order
to achieve the desired performance.
faC fbC fcC
Figure 3. 2. UPS structure containing three VSCs that are supplied from a common source.
3.2.2. Reference Generation
Let us define the rms source and PCC voltages as
δ−∠=°∠= ttss VVVV and 0 (3.1)
43
Then from Fig. 3.1, we get the following expression for the active and reactive power
entering the PCC from the source
( )[ ]δδ sincos22 sts
ts VXVVR
XR
VP +−
+= (3.2)
( )[ ]δδ sincos22 sts
ts VRVVX
XR
VQ −−
+= (3.3)
where X = ωL. If |Vs| ≈ |Vt|, the first term inside the bracket on the right hand side of
(2.2) is negative. However, its influence on the positive valued second term is
negligible as R << X. It is clear from (2.2) that real power flow can be controlled
using δ. Because if δ is increased or decreased, the amount of real power can be
increased or decreased accordingly. Therefore the reference PCC voltages are given
by
( )( )( )
°+−=
°−−=
−=
120sin
120sin
sin
δωδωδω
tVv
tVv
tVv
tmrefc
tmrefb
tmrefa
(3.4)
where Vtm is a pre-specified magnitude and δ is controlled according to the power
control mode.
3.2.2.1. Mode-1 Control
In this mode, a fixed amount of active power is drawn from the source and the UPS
supplies the balance amount of load requirement. As mentioned before, this can be
achieved by controlling δ. This gives the following power control loop
dt
deKdteKeK s
dssissps ++= ∫δ (3.5)
where es = Psref − Ps, Psref is the reference power which is drawn from the source.
As mentioned earlier, the UPS must regulate the PCC voltage even during changed
source voltage condition. Suppose a voltage sags occurs causing source voltage (|Vs|)
44
to drop. As per requirement, the PCC voltage |Vt| is still held constant. Hence from
(2.2), it is evident that δ must increase in order to maintain the power flow constant.
On the contrary, the angle δ must reduce during swell in the source voltage.
Also, it can be seen from (3.3) that reactive power (Qs) is function of δ. Furthermore,
since |Vs| cos δ < |Vt|, Qs is negative. This means that the UPS supplies reactive
power to the grid. As described above that at the time of sag in source voltage, δ is
increased to maintain Ps constant. This will cause the first term of (3.3) to become
more negative. It means source will draw more reactive power from the UPS during
this condition.
3.2.2.2. Mode-2 Control
In this mode, a fixed amount of power is drawn from the UPS and the source
supplies the balance amount of load requirement. Hence the δ control loop is given
by
dt
deKdteKeK u
duuiuupu ++= ∫δ (3.6)
where eu = Puref − Pu , Puref being the reference power that is required from the UPS.
This controller works in a similar fashion as Mode-1 controller and adjusts the angle
δ to regulate the power flow from the UPS.
3.3. Control Strategies
Many control methodologies are available to track the PCC voltage. In this section,
we shall introduce a new control method and compare with an existing method.
These two methods are discussed below.
3.3.1. Hybrid Discontinuous Control
This control scheme is useful, when an LC filter is connected to the output of a single
phase converter and the instantaneous output voltage of filter capacitor (vcf) needs to
45
be controlled. Fig. 3.3 shows the circuit configuration of a single-phase H-bridge
converter with the LC filter. In this control method, the converter switching decision
is made based on both filter inductor current (i f) and filter capacitor voltage. The
control is switched from one stage that is based on inductor current to second stage
which is based on capacitor voltage according to zones.
1S 2S
3S 4S
cfv
Figure 3. 3. VSC scheme to control capacitor voltage.
The zonal scheme is shown in Fig. 3.4 for a sinusoidal reference voltage with zones
and hysteresis band. The controller is assumed to be in Zone-1 when the error is
large and it is in Zone-2, when the error is small (within the hysteresis band). In
Zone-1, the control decision is made based on filter inductor current. When the error
reduces as a result of the control action of Zone-1, the controller switches to Zone-2,
where the decision will be made depending on filter capacitor voltage. However, in
both the zones, all three states (+1, -1 and 0) of converter are used based upon the
reference voltage. In + 1 state, the converter output becomes + Vdc, which is achieved
by turning on the switches S1 and S4 and turning off the switches S2 and S3 of
Fig. 3.3. Similarly in − 1 state, the converter output becomes − Vdc that can be
achieved by turning on the switches S2 and S3 and turning off the switches S1 and S4.
Usually the 0-state is defined when output voltage of converter is 0 V which is
achieved by closing the pair S1-S2 or S3-S4. But in this paper, the 0-state is modified
be a diode state where all the four switches S1-S4 of the converter are turned off.
During this time, the anti-parallel diodes conduct to bring filter inductor current (i f)
to zero. Once i f becomes zero, the diodes stop conducting and the converter output
voltage becomes equal to filter capacitor voltage (vcf). Because of the major
involvement of the diodes, this state is termed as the diode state in this paper. This
state introduces discontinuity in the converter output current (i f). Since the converter
46
current (i f) becomes zero in the diode state, the next switching for either + 1 or − 1
state, occurs at zero current resulting in a loss free switching.
Figure 3. 4. The two zones voltage control scheme.
To track a sinusoidal capacitor voltage reference, one cycle is divided in four regions
as shown in Fig. 3.5 where each region is divided into two zones explained above.
For each zone, the hysteresis band is defined separately. In Zone-1, the hysteresis
band is defined for the inductor current and in Zone-2 the band is defined for the
capacitor voltage. In Regions 1 and 3, the capacitor is charged for positive and
negative voltage respectively. Thus the switching control logic is very much similar
in Regions 1 and 3. Only reference changes from positive to negative.
0 0.005 0.01 0.015 0.02-1.5
-1
0
1
1.5
Time
Mag
. Region 1 Region 2
Region 3 Region 4
Figure 3. 5. Four regions of one cycle of a sinusoidal wave.
If the reference of the capacitor voltage is in Region 1, then switching in Zone 1 will
be defined as
0 then If 41 =≥ −Shi if (3.7)
47
where hi is the upper current hysteresis band. This implies that if the current i f is
greater than or equal to hi, turn all the switches off. However, if this current is less
than zero which is lower current band limit, apply positive voltage at the VSC
output, i.e.,
0 and 1 then 0If 3,24,1 =+=< SSi f (3.8)
Let the upper and lower voltage hysteresis bands (for Zone-2) be denoted by huv and
hlv respectively. Then for Zone-2, we have the following switching logic
0 then If 41 =+≥ −Shvv uvrefcf (3.9)
0 and 1 then If 3,24,1 =+=−≤ SShvv lvrefcf (3.10)
The switching for Region 3 can also be defined similarly. Since in this region, the
inductor current would be negative, the switching in Zone-1 for Region 3 is defined
as
0 then If 41 =−≤ −Shi if (3.11)
1 and 0 then 0If 3,24,1 =+=> SSi f (3.12)
The switching in Zone-2 would be
0 then If 41 =−≤ −Shvv uvrefcf (3.13)
1 and 0 then If 3,24,1 =+=+≥ SShvv lvrefcf (3.14)
For Regions 2 and 4, a separate switching scheme needs to be implemented because
the capacitor discharges in these regions. While In Region 2, the capacitor discharges
from positive to zero, it discharges from negative to zero in Region 4. The two zones
mentioned above are also defined for Regions 2 and 4, one for current control and
the other for voltage control. For Region 2, switching in Zone-1 is
0 and 1 then 0If 4,13,2 =+=≥ SSi f (3.15)
0 then If 41 =≤ −Shi if (3.16)
48
The switching for Zone-2 is
0 and 1 then If 4,13,2 ==+≥ SShvv lvrefcf (3.17)
0 then If 41 =−≤ −Shvv uvrefcf (3.18)
Similarly the switching in Zone-1 for Region 4 is defined as
1 and 0 then 0If 4,13,2 =+=≤ SSi f (3.19)
0 then If 41 =≥ −Shi if (3.20)
The switching for Zone 2 is
0 then If 41 =+≥ −Shvv uvrefcf (3.21)
1 and 0 then If 4,13,2 ==−≤ SShvv lvrefcf (3.22)
It is to be noted that, in Region 1, even if all four switches are turned off, the
capacitor voltage increases until i f becomes zero forcing the capacitor voltage to
become more than vref + huv. If huv and hlv are chosen to be the same, a steady state
error will always exist. To eliminate this error, huv should be chosen less than hlv.
The filter parameters Lf and Cf, a small value of Lf is chosen for discontinuous mode
of operation until it hits the current limit of the VSC. Small value of inductor helps in
charging the capacitor rapidly. However small value of inductor increases the filter
current, but it can be controlled with the help of controller algorithm. Large inductor
will lead to more and more continuous current at switching and less controlled
capacitor voltage. Large inductor will have more energy stored in it and after closing
the all four switch it will dissipate this energy to capacitor that will result unwanted
voltage rise of capacitor and this voltage rise is uncontrolled which is undesirable. It
must be ensured that the filter inductance Lf and the capacitor Cf do not resonate at
the fundamental frequency. If the filter capacitor resonates with the filter inductance
at a frequency ωr , then we get,
Cfr = 1/ωr2*L f (3.23)
49
Let us assume that this value is equal to Cfo when ωr is equal to the fundamental
frequency (ω). The filter capacitor Cf should never be chosen near Cfo. This can be
achieved by either Cf_>>Cfo or Cf_<<C fo . However, if Cf is very large, the
impedance between the PCC and ground becomes very small resulting in excessive
currents through filter capacitors. Therefore the choice of Cf_>>C fo is invalid. We
must therefore restrict Cf to be much smaller than Cfo.
Example 3.1: In this example, a passive load is connected to the VSC through an LC
filter and it is desired that capacitor voltage tracks the reference voltage
1.0(sin (100πt)). For a passive load, a diode state is required for all the regions
shown in Fig. 3.5. In addition to the 0-state, only + Vdc is required in Regions 1 and
4, while in Regions 2 and 3, only − Vdc is required. Note that there is no need to
impress − Vdc in Regions 1 and 4 and + Vdc in Regions 2 and 3. But if the passive
load is small and it discharges the capacitor rapidly, then + Vdc may be required in
Regions 2 and 3. Hence the scheme described above produces very accurate tracking.
However when the load is active in nature, − Vdc may also be required in Regions 1
and 4 + Vdc may be required in Regions 2 and 3 depending on the relative phase
difference between the VSC output voltage and the back emf.
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-1.5
-1
-0.5
0
0.5
1
1.5
Time (s)
Vol
tag
e (K
V)
Capacitor Voltage
(a)
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-3
-2
-1
0
1
2
3
Time (s)
Cur
rent
(kA
)
Inductor Current
(b)
Figure 3. 6. (a) Capacitor voltage and (b) inductor current for Example 3.1.
50
This may increase the switching frequency of the VSC and lead to continuous
conduction mode of the inductor current. Fig. 3.6 shows the load voltage and
inductor current which is discontinuous in nature for a passive load. Fig. 3.7 shows
the filter inductor current with switching signals for switches S1 and S4. It is clear
from the figure that when switches S1 and S4 are on, the output voltage of VSC is
+Vdc and when these two switches are turned off, all four switches are off because the
switches S2 and S3 were already off. Thus the inductor current reduces and becomes
zero with the help of diode conduction. During the diode conduction, the output
voltage becomes − Vdc and as inductor current becomes zero, the output voltage
becomes equal to filter capacitor voltage (vcf). Since every + 1 or − 1 state is
followed by a diode state, it results in alternate switching at zero current. Hence half
of the total switching is free of losses. Fig. 3.8 shows that one switching edge (either
rising or falling) occurs at almost zero current.
-1
0
1
2
4.29 4.3 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38
x 10-3
-20
-10
0
10
20
Time (s)
Vo
ltag
e (k
V)
Inductor Current
Switching S1,4
VcfVcf+Vdc
Diode state
-Vdc
Diodeconducts
Figure 3. 7. Inductor current with diode state and VSI output voltage.
0.2867 0.2868 0.2869 0.287 0.2871 0.2872 0.2873 0.2874-1
-0.5
0
0.5
1
1.5
2
Time (s)
Filter Inductor Current and Switching
S2S1
Inductor Current (kA)Switching at zero current
Figure 3. 8. Inductor current and switching.
51
For tracking in Region 1 with an active load, the switching control is defined as
follows. If capacitor voltage is in Zone-1, then
0 then If 41 =≥ −Shi if (3.24)
0 and 1 then 0If 3,24,1 ==< SSi f (3.25)
But if the capacitor voltage is in Zone-2, then
0 and 1 then If 3,24,1 ==−≤ SShvv lvrefcf (3.26)
0 then and If 41 =+<−> −Shvvhvv uvrefcflvrefcf (3.27)
1 and 0 then If 3,24,1 ==+≥ SShvv uvrefcf (3.28)
The switching for Region 3 will be the same as above except that − Vdc state will be
chosen instead of + Vdc state.
The switching for Region 2 two is defined as follows. The switching in Zone-1 is
0 and 1 then 0If 4,13,2 ==≥ SSi f (3.29)
0 then If 41 =≤ −Shi if (3.30)
For Zone-2,
0 and 1 then If 4,13,2 ==+≥ SShvv uvrefcf (3.31)
0 then andIf 41 =−>+< −Shvvhvv lvrefcfuvrefcf (3.32)
1 and 0 then If 4,13,2 ==−≤ SShvv lvrefcf (3.33)
Switching for Region 4 can be obtain in the same way as in Region 2, the only
difference being the capacitor discharges from negative to zero instead of positive to
zero.
52
3.3.2 State Feedback Control
From Fig. 3.3, the state space equation of the system is given by
cBuAxx +=& (3.34)
where
=
−−
=
=
0,
01
1
,f
dc
f
ff
f
cf
fL
VB
C
LL
R
Av
ix
The state feedback control law is then given by
−−
−=refcf
fHP
c vv
iKu
0 (3.35)
where K is the feedback gain matrix and i fHP is obtained by passing i f through a high
pass filter. Since it is rather difficult to obtain a reference for i f, it is safer to enforce
that the high frequency components of this signal should be zero. The gain matrix K
is obtained using a linear quadratic regulator (LQR) design, where the maximum
weightage is given to vcf. Once uc is obtained, the switching logic is generated using a
three-level HCC control as shown in Fig. 3.9. In this figure, two hysteresis bands are
chosen. Suppose uc starts at 0 and crosses the upper band h1 and reaches point A.
Then the switches S1 and S4 are turned on such that the output voltage is + Vdc. When
uc reaches − h1 at point B, the output voltage is made 0.
Figure 3. 9. Three-level modulation with state feedback control.
Subsequently, when uc reaches h1 at point C, the output voltage is made + Vdc.
Thereafter when uc reaches − h1 at point D, the output voltage is made 0. If uc
53
continues in the same direction and overshoots − h1 to reach point D, then the output
voltage is made − Vdc. Thereafter when uc reaches h1 at point F, the output voltage is
made 0. This logic is applied depending on the current and previous state of uc.
3.4. UPS Performance Evaluation
Once the reference for PCC voltage is computed from (3.4), the PCC voltage can be
tracked using the controllers described in Section 3.3. Application of hybrid
discontinuous controller is illustrated with the help of the following example where a
comparison is also made with the state feedback controller.
Example 3.2: Consider the system shown in Fig. 3.1. It is assumed that the source
voltage vs is balanced and has a magnitude of 11 kV (L-L, rms), which is equal to
about 9 kV (L-N peak). The load is an unbalanced nonlinear load, whose unbalanced
RL components are
Zla = 48.2 + j94.2 Ω, Zlb = 12.2 + j31.4 Ω and Zlc = 24.2 + j60.47 Ω
where the subscripts a, b and c denote the three phases. In addition, a three-phase
rectifier is also connected to the PCC with an output of 100 + j31.4 Ω. The feeder
impedance is R + jωL = 3.025 + j18.13 Ω. The UPS parameter are Vdc = 3.5 kV, Rf =
1.5 Ω and Cf = 50 µF. The single-phase transformers are rated 1 MVA, 3 kV/11 kV
with a leakage inductance of 2.5%. The UPS is connected to grid at time t = 0 where
it is required to maintain the PCC voltage at 11 kV (L-L rms). At t = 0.3 s, one more
balanced three phase load with 50 + j94.2 Ω (per phase) is connected. It is assumed
that the source power remains constant (Mode-1 control) such that balance power
comes from the UPS. The additional load is turned off at t = 0.5 s. The active power
flowing through the circuit is shown in Fig 3.10 (a). It can be seen that the source
real power remains constant during the load transients. The PCC voltage angle is
shown in Fig. 3.10 (b). Note from (2.4) that the PCC voltage angle is − δ. Hence in
the figure and in all the subsequent figures, the PCC voltage angle indicates − δ. This
also remains constant all through the load changes, as expected. From (2.3), it is
54
obvious that if the voltage and angle δ remain constant, the reactive power drawn
from the source should also remain constant. This is shown in Fig. 3.10 (c) where the
UPS reactive power changes in sympathy with that of the load, while maintaining the
source reactive power constant. The three-phase PCC voltage during the load
increase is shown in Fig. 3.10 (d). It can be seen that this voltage does not get
disturbed during the load transient. The controller parameters chosen are Kps =
−0.025, Kis = −10.0 and Kds = −10×10−6.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
Pow
er (M
W)
Real Power
Source PowerLoad Decreases
Load Power
Load Increases
UPS Power
(a)
0 0.1 0.2 0.3 0.4 0.5 0.6-50
-40
-30
-20
-10
0
Time (s)
Deg
ree
PCC Voltage Angle
(b)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7-2
-1
0
1
2
3
4
5
Time (s)
Pow
er (M
VAR)
Reactive Power
Load Increase Load Decrease
Load QLoad QLoad QLoad Q
Source QSource QSource QSource Q
UPS QUPS QUPS QUPS Q
(c)
55
0.25 0.26 0.27 0.28 0.29 0.3 0.31 0.32 0.33 0.34 0.35-10
-5
0
5
10
Time (s)Volta
ge (kV
)
Three Phase PCC Voltage
(d)
Figure 3. 10. UPS performance during load transient with Mode-1 control.
To compare the results obtained with the hybrid discontinuous control, the same test
is repeated with the state feedback control. The results obtained are very similar and
hence are not shown here. However the switching and conduction losses and the
THD of the PCC voltages are computed for both these methods. To compute the
switching losses, it is assumed that the VSC is made of Toshiba GTR Module Silicon
N Channel IGBT (MG400J1US51) IGBTs, the specifications for which are given in
Appendix A. The comparative results are listed in Table 3.1. It can be seen that the
switching edges in the discontinuous control is only 31% of those in the state
feedback control. The current through switches in the discontinuous mode is higher
than that in the state feedback control. Hence the switching losses in the
discontinuous control are 56% of the state feedback control and the conduction
losses are higher in the discontinuous control. It can therefore to be concluded that
the high current through switches in the discontinuous control somewhat nullifies the
benefit of less switching edges.
TABLE 3. 1. COMPARISON OF STATE FEEDBACK AND DISCONTINUOUS CONTROL
Switching
Edges in
one cycle
(0.02s)
THD
(PCC
Voltage)
Conduction
Losses in
Switches
(0.02 s)
Switching
losses (0.02s)
State Feedback 914 2.4% 7.41 J 166.14 J
Discontinuous
Control 286 0.68% 10.47 J 93.18 J
56
The state feedback controller is not used in the remaining part of the paper. Only the
results with the hybrid discontinuous controller are presented subsequently.
Example 3.3: To investigate the behavior of the UPS controller at the time of sag in
source voltage, we consider the same system as given in Example 3.2. There is
unsymmetrical voltage sag at t = 0.3 s where the source voltage of phase a, b and c
decreases to 7 kV, 6 kV and 8 kV (L-N, peak) respectively with an angle jump of -10
degree. Voltage at PCC is maintained at 9 kV (L-N, peak). The results are shown in
Fig. 3.11. Fig. 3.11 (a) shows the three phase source voltage with an asymmetrical
sag at t = 0.3 s. Fig 3.11 (b) shows the three-phase PCC voltage at the occurrence of
the sag. It can be seen that its magnitude remains constant. From (2.2), it is clear that
if source voltage reduces then angle should increase to maintain the same level of
power flow. Fig 3.11 (d) shows that the angle δ increases at t = 0.3 s. The active
power is shown in Fig. 3.11 (c). It can be seen that real power remain constant
barring transients, the results with a swell in the source voltage are very similar and
hence are not shown here.
0.29 0.3 0.31 0.32 0.33 0.34-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)
Vol
tage
(kV
)
Three Phase Source Voltage
Sag with angle jump
(a)
0.29 0.3 0.31 0.32 0.33 0.34-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)
Vol
tage
(kV
)
Three Phase PCC Voltage
(b)
57
0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.60
0.5
1
1.5
2
2.5
3
3.5
Time (s)Pow
er (M
W)
Real Power
Load PowerSource PowerUPS Power
(c)
0.25 0.3 0.35 0.4 0.45 0.5-50
-45
-40
-35
-30
-25
-20
Time (s)
Deg
ree
PCC Voltage Angle
(d)
Figure 3. 11. System performance at the time of asymmetrical sag in source voltage for Example 3.3
Example 3.4: Let us now consider Mode-2 control. This control mode can be
beneficial when running cost of the UPS is cheaper than the grid power. At this time
maximum constant power (based upon the UPS rating) is supplied by the UPS. In
other words, we can say that the UPS is operated at full load and rest of the power or
change in load power is supplied by the source. However the unbalanced and non-
linear portion of the load is still supplied by the UPS such that source current can be
maintained balanced sinusoidal. The controller parameters are chosen as Kpu = 0.025,
Kiu = 10.0 and Kdu = 10×10−6. To investigate the behavior of Mode-2 control during
sag and swell in the source voltage, it is assumed that a sag occurs at t = 0.3 s where
it reduces to 6.98KV (L-N, peak) and a voltage swell occurs at t = 0.5 s where it
increases to 10.98KV (L-N, peak). The results are shown in Fig. 3.12. It shows the
real powers through the different parts of the circuit. Since the load power remains
constant, the powers supplied by the UPS and the source also remain constant.
However the angle δ changes to accommodate this as evident from Fig. 3.12 (b).
58
0.2 0.3 0.4 0.5 0.6 0.7 0.8-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Time (s)
Pow
er (M
W)
Real Power
Load PowerSource powerUPS Power
(a)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9-20
-15
-10
-5
0
5
10
Time (s)
Deg
ree
PCC Voltage Angle
Sag
Swell
(b)
Figure 3. 12. Mode-2 control at the time of sag and swell in the source voltage for Example 3.4.
Additionally to test the power tracking behavior of the controller, the reference
power from the UPS is changed from 2 MW to 1 MW at t = 0.3 s. The additional
power must come from the source. This is evident from Fig. 3.13 (a). The angle δ is
shown in Fig. 3.13 (b). It can be seen that the angle quickly settles to a new value to
increase the power flow from the source.
Example 3.5: In this example, we explore the mode shifting behavior of the total
system. This can be useful for economic operation the system in which the maximum
power is drawn from the cheaper source. The mode shifting is achieved by
controlling δ with the help of two PID controllers as shown in Fig 3.14. Both the
controllers are run simultaneously irrespective of the control mode. For example,
suppose the control is running in Mode-1 with the power reference of Psref. Then δ is
computed from (2.5) with the switches Sw1 and Sw3 connected in the upper position.
In order to avoid any large transient in case of a mode switch, Mode-2 controller is
also run at this time. However, the reference for Mode-2 controller is computed from
the balance power, i.e., PL − Psref. Therefore the switch Sw2 is also in the upper
59
position. However since the switch Sw3 is in the upper position, the angle δ computed
from Mode-2 controller is given to the system for the computation of the voltage
reference (2.4). Once the mode shift to Mode-2 control is desired, all the three
switches are connected to the lower position. In this case the output angle of Mode-2
with the reference of Puref is used in (2.4) and Mode-1 controller runs off-line with a
reference of PL − Puref.
0 0.1 0.2 0.3 0.4 0.5 0.6-1
0
1
2
3
4
Time (s)
Pow
er (M
W)
Real Power
Load PowerSource PowerUPS Power
(a)
0 0.1 0.2 0.3 0.4 0.5 0.6-80
-60
-40
-20
0
20
Time (s)
Deg
ree
PCC Voltage Angle
(b)
Figure 3. 13. Mode-2 control during power reference change.
Figure 3. 14. Control switching at the time of mode shifting.
60
The results are shown in Fig. 3.15. It is assumed that the system is operating in
Mode-1 when a load increase occurs at t = 0.2 s. The load is reduced back to its
nominal value at t = 0.3 s. Subsequently the control is switched to Mode-2 at t = 0.4
s. Following this, the load again increases at t = 0.6 s and reduces at t = 0.8 s.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
Pow
er (M
W)
Real Power
Load PowerSource PowerUPS Power
Mode Change
(a)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8-100
-50
0
50
100
Time (s)
Deg
ree
PCC Voltage Angle
Mode Change
(b)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
Time (s)
Curr
ent (k
A)
Phase A Source Current
(c)
Figure 3. 15. System performance during mode switching and load change.
Fig 3.15 (a) shows the three active powers. It is evident that the control scheme
works in a desired manner. The angle δ is shown in Fig. 3.15 (b). It does not have
any significant transient barring a momentary jump at the switching point. The
source current of phase-a is shown in Fig. 3.15 (c). It can be seen that it remains
61
constant for Mode-1 control and changes according to the load requirement in Mode-
2 when the UPS supplies a constant power.
Example 3.6: In this example, the system performance during islanding is
investigated when the UPS is operating under Mode-2 control. With the system
operating in the steady state, the breaker connecting the supply side with the PCC
opens inadvertently at t = 0.2 s. When there is no power from source at that time total
load power is supplied by the UPS provided that total load power does not exceed the
UPS rating. The breaker recloses at t = 0.4 s.
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6-1
0
1
2
3
4
Time (s)
Pow
er (M
W)
Real Power
Source PowerUPS PowerLoad Power
Islanding
(a)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6-140
-120
-100
-80
-60
-40
-20
0
20
40
60
Time (s)
Deg
ree
PCC Voltage Angle
(b)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Curr
ent (k
A)
Load and Source Currents for Phase A
Source CurrentLoad Current
(c)
Figure 3. 16. System performance during islanding and reclosing.
62
Fig 3.16 (a) shows the source, load and UPS power variation during islanding and
reclosing. It can be seen that the UPS power becomes equal to the load power during
islanding, as expected. During islanding, however, the angle of the PCC voltage is
irrelevant since the total power is supplied by the UPS and zero power is drawn from
the source. Also since the source power is zero, the output of the PID controller
keeps on increasing. This is cause severe angle transient during reclosing. To avoid
this, the angle controller is turned off at the onset of island detection and the angle is
held constant at its pre-islanded value. The angle is shown in Fig. 3.16 (b). Phase-a
of the source and load currents are shown in Fig. 3.16 (c). It can be seen that load
current does not undergo any substantial transient during islanding or reclosing.
3.5. Conclusions
This paper presents a new control methodology to balance the source currents and
real power sharing between the grid and a UPS. Since the PCC voltages are
balanced, the current drawn from the source are balanced irrespective of the nature of
the load. The use of an LC filter with the UPS removes the effect of switching
frequency components at PCC voltage.
A new control strategy for the control of the PCC voltage is proposed in this paper.
In this, a diode state is used instead of the common 0-state. This results in
discontinuity in the VSC output current (i.e., the inductor current of the LC filter). In
comparison to 3-level state feedback control, the proposed method gives much less
switching and the switching loss is almost half compared to the state feedback
control. Furthermore, the new control scheme generates less THD in PCC voltage
than the 3-level state feedback control. In discontinuous control, the peak inductor
current of the LC filter is higher than the 3-level state feedback control. But
average/rms currents in both the controls are in the same order of magnitude. The
saturation current rating of an inductor is frequently designed to be higher than the
heating/average current rating, hence the same inductor can often work in both
discontinuous and 3-level state feedback (continuous) controls. In worse case we
might have to go for some higher rating inductors. In discontinuous control, it is not
necessary that the inductor current will always be discontinuous. Control logic tries
63
to make it discontinuous but, if next switching event occurs before inductor current
reaches to zero then inductor current doesn’t becomes discontinuous. If inductor
value is high then chances of discontinuity in current is less. Thus there will be
periods of discontinuous current and other periods of continuous. The extent of the
discontinuous mode determines the overall gain of switching losses for the new
control.
The PCC voltage angle (δ) is controlled using a simple PID controller. Mode shifting
between grid and UPS with the help of two PID controllers is discussed along with
switching of these two controllers.
Appendix - A
The characteristics of Toshiba MG400J1US51 module is listed in Table 3.2. These
ratings are used for loss computation of Example 3.2.
TABLE 3. 2. DATA SHEET OF TOSHIBA SILICON N CHANNEL IGBT, MG400J1US51
S.No Characteristic Rating
1 Collector Emitter Voltage 600V
2 Gate Emitter Voltage 20V
3 Forward Current 400A
4 Turn on Time (Max) 1.2µs
5 Rise Time (Max) 0.3µs
6 Turn on Delay (Max) 0.4µs
7 Turn off Time (Max) 1.0µs
8 Turn off Delay (Max) 0.4µs
9 Fall Time (Max) 0.3µs
References
[1] W. Bower and G. O'Sullivan, “Bimode uninterruptible power supply
compatibility in renewable hybrid energy systems,” IEEE Aerospace and
Electronic Systems Magazine, Vol. 5, No. 8, pp. 16-22, August 1990.
64
[2] K. Hkachi, M. Sakane, T. Matsui, A. Kojima and M. Nakaoka, “Cost-
effective practical developments of high-performance and multi-functional
ups with new system configurations and their specific control
implementations,” IEEE Power Electronics Specialist Conference (PESC),
Vol. 1, pp. 480-485, June 1995.
[3] F. Kamran, and T. G. Habetler, “ A novel on-line ups with universal filtering
capabilities,” IEEE Trans. on Power Electronics, Vol. 13, No. 3, pp. 410-418,
May 1998.
[4] C. Wang and M. H. Nehrir, "Distributed Generation Applications of Fuel
Cells," Power Systems Conference: Advanced Metering, Protection, Control,
Communication, and Distributed Resources, 2006. PS '06, 2006, pp. 244-248.
[5] Z. Jiang and R. A. Dougal, “ Control strategies for active power sharing in a
fuel-cell-powered battery-charging station,” IEEE Trans. on Industry
Applications, Vol. 40, No. 3, pp. 917-924, May/June 2004.
[6] M. K. Mishra, A. Ghosh and A. Joshi, “Operation of a DSTATCOM in
Voltage Control Mode,” IEEE Trans. on Power Delivery, vol. 18, pp. 258-
264, January 2003
[7] G. H. Bode and D. G. Holmes, "Implementation of Three Level Hysteresis
Current Control for a Single Phase Voltage Source Converter," in Power
Electronics Specialists Conference, pp. 33-38, 2000.
[8] F. Zare and G. Ledwich, "A Hysteresis Current Control for Single-Phase
Multilevel Voltage Source Converters: PLD implementation," IEEE
Transaction on Power Electronics, vol. 17, pp. 731-738, September 2002.
[9] A. Ghosh and G. Ledwich, "Load compensating DSTATCOM in weak AC
Systems," IEEE Transaction on Power Delivery, vol. 18, pp. 1302-1309,
October 2003.
[10] A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom Power
Devices: Kluwer Academic Publishers, 2002.
[11] Toshiba GTR Module Silicon N Channel IGBT, MG400J1US51, from the
website,
http://www.datasheetcatalog.com/datasheets_pdf/M/G/4/0/MG400J1US51.sht
ml.
65
CHAPTER 4
POWER NETWORK IN LOOP: A PARADIGM FOR REAL-TIME SIMULATION AND HARDWARE
TESTING
SACHIN GOYAL, GERARD LEDWICH AND ARINDAM GHOSH
School of Engineering Systems
Queensland University of Technology
Submitted: IEEE Transaction on Power Delivery.
66
Abstract −−−− The paper discusses a new paradigm of real-time simulation of power
systems in which equipment can be interfaced with a real-time digital simulator. In
this scheme, one part of a power system can be simulated using a real-time simulator,
while the other part is implemented as a physical system. The only interface of the
physical system with the computer based simulator is through data acquisition
system. The physical system is driven by a voltage source converter (VSC) that is
mimicking the power system simulated in the real-time simulator. In the paper, the
VSC is operated in a voltage control mode to track the PCC voltage signal supplied
by the digital simulator. This type of splitting a network in two parts and running a
real-time simulation with a physical system in parallel is termed as a power network
in loop here. This opens up the possibility of the study of interconnection of one or
several distributed generators to a complex power network. The proposed
implementation is verified through simulation studies using PSCAD/EMTDC and
through hardware implementation on a TMS320F2812 DSP.
Index Terms − Real-time simulator, power network in loop simulation, VSC,
control bandwidth.
4.1 Introduction Digital computer simulations have been used extensively in power systems studies
for both design and testing. However, this form of evaluation tool is often not
suitable for testing of protective devices like relays or testing real life controllers. To
alleviate this problem, real-time digital simulators have been developed, which use
high speed parallel processors to simulate a complex power network within
microseconds [1-3]. These simulators can be interfaced with a physical controller on-
line and this form of operation is often termed as “hardware-in-the-loop” testing.
While testing protection devices, the real-life system components interact with a
digital simulation of a power network running in real time. The hardware is sent
signals to represent the currents or voltages in a network with small amplifiers to
make the signals compatible with the output expected from VT’s and CT’s. The trip
signal from the protecting device is then passed to the simulator which can then
67
open/close circuit breakers in the simulated network. The advantage of the approach
is that limitations of the hardware implementation can be evaluated within a realistic
environment.
The aim of this paper is to broaden the “hardware in the loop” concept to include
testing of network components. For many consumer devices, the mains supply can be
treated as an ideal voltage source, and hence, the component testing only requires
finding a near-ideal source for evaluating performance. This paper aims to develop
the theory for on-line interaction between power network components and simulation
using an inverter interface. For the simulation of large systems, Kron’s method of
tearing the network into two or more segments offers possibilities [4,5]. The
difficulty is that the theory is developed with similar network solution processes in
both sections without the interface issues.
The interface of real-time controller with a simulated circuit is reported in [6].
Controller output is sent to real time virtual test bed (RTVTB) through an A/D card
and simulation output is sent to micro-controller. Here the communication is at low
voltage. No amplification is required. Communication is carried out through a serial
port.
The network tearing aspect has been studied in a two part paper [7,8]. In Part 1 [7],
different methods of tearing are presented and compared against their performance.
This paper discusses power hardware in loop (PHIL) concept through a two way
interactions. But however does not discuss the hardware feasibility. The frequency
response of different simulation/hardware interface schemes has been presented in
[8]. It however does not present the stability analysis aspects of tearing.
We begin our discussion with an introduction to the hardware-software simulation
concept. This will be followed a discussion of closed-loop VSC control employed in
the paper for voltage control. The associated filtering issues will also be discussed.
The proposed structure will be verified through extensive PSCAD simulation and
also through an experimental setup prepared around a TMS320F2812 DSP processor.
68
4.2. The Hardware-Software Concept
The conceptual diagram of the hardware-software simulation system is shown in Fig.
4.1. In this diagram, the power network, simulated in a real-time simulator, is termed
as the supply side, while the equipment to be tested is termed as the test side. In
general the test side is assumed to contain a separate generator, which often can be a
disturbed generator (DG). The supply side is represented by its Thevenin equivalent
v1, Z1. The test side may contain a DG, feeder and any local load, which have a
Thevenin equivalent of v2, Z2. In this figure, the voltage vf of the test side is
generated by a voltage source converter (VSC).
Figure 4. 1 Conceptual hardware-software simulation diagram: Voltage control.
In Fig. 4.1, the voltage vp measurement is tracked by the VSC to produce vf of the
test side. The current-controlled current source i f is controlled by the output of the
low-pass filter (LPF). The function of the LPF is to suppress the high frequency
switching components generated by the VSC of the test side current. Moreover, it
also has an impact on the stability of the system, as we shall discuss later. The
voltage and current are transferred from one part (supply side) of the network to the
other part (test side) of the network in the form of low voltage signals with the help
of voltage and current sensors. A current sensor measures the current i2, which is
then sampled and converted by an A/D converter. This signal can then be scaled to
be of the same magnitude as that in the simulated circuit. The LPF is realized in the
form of an averaging process in software itself. The voltage feedback from supply
side to test side is amplified by the VSC, which acts as a power amplifier. The design
of this amplifier is described in Section 4.3. It is to be noted that the connection
between the supply side and the test side is only through signal level through digital-
69
to-analog converter (DAC) and analog-to-digital converter (ADC). Power level
signals are not exchanged.
Depending on the network complexity and parallel processing hardware availability,
a real-time simulator can solve the supply side dynamic equations in as little as 2
microseconds. A VSC, however, cannot be operated at this speed. Therefore a much
lower switching frequency of the VSC can be chosen, provided that it is sufficient to
track the desired voltage.
In Fig. 4.1, the VSC mimics the supply side for the test side and it is supposed to
generate same voltage waveform as vp. But when VSC tracks supply side voltage for
test side, it generates high frequency switching components along with desired
voltage. These high frequency components reflect in current (i2) flowing at test side.
Since these high frequency switching components are not part of network therefore
elimination of these components are necessary. If this current (i2), containing high
frequency components, is fed to supply side directly, total deterioration of the system
performance will occur. Hence low pass filter is used to eliminate undesired high
frequency components. The effect of the LPF on the system stability is discussed in
Appendix A.
4.3. Amplifier Structure
Fig. 4.2 shows the structure of VSC based power amplifier. It contains one H-Bridge
voltage source converter and an LC filter with inductance of Lf1 and capacitance of Cf
at the output of converter. This filter prevents the high frequency switching
components from entering the test side. VSC is connected to DC storage Vdc. Output
voltage vcf is controlled using a voltage control scheme. Voltage signals of vp from
supply side is considered as a reference for the voltage control scheme.
To discuss the VSC control strategy used in the paper, let us consider a simple power
system, as shown in Fig. 4.3. The network tearing line is also shown in this figure. In
this, the supply side contains the voltage source v1, while source impedance is being
represented by R1 + jωL1. The test side voltage source v2 has a source impedance
70
jωLs. It also contains a passive R-L load (Rl, Ll) and a feeder with an impedance of R2
+ jωL2. The test side equivalent circuit is shown in Fig. 4.4.
Figure 4. 2 Power amplifier Structure
Figure 4. 3. Simple network under study.
Figure 4. 4. Voltage controlled VSC amplifier connection with the test side.
Ideally, vp1 should be equal to vp2 and i1 should be equal to i2. However with the
network being torn, this will not be so. The main idea of the VSC control is force
them to be nearly equal. The success of the scheme will depend on the closed-loop
71
control of the VSC, which enables it to track the reference voltage accurately.
Closed-loop voltage tracking in the presence of a filter, however, is a nontrivial task.
In this paper, a strategy of close loop voltage control is discussed.
4.4. Hybrid Discontinuous Voltage Control
In this control scheme, the converter switching decision is made based on inductor
current (i f1) and capacitor voltage (vcf) of LC filter to control the output voltage of
amplifier. All the three states (+ 1, − 1 and 0) of inverter are used here. In + 1 and − 1
states, the output voltages of converter are + Vdc and − Vdc respectively and the 0-
state is the diode state where all four switches are turned off. In the diode state, with
the help of the free-wheeling diode, the inductor current is forced to zero. This state
introduces discontinuity in the converter output current (i f1).
Based on zones, control action between inductor current control and capacitor
voltage control is switched as shown in Fig. 4.5. If error between reference voltage
and capacitor voltage is high then control action is assumed in Zone-1 where
converter decision is made based on filter inductor current and it is controlled inside
a band. Once error reduces due to the control action of Zone-1, control action is
switched to Zone-2, where converter switching decision is made based on filter
capacitor voltage.
Figure 4. 5. The two zones voltage control scheme.
To track a sinusoidal capacitor voltage reference, one cycle is divided in four regions
as shown in Fig. 4.6, where each region is divided into two zones explained above.
72
For each zone, the hysteresis band is defined separately. In Zone-1, the hysteresis
band is defined for the inductor current and in Zone-2, the band is defined for the
capacitor voltage. In Regions 1 and 3, the capacitor is charged for positive and
negative voltage respectively. Thus the switching control logic is very much similar
in Regions 1 and 3. Only reference changes from positive to negative.
0 0.005 0.01 0.015 0.02-1.5
-1
0
1
1.5
Time
Mag
. Region 1 Region 2
Region 3 Region 4
Figure 4. 6. Four regions of one cycle of a sinusoidal wave
If the reference of the capacitor voltage is in Region 1, then switching in Zone-1 will
be defined as
0 then If 411 =≥ −Shi if (4.1)
where hi is the upper current hysteresis band. This implies that if the current i f1 is
greater than or equal to hi, turn all the switches off. However, if this current is less
than zero, which is lower current band limit, apply positive voltage at the VSC
output, i.e.,
0 and 1 then 0If 4,32,11 =+=< SSi f (4.2)
Let the upper and lower voltage hysteresis bands (for Zone-2) be denoted by huv and
hlv respectively. Then for Zone-2, we have the following switching logic
0 and 1 then If 4,32,1 ==−≤ SShvv lvrefcf (4.3)
0 then and If 41 =+<−> −Shvvhvv uvrefcflvrefcf (4.4)
1 and 0 then If 4,32,1 ==+≥ SShvv uvrefcf (4.5)
73
The switching for Region 3 will be the same as above except that − Vdc state will be
chosen instead of + Vdc state.
The switching for Region 2 two is defined as follows. The switching in Zone-1 is
0 and 1 then 0If 2,14,3 ==≥ SSi f (4.6)
0 then If 41 =≤ −Shi if (4.7)
Similarly for Zone-2, we have
0 and 1 then If 2,14,3 ==+≥ SShvv uvrefcf (4.8)
0 then andIf 41 =−>+< −Shvvhvv lvrefcfuvrefcf (4.9)
1 and 0 then If 2,14,3 ==−≤ SShvv lvrefcf (4.10)
Switching for Region 4 can be obtain in the same way as in Region 2, the only
difference being the capacitor discharges from negative to zero instead of positive to
zero.
Example 4.1: To demonstrate the voltage tracking ability of the VSC, let us consider
the system of Fig. 4.3. Here it is assumed that network is torn in two parts (supply
and test) from network tearing line as shown in Fig. 4.3. The torn network is
interfaced with the help of VSC amplifier as shown in Fig. 4.4. Efficiency of
amplifier can be judged with the help of error between voltage (vp1) at tearing point
in actual network (Fig. 4.3) and voltage vp2 at test side in the torn network. Ideally
these two voltages should be identical. The system parameters chosen for the study
are:
System Frequency = 50 Hz,
v1 = 9 sin (ωt ) kV, v2 = 9 sin (ωt − 30°) kV,
L1 = 60 mH, Ls = 5 mH, R1 = 0.94 Ω,.
Feeder & Load: R2 = 1.25 Ω, L2 = 80 mH, Rl = 50 Ω,
Ll = 100 mH.
VSC & Filter: Vdc = 15 kV, Lf1 = 10 µH, Cf = 2500 µF.
74
( )20000
20000LPF
+=
ss
The system is simulated using PSCAD with a simulation step size of 10 µs. Voltage
tracking results of hybrid discontinues voltage control is shown in Fig. 4.7 (a) which
shows reference voltage vp1 of the total (real) network (Fig. 4.3) and output voltage
of amplifier (vp2). Since the difference between the two voltages is not visible from
this figure, the error between them is plotted in Fig. 4.7 (b). The average error is less
than 0.55%.
(a)
(b)
Figure 4. 7 (a) Voltages vp1 and vp2 and (b) voltage tracking error.
Fig. 4.8(a) shows the reference current i2 of the total (real) network (Fig. 4.3) and the
current flowing in torn network (i2′). The error between these two currents is plotted
in Fig. 4.8 (b). The steady state average and maximum errors in current are about
0.58% and 1.56%.
75
(a)
(b)
Figure 4. 8. (a) Currents i1 and i2 and (b) the error between these two currents.
4.5. Experimental Results
A hardware setup is built to test and verify the practical feasibility of the power
network-in-loop concept. One H-Bridge single phase inverter is used for amplifier.
Texas instrument DSP board TMS320F2812 is used to control the VSC and is also
used to simulate the test side network. LEM current sensor is used to measure the
filter inductor current. For the capacitor voltage of the LC filter of the amplifier,
voltage is scaled down and measured with the help of an operational amplifier. The
PCC voltage (vp) was used as reference voltage for amplifier. Test side current is
sensed using LEM current sensor and A/D converter which is inbuilt in this DSP.
Example 4.2: Here, a simple circuit, as shown in Fig. 4.9, is tested. The tearing line
is as shown in this figure. Since supply side circuit is simulated and the amplifier
control is computed in the same DSP chip, the reference voltage (vp) for amplifier is
directly passed and no DAC is required here. The supply side is simulated using
discrete time state equation with a time step of 40 µs. The schematic diagram of the
hardware setup for this example is shown in Fig. 4.10.
76
Figure 4. 9. The test circuit of Example 4.2.
Figure 4. 10. Schematic diagram of the hardware setup for Example 4.2.
The state equations for supply side circuit are represented as follow:
( )
=−−
=
s
i
s
s
is
L
RL
BL
RRA
0
01
, (4.11)
The discrete-time equivalent of the circuit for a sampling time (Ts = 40 µs) is given
by
( ) ( ) ( )kGukFxkx c+=+1 (4.12)
where ( ) [ ]lsTcs ivuikx == and .
The system parameters are: Rl = 10 Ω, RL = 200Ω, Ll = 20mH and LL = 54mH. The
supply voltage is chosen with a peak of 20 V and a frequency of 50 Hz. The load
current (i l) is taken to the supply side using current sensor and A/D card. It is then
filtered using an averaging process.
77
The entire (complete) network without tearing is simulated in PSCAD. This is then
compared with the experimental results obtained with torn network, as per the
experimental set up discussed. Fig 4.11 shows the PCC voltage (vp), while Fig. 4.12
depicts the test side current (i l). It is clear that the experimental results with network
tearing are similar to simulation results with the complete network. These results
prove that the testing of power system network is practically feasible using power
network-in-loop concept.
0.2 0.205 0.21 0.215 0.22 0.225 0.23 0.235 0.24 0.245 0.25-30
-20
-10
0
10
20
30
Time (s)
Vol
tage
(V
)
PCC Voltage
Experimental ResultSimulation Result
Figure 4. 11. Experimental and simulation result for PCC voltage (vp)
1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29
-0.1
-0.05
0
0.05
0.1
0.15
Time(s)
Cur
rent
(A
)
Test Side Current
Experimental resultSimulation Result
Figure 4. 12. Experimental and simulation result for i l
In the next step of this test, a 30 µF capacitor is connected in series with RL and LL
and value of RL was reduced to 10 Ω. The capacitor is switched to examine the
transient behaviour of torn network. With the circuit being in steady state, the
capacitor is bypassed (short circuited) in the simulation studies. Fig. 4.13 shows the
current i l. Note that the reactance of the capacitor is much larger than that of the
inductor. Hence the load impedance reduces as the capacitor is bypassed. This results
in an increase in the current as is evident from Fig. 4.13. The experimental waveform
is shown in Fig. 4.14. The transient behaviours are not identical since the dynamics
of the switch and the instant of bypass switch closing could not be matched.
78
0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Time(s)
Cur
rent
(A)
Load Switch (Simulation Result)
Load Change
Figure 4. 13. Simulation result for i l
Figure 4. 14. Experimental result for i l during capacitor switching.
Example 4.3: In this example, the feasibility of power network tearing is extended
by testing the interaction of two generators. Fig. 4.15 shows the network under test in
which the network tearing line is also indicated. The supply side network is
simulated in the DSP using state equations of (4.11) and (4.12) since the supply side
remains unchanged from Example 4.2.
Figure 4. 15. Circuit under test for two generators interaction.
The grid voltage is scaled down using an auto-transformer and used as the voltage
source v2. Synchronization between v2 and v1 must be established to avoid a
79
frequency mismatch. Generally, a phase lock loop (PLL) is used to establish
synchronization between two sources. To avoid complexity, the grid voltage is scaled
down and passed to the DSP through an ADC. We can then set the frequency of the
voltage source v1 to that of the mains. The voltage magnitude and phase difference
(Φ) can be created using software program in the DSP by storing one cycle data at a
40 µs sampling rate. The study system parameters are shown in Table-4.1.
TABLE 4. 1: SYSTEM PARAMETERS FOR EXAMPLE-4.3. System
Quantities
Value
v1 )sin(5.32 tω×
v2 )sin(10 φω +× t
Rl 10Ω
Ll 20mH
Ri 5Ω
RL 200Ω
LL 54mH
R2 5Ω
L2 9mH
1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Time(s)
Cur
rent
(A)
Experimental ResultsSimulation Results
Figure 4. 16. Current at network tearing point (i l).
For this test, again the PSCAD simulation of the complete network is compared with
the experimental results. First the network is tested with zero phase difference
between v1 and v2. Fig. 4.16 shows the current at network tearing point (i l). Fig. 4.17
shows the comparison between the line currents (i l1). It is clear from these figures
80
that the currents in the torn network are similar to those in the simulated entire
network. Fig. 4.18 shows the phase difference between i l1 and v2, obtained
experimentally. The PCC voltage is shown in Fig. 4.19.
1.78 1.79 1.8 1.81 1.82 1.83 1.84 1.85
-1.5
-1
-0.5
0
0.5
1
1.5
Time(s)
Cur
rent
(A
)
Line Current
Experimental ResultSimulation Result
Figure 4. 17. Line current passing through R2 (i l1).
5.24 5.26 5.28 5.3 5.32 5.34 5.36 5.38 5.4 5.42-25
-20
-15
-10
-5
0
5
10
15
20
25
Time(s)
Current
Voltage
Figure 4. 18. Phase difference between i l1 and v2.
Figure 4. 19. Tearing point (PCC) voltage vp. In the next stage of this test, a phase difference of 20° was created between v1 and v2
in which the phase of v1 is advanced by 20° vis-à-vis that of v2 in the software
program. Fig. 4.20 shows the voltage v1 and v2. Fig. 4.21 shows the current at
network tearing point (i l). Since the case magnitude of i l is very small, the noise to
signal ratio of the current sensor is high. Therefore the current i l is significantly
81
distorted. However, the performance of the system does not get affect due to the
small magnitude of the current. This is evident from the PCC voltage shown in Fig.
4.22.
1 1.002 1.004 1.006 1.008 1.01 1.012 1.014 1.016 1.018 1.02-40
-30
-20
-10
0
10
20
30
40
Time(s)
Vol
tage
(V)
v1
v2
Figure 4. 20. v1 and v2 with 20° phase difference.
1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3
-0.5
0
0.5
Time(s)
Cur
rent
(A)
Experimental ResultsSimulation Results
Figure 4. 21. Current at network tearing point (i l).
Figure 4. 22. Tearing point (PCC) voltage vp.
Example 4.4: To study the two way interaction of power network in loop, the
network shown in Fig. 4.23 is considered, where the voltage source v2 is the utility
bus. The voltage source v1 is simulated in the DSP and its angle (δ) is varied
according to the swing equation.
82
Figure 4. 23. Circuit under test for Example 4.4.
The swing equation is solved in discrete time domain at sampling rate of 40µs. It can
be represented as follow:
( )em PPHf
H
D
dt
d −
+
−=
02
1
02
02 δ
ω
πδω
(4.13)
The discrete-time equivalent of the swing equation at the sampling frequency of 1/Ts
is given by
( ) ( ) ( )kGukFxkx c+=+1 (4.14)
The parameters chosen for the study are
R=15 Ω, L=20mH, f=50Hz, D=6 and H=0.5
)sin(121 δω +×= tv and )sin(102 tv ω×=
To calculated the instantaneous electrical power (Pe), is is sensed using A/D card and
multiplied with v1. The angle δ is calculated using (4.14) by the DSP. To overcome
the problem of frequency mismatch between v1 and v2, mains grid voltage is sensed
using A/D card and scaled to form the magnitude of v1, while a phase lead is
provided according the calculated value of δ as per (4.14).
Initially Pm is set to 2 watts. Fig. 4.24 (a) and (b) show the simulation and
experimental results, respectively, of the initial transient in is. It is clear from these
that the initial transients are similar.
83
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-1
-0.6
-0.2
0
0.2
0.6
1
Time(t)
Cur
rent
(A)
Siumulation result
(a)
0.2 0.4 0.6 0.8 1 1.2 1.4
-1
-0.6
-0.2
0
0.2
0.6
1
Time(t)
Cur
rent
(A)
Experimental Results
(b)
Figure 4. 24. Initial transients in is: (a) simulated waveform and (b) experimental waveform.
The value of Pm is now suddenly changed from 2 to 5 watts. It is well-known that as
Pm increases; both the values of δ and is will increase. Fig. 4.25 (a) shows the
simulation result of change in Pm, while Fig. 4.25 (b) shows the waveform obtained
experimentally. It can be seen that the magnitudes and trends are similar for both
these waveforms.
2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Time(t)
Cur
rent
(A)
Simulation Result
(a)
84
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Time(t)
Cur
rent
(A)
Experimental Result
(b)
Figure 4. 25. Transients in is during power change: (a) simulated waveform and (b) experimental waveform.
Hence this experiment proves that the transient study of power system network can
be performed using the proposed power network in loop concept. For study of big
power network, high speed real time digital simulators are required so that the supply
side network can be simulated in lesser time.
4.6. Power Network In Loop Of A Complex System
So far we have demonstrated the proposed concept of power network in loop for
simple systems and have verified it through simulations and experiments. In this
section, we shall show that this concept of tearing is valid even in the case of more
complex networks. The dynamic interaction will be verified through simulation
studies only. The system is considered to be single phase.
Example 4.5: Let us consider the system as shown in Fig. 4.26. In this figure,
different feeder sections are denoted by the subscript ‘f’, while the loads are denoted
the subscript ‘l’. The system parameters for the network are listed in Table 4.2. It is
assumed that the circuit on the left of the network tearing line (the supply side) is
simulated in a digital simulator, while the circuit on the right (test side) consists of
physical systems with the interface driven by an amplifier. Both these systems are
simulated in PSCAD. The amplifier is controlled with discontinuous hybrid voltage
control. The network tearing line is also indicated in this figure. This network has 2
buses and 5 feeders. Voltage sources v1 and v2 are connected to Bus-1 and Bus-2
85
through feeders one and five respectively. There is a rectifier load connected to Bus-
1 through feeder 3 that injects the harmonics to the system.
The PCC voltage of the complete network without tearing and the torn network with
the VSC amplifier are shown in Fig. 4.27 (a), while the error between these two
voltages is shown in Fig. 4.27 (b). The average voltage error is 2%. The currents
flowing in the test side for the two networks (without tearing and torn) are shown in
Fig. 4.27 (c), while the error between these two quantities is shown Fig. 4.27 (d). The
average current error is 3%.
Figure 4. 26. The complex study system.
TABLE 4. 2: PARAMETERS OF THE SYSTEM OF FIG. 4.24. System quantities Values
System frequency 50 Hz
Voltage Source v1, v2 9 sin (ω t)
Feeder (Rf1, Lf1) 0.4032 Ω, 12.8
mH
Feeders (Rf2, Lf2), (Rf3, Lf3),
(Rf4, Lf4),
0.2016 Ω, 6.4 mH
Source inductance (Ls) 5 mH
Load (Rl1, Ll1), (Rl3, Ll3), 50 Ω, 100 mH
86
(Rl4, Ll4)
Feeders Rf5, Lf5 1.25 Ω, 6.4 mH
Load (Rl2, Ll2) 10 Ω, 100 mH
Filter capacitance Cl2 50 µF
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-10
-5
0
5
10
Time (s)
Vol
tage
(kV
)
PCC Voltage in Real & Torn Network
TornReal
(a)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Time (s)
Vol
tage
Err
or (kV
)
(b)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Time (s)
Cur
rent
(kA
)
Current in Real & Torn Network
TornReal
(c)
87
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-0.015
-0.01
-0.005
0
0.005
0.01
0.015
Time (s)
Cur
rent
Err
or (k
A)
(d)
Figure 4. 27. Voltage, current and their errors in Example 4.5.
Example 4.6: In this example, we investigate the behavior due to voltage sag and
swell in the source voltage of the supply side of the system of Fig. 4.26 and Table
4.2. A sag in the source voltage is created at 0.5 s, where the source voltage is
decreased to 7 kV (L-N Peak). This is followed by a swell in this voltage at 0.6 s,
where the voltage becomes 11 kV (L-N Peak). The voltage returns to its nominal
value (9 kV) at 0.7 s.
Fig. 4.28 (a) shows the PCC voltage of the complete and the torn networks, while the
voltage error is shown in Fig. 4.28 (b). The average voltage error is less than 2%.
However at the points of the occurrence of voltage transients, the error shoots up to
about 3.5%. Fig. 4.28(c, d) shows the current in the actual and torn networks and
error between these two currents. It is clear from Fig. 4.28(d) that the current error is
less than 5%.
0.45 0.5 0.55 0.6 0.65 0.7 0.75-15
-10
-5
0
5
10
15
Time (s)
Vol
tage
(kV
)
PCC Voltage in Real and Torn Network
TornReal
Sag Swell
(a)
88
0.45 0.5 0.55 0.6 0.65 0.7 0.75
-0.4
-0.2
0
0.2
0.4
0.6
Time (s)
Volta
ge E
rror
(kV)
(b)
0.45 0.5 0.55 0.6 0.65 0.7 0.75-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Time (s)
Cur
rent
(kV
)
Current in real and Torn Network
TornRealSag Swell
(c)
0.45 0.5 0.55 0.6 0.65 0.7 0.75-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
Time (s)
Cur
rent
Err
or (kA
)
(d)
Figure 4. 28. Voltage, current and their errors in Example 4.6.
Example 4.7: In this example effect of line to ground faults at buses 1 and 2 is
examined. At t = 0.5 s, the fault is created at Bus 1 and it is removed at t = 0.6 s.
Again at t = 0.7 s, a fault is created at Bus 2, which is removed at t = 0.8s. Due to
either of these faults, the PCC voltage decreases and test side current increases. Fig.
4.29 (a) shows the PCC voltage in the actual and torn networks. It is clear from
figure that the amplifier is able to track the voltage closely even when it reduces due
to the faults. Fig. 4.29 (b) shows error in the PCC voltages. It is clear from this figure
that except for the spikes at the instants of voltage change, the error is less than 3.5%.
Fig. 4.29 (c) shows the current in the actual and torn networks, while their error is
plotted in Fig. 4.29 (d). The average current tracking error is less than 2.5%.
89
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85
-10
-5
0
5
10
Time (s)
Vol
tage
(kV
)
PCC Voltage in Real and Torn Network
TornReal
Fault at Bus A
Fault at Bus B
(a)
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85-3
-2
-1
0
1
2
3
4
5
6
Time (s)
Vol
tage
Err
or (k
V)
(b)
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85-3
-2
-1
0
1
2
3
Time (s)
Cur
rent
(kA
)
Crrent in Real and Torn Network
TornReal
Fault at Bus A
Fault at Bus B
(c)
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85
-0.1
-0.05
0
0.05
0.1
Time (s)
Cur
rent
Err
or (k
A)
(d)
Figure 4. 29. Voltage tracking of a complex system at the time of faults
90
4.7. Conclusions
In this paper a new concept has been proposed. This Power Network in Loop
provides a new method for testing of power system components. This paper shows
how this can be applied to general power networks through simulation and
experimental studies. The research shows that a subsystem of a power network can
be interfaced with a real-time simulation using the switching amplifier. The amplifier
is capable of amplifying the voltage signal received from the real-time simulation.
This can represent the effect of the simulated network, which can be complex. This
amplified voltage can then be interfaced with a small physical subsystem. Using this
concept, the effect of different faults and other conditions in the simulated network
can be evaluated on the subsystem under test.
References
[1] R. Kuffel et al, “RTDS – a fully digital power system simulator operating in real-
time,” Digital Power System Simulators, ICDS’95, 1995.
[2] G. Sybille and P. Giroux, “Simulation of FACTS controllers using the MATLAB
power system blockset and Hypersim real-time simulator,” IEE PES Panel
Session on Digital Simulations of FACTS and Custom Power Controllers, Winter
Meeting, New York, 2002.
[3] C. A. Rabbath, M. Abdoune and J. Belanger, “Effective real-time simulations of
event-based systems,” Proceedings of the 2000 Winter Simulation Conference,
2000.
[4] B. Han, B. Bae and Y. Jeong, “Load simulator with power recovery capability
based on voltage source converter-inverter set,” Proc. IEE Electric Power
Application, Vol. 153, No. 6, pp. 891-897, 2006.
[5] G. Kron, Tensor Analysis of Networks, John Wiley, N.Y., 1939.
[6] Z. Jiang, R, Leonard, R. Dougal, H, Figueroa and A. Monti, “Processor-in-the-
loop simulation, real-time hardware-in-the-loop testing, and hardware validation
of a digitally-controlled, fuel-cell powered battery-charging station,” IEEE
Power Electronics Specialists Conference, pp. 2251-2257, Aachen, 2004.
91
[7] X. Wu and A. Monti, "Methods for partitioning the system and performance
evaluation in power-hardware-in-the-loop simulations. Part I," in Industrial
Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE, 2005,
pp.251-256
[8] X. Wu and A. Monti, "Methods for partitioning the system and performance
evaluation in power-hardware-in-the-loop simulations - Part II," in Industrial
Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE, 2005,
pp.257-262
Appendix - B
This appendix discusses the numerical stability issue and provides a guideline for the
remedial action. Consider the network shown in Fig. 4.30, for which the following
parameters are chosen: R1 = 1 Ω, L1 = 1 mH, R2 = 0.1 Ω, L2 = 0.1mH, C = 10 µF Ri =
2 Ω and v1 = √2×10 sin (ω t) V. The network tearing line is also shown in the figure.
Let us assume that the current i1 is directly supplied from test side to the supply side
without passing it through the LPF. For the parameters chosen, the complete network
without tearing is stable. However, the power network in the loop simulation
becomes unstable as shown in Fig. 4.31. It can be seen from Fig. 4.7 (b) that the
voltage error contains the high frequency components, which is then passed to the
current i1. A direct feedback of this current to the supply side will result in the
distortion of the PCC voltage as shown in Fig. 4.32. The distorted PCC voltage
further distorts the current, which then distorts the PCC voltage further. Thus the
distortions shown in Figs. 4.31 and 32 are due to these cumulative effects.
Figure 4. 30. The network considered for stability studies.
92
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Time (s)
Cur
rent
(A)
Test Side Current (il)
Figure 4. 31. The test side current containing high frequency ripple components.
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04-15
-10
-5
0
5
10
15
Time (s)
Volta
ge (V
)
PCC Voltage
Figure 4. 32. The distorted PCC voltage.
To alleviate the problem, the current i1 is first passed through a low pass filter (LPF)
before passing it to the supply side as shown in Fig. 4.33. The LPF prevents the
injection of the high frequency components of i1 to the supply side and hence PCC
voltage does not get distorted. This results in the stable tracking as shown in Fig.
4.34. A more formal proof of the effect of the LPF is beyond the scope of this paper.
Figure 4. 33. System structure with LPF.
93
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)Volta
ge (V
)
PCC Voltage
Figure 4. 34. Stable PCC voltage with LPF.
94
CHAPTER 5
TESTING OF A DISTRIBUTED GENERATION SYSTEM WITH A VIRTUAL GRID
SACHIN GOYAL, ARINDAM GHOSH AND GERARD LEDWICH
School of Engineering Systems
Queensland University of Technology
Submitted: Electric Power Systems Research.
95
Abstract – The paper provides the solution for testing of a distributed generation
system (DGs) with a computer simulated grid. The computer simulated grid is
referred as virtual grid in this paper. Integration of DG with the virtual grid provides
broad area of testing of power supplying capability and dynamic performance of a
DG. It is shown that a DG is supplying a part of load power while keeping PCC
voltage magnitude constant. To represent the actual load, a universal load along with
power regenerative capability is designed with the help of voltage source converter
(VSC) that mimics the load characteristic for DG. The overall performance of the
proposed scheme is verified using computer simulation studies.
Keywords −−−− UPS, Virtual grid, Universal Load, LC output filter.
5.1. Introduction
Because of size and the complexity of interaction within a power network, most
power system research is based on pure simulation. To validate the performance of
physical generator or protection system, most testing is constrained to very simple
power networks. This paper examines a method to test power system hardware
within a complex virtual environment. Integration of simulation with a physical
system gives an opportunity to test a small distributed generation system with in a
large power network. According to this concept, the total power network is torn in
two parts. One part represents the physical system that needs to be tested and the
other part represents the rest of the complex network. The complex power network is
simulated in a real time simulator [1-3] and with the help of analog-to-digital (A/D)
and digital to analog (D/A) converter cards signals (voltage and current) are
transferred from simulated network to physical system and vice versa. Since there is
a voltage level difference between the simulation signals and the physical system, an
amplifier is required to bring simulation signal to the level of physical system. A
high bandwidth switching amplifier (VSC based) is used to connect the physical
system in a loop with the simulation.
While testing protection devices [4], the real-life system components interact with a
digital simulation of a power network running in real time. The hardware is sent
96
signals to represent the currents or voltages in a network with small amplifiers to
make the signals compatible with the output expected from VT’s and CT’s. The trip
signal from the protecting device is then passed to the simulator which can then
open/close circuit breakers in the simulated network. The advantage of the approach
is that limitations of the hardware implementation can be evaluated within a realistic
environment
In this paper, the concept of “Hardware in loop” is explored to test a DG system with
a power network. The DG is connected to the main grid with a VSC and a LC filter.
The LC filter is used to bypass the switching frequency components of VSC output
voltage. The control and structure of the total DG system is designed in such a way
so that it overcome the power quality problem, while supplying clean power from
DGs at the same time. In case of emergency, when there is no power from the grid, it
can supply the total load and that is why in this paper this total DG system is termed
as uninterruptible power supply (UPS). This UPS can compensate the load at the
time of sag or swell in source voltage. Also it can compensate the load at the time of
feeder change [5]. For the simulation of large systems, Kron’s method of tearing the
network into two or more segments offers possibilities [6]. The difficulty is that the
theory is developed with similar network solution processes in both sections without
the interface issues. The load simulator with power recovery unit has been studied in
[7-9]. Here the concept of back to back inverter is used for power recovery at AC
side with PLL which requires extra hardware and control.
We start our discussion with an introduction to the hardware – software integration
concept. This will be followed by the UPS and its testing scheme with power
recovery scheme. We will also discuss the control of amplifier with power recovery
capability. The proposed scheme and control will be verified through extensive
PSCAD simulation.
5.2. The Concept
The conceptual diagram of the hardware-software interface system is shown in Fig.
5.1. In this diagram, the complex power network, simulated in a real-time simulator
97
(RTS), is termed as the supply side, while the equipment to be tested is termed as the
test side. In general the test side is assumed to contain a separated generator, which
often can be a distributed generator (DG). The supply side can be a set of generators
and a complex network. The test side may contain a DG, feeder and any local load.
For the simplicity a small network as shown in Fig. 5.1 (a) is considered to explain
the concept. Here the supply side contains a generator v1 and a feeder with the
impedance of Z1 and the test side contains another generator v2 and a feeder with the
impedance of Z2. The network is torn along the network tearing line as shown in Fig.
5.1 (a). After tearing a voltage controlled voltage source is connected at supply side
and a current controlled current source is connected at supply side as shown in Fig.
5.1 (b).
(a)
(b)
Figure 5. 1 Conceptual hardware-software simulation diagram: Current control. (a) The Un-torn Network (b) Torn Network
In Fig. 5.1 (b), the current i1 measurement from the supply side controls the current-
controlled current source i f of the test side. Similarly the voltage-controlled voltage
source vf is controlled by the point of common coupling (PCC) voltage vt.
98
It is to be noted that the connection between the supply side and the test side is
through digital-to-analog converter (DAC) and analog-to-digital converter (ADC).
For example, consider the system of Fig. 5.1. The current signal i1 is passed through
a low pass filter (LPF) and using a DAC sets the reference for i f. Similarly, the
measured voltage vp is passed through a LPF and given as the input vf through an
ADC. There are some stability issues in the system because of the bandwidth
mismatch between the supply side voltage controlled voltage source and the test side
current controlled current source which is an amplifier. LPF1 and LPF2 are used to
overcome the stability problem of the whole system.
Since output signal of the RTS is a low voltage signal and it can not supply any
amount of power to the physical power network therefore the RTS can not be
directly connected to the physical power network. To integrate the RTS and the
physical power network, an amplifier is required that amplifies the RTS output signal
from signal level to power level so that it can interact with physical power network.
In later part of this paper design of a current amplifier will be discussed.
5.3. The Scheme
The single-line diagram of the scheme under test is shown in Fig. 5.2. It is a
distribution system containing the UPS for reliability and power quality
enhancement. It is assumed that the UPS is supplied from a DG with a dc voltage of
Vdc. The load is assumed to be unbalanced and nonlinear. The load is connected at
the far end of a feeder with an impedance of R + jωL, which is supplied by a source
(vs). An LC filter is connected at the output of VSC, the inductance and the
capacitance of which are denoted by Lf and Cf respectively, while the resistance Rf
indicates the circuit losses. The PCC voltage is denoted by vt.
The main purpose of the UPS is to maintain a balanced PCC voltage (vt) irrespective
of unbalance and distortion in the load currents and to share a specific amount of the
load power. It also controls the magnitude of the PCC voltage to a pre-specified
value even when there is a sag or swell in the source voltage. To control the power
flow either from the grid or from the UPS, the angle of the PCC voltage must be
99
controlled. Therefore the reference for the PCC voltage contains a pre-specified
magnitude and an angle that is based on power requirements. The VSC then will
have to track this reference voltage in order to achieve the desired performance. The
amount of power shared by the UPS depends on capability of DG system and
different mode of the UPS operation. In later part of this paper these different modes
will be described.
Figure 5. 2. Distributed Generation scheme under test
The aim is to test this UPS in real time frame in different network condition. This
network is torn along the network tearing line as shown in Fig. 5.2. The portion of
network which is above the tearing line is simulated inside the computer which is
referred here as the supply side. A VSC based current amplifier is connected to the
UPS at PCC’, which amplifies the current signal of RTS and mimics the supply side
network for the UPS. Sine the UPS shares the certain amount of the load power
therefore power flows from UPS to amplifier. To minimize the losses at the time of
testing, this amplifier was designed with power regeneration capability so that the
amplifier can supply back the power to the UPS. The PCC’ voltage is measured with
the help of voltage sensor and fed in to RTS with the help of A to D card. Current i f
from computer simulation is taken out for the reference of amplifier and amplifier
tracks this reference current.
100
When VSC based amplifier tracks this reference current, power is fed from the UPS
to the DC side of the VSC. This power is fed back to the DC bus of UPS. Therefore
only the power required for circuit losses in the whole system is consumed
effectively.
vs
+
RL
is Unbalanced
Non-Linear
load
if*
il
vt
Ps, Qs PL, QL
PCC
VSC
Rf
Lf
CfPU, QU
PCC’
VSC
(Mimicking Load)
if
Power
Feed Back
vt*
Lf1
if*
Reference
A/D Card
D/A Card
Vdc
The Operating
DGVdg
Figure 5. 3 Network Tearing Scheme
5.3.1. The UPS Model
Fig. 5.4 shows the structure of the UPS. It contains three H-Bridge VSCs. All three
VSCs are connected to common DC storage source Vdc. Each VSC is connected to
grid through single phase transformer and a capacitor. The three single phase
transformers are used to provide isolation [7]. Leakage inductance of transformer Lf
and the filter capacitor Cf constitute the LC filter for each phase. All three
101
transformers are connected in star and neutral point is connected to the neutral of the
load or it may be grounded if neutral point of load is not available. As far as structure
of single phase converter is concern, it has four switches with anti-parallel
freewheeling diode.
The main purpose of the UPS is to maintain a balanced PCC voltage (vt) irrespective
of unbalance and distortion in the load currents. It also controls the magnitude of the
PCC voltage to a pre-specified value even when there is a sag or swell in the source
voltage. To control the power flow according to the modes described in the previous
section, the angle of the PCC voltage must be controlled. Therefore the reference for
the PCC voltage contains a pre-specified magnitude and an angle that is based on
power requirements. The VSC then will have to track this reference voltage in order
to achieve the desired performance.
Figure 5. 4. UPS structure used in which three separate VSCs are supplied from a common dc storage capacitor.
102
5.3.2. The Amplifier Model
Figure 5. 5 The Structure of Universal Load
Fig. 5.5 shows the structure of the current amplifier. It contains three H-Bridge
VSCs. All three VSCs are connected to the same DC storage source Vdc where UPS
is connected. Each VSC is connected to PCC through single phase transformer.
Leakage inductance of transformer Lfl constitute the L filter for each phase. All three
transformers are connected in star and neutral point is connected to the neutral of the
load or it may be grounded if neutral point of load is not available. However this
current amplifier is amplifying the current signals of RTS but it is not supplying any
amount of power to the system. Because power flow is from USP to the rest of the
system. Therefore this power has to consume by some load. The current amplifier
works as a load for the UPS and can be termed as universal load. But the power
consumed by universal load can be fed back to the DC bus of the UPS to minimize
the power losses. Here this power is fed back to the UPS by making a common DC
bus as shown in Fig. 5.3.
5.4. Reference Generation
Let us define the rms source and PCC voltages as
δ−∠=°∠= ttss VVVV and 0 (5.1)
103
Then from Fig. 5.2, we get the following expression for the active and reactive power
entering the PCC from the source
( )[ ]δδ sincos22 sts
ts VXVVR
XR
VP +−
+= (5.2)
( )[ ]δδ sincos22 sts
ts VRVVX
XR
VQ −−
+= (5.3)
where X = ωL. If |Vs| ≈ |Vt|, the first term inside the bracket on the right hand side of
(5.2) is negative. However, its influence on the positive valued second term is
negligible as R << X. It is clear from (5.2) that real power flow can be controlled
using δ. Because if δ is increased or decreased, the amount of real power can be
increased or decreased accordingly. Therefore the reference PCC voltages are given
by
( )( )( )
°+−=
°−−=
−=
120sin
120sin
sin
δωδωδω
tVv
tVv
tVv
tmrefc
tmrefb
tmrefa
(5.4)
where Vtm is a pre-specified magnitude and δ is controlled according to the power
control mode.
Power Control:
A fixed amount of active power is drawn from the source and the UPS supplies the
balance amount of load requirement. As mentioned before, this can be achieved by
controlling δ. This gives the following power control loop
dt
deKdteKeK s
dssissps ++= ∫δ (5.5)
where es = Psref − Ps, Psref is the reference power which is drawn from the source.
As mentioned earlier, the UPS must regulate the PCC voltage even during a changed
source voltage condition. Suppose a voltage sags occurs causing source voltage (|Vs|)
104
to drop. As per requirement, the PCC voltage |Vt| is still held constant. Hence from
(2), it is evident that δ must increase in order to maintain the power flow constant.
On the contrary, the angle δ must reduce during swell in the source voltage.
Also, it can be seen from (3) that reactive power (Qs) is function of δ. Furthermore,
since |Vs| cos δ < |Vt|, Qs is negative. This means that the UPS supplies reactive
power to the grid. As described above that at the time of sag in source voltage, δ is
increased to maintain Ps constant. This will cause the first term of (5.3) to become
more negative. It means source will draw more reactive power from the UPS during
this condition.
The UPS can be operated in a different mode where the UPS is responsible to supply
the constant power and the source supplies the balance amount of load requirement
[5]. Here in this paper, this second mode of operation is named Mode II operation.
5.5. Control Strategy
5.5.1. Control of UPS: Hybrid Discontinuous Control
A hybrid discontinuous control is used to operate the UPS [5, 10]. This control is
useful, when an LC filter is connected to the output of a single phase converter and
the instantaneous output voltage of filter capacitor (vcf) needs to be controlled.
1S 2S
3S 4S
cfv
Figure 5. 6. VSC scheme to control capacitor voltage.
Fig. 5.3 shows the circuit configuration of a single-phase H-bridge converter with the
LC filter. In this control method, the converter switching decision is made based on
105
both filter inductor current (i f) and filter capacitor voltage. The control is switched
from one stage that is based on inductor current to second stage which is based on
capacitor voltage according to zones. The zonal scheme is shown in Fig. 5.4 for a
sinusoidal reference voltage with zones and hysteresis band. The controller is
assumed to be in Zone-1 when the error is large and it is in Zone-2, when the error is
small (within the hysteresis band). In Zone-1, the control decision is made based on
filter inductor current. When the error reduces as a result of the control action of
Zone-1, the controller switches to Zone-2, where the decision will be made
depending on filter capacitor voltage. However, in both the zones, all three states
(+1, -1 and 0) of converter are used based upon the reference voltage. In + 1 state,
the converter output becomes + Vdc, which is achieved by turning on the switches S1
and S4 and turning off the switches S2 and S3 of Fig. 5.3. Similarly in − 1 state, the
converter output becomes − Vdc that can be achieved by turning on the switches S2
and S3 and turning off the switches S1 and S4. Usually the 0-state is defined when
output voltage of converter is 0 V which is achieved by closing the pair S1-S2 or S3-
S4.
Figure 5. 7. The two zones voltage control scheme.
But in this paper, the 0-state is modified to be a diode state where all the four
switches S1-S4 of the converter are turned off. During this time, the anti-parallel
diodes conduct to bring filter inductor current (i f) to zero. Once i f becomes zero, the
diodes stop conducting and the converter output voltage becomes equal to filter
capacitor voltage (vcf). Because of the major involvement of the diodes, this state is
termed as the diode state in this paper. This state introduces discontinuity in the
106
converter output current (i f). Since the converter current (i f) becomes zero in the
diode state, the next switching for either + 1 or − 1 state, occurs at zero current
resulting in a loss free switching.
5.5.2. Control of Current Amplifier (Universal load):
Since PCC’ voltage is controlled by the UPS. Hence VSC (amplifier) is responsible
to control the current i f. Reference for this current is taken from the computer
simulation with the help of D to A card. This current can be tracked with simple
hysteresis current control (HCC).
( )dctf
f vuvLdt
di×−=
1
1 (5.6)
1
1
=−≤
−=+≥∗
∗
uthenhiielseif
uthenhiiif
ff
ff (5.7)
Usually a Simple HCC results in high switching frequency component in the PCC
voltage. To overcome this problem a capacitor is connected to bypass the switching
frequency ripple in the PCC voltage and it needs a special form of control because of
instability. In this design the capacitor Cf helps to filter out switching frequency
component of both VSC and UPS. Hence the amplifier does not need any special
control, the simple HCC work fine to control the current i f.
Example 5.1: Consider the system shown in Fig. 5.2. It is assumed that the source
voltage vs is balanced and has a magnitude of 11 kV (L-L, rms), which is equal to
about 9 kV (L-N peak). The load is an unbalanced nonlinear load, whose unbalanced
RL components are
Zla = 48.2 + j94.2 Ω, Zlb = 12.2 + j31.4 Ω and Zlc = 24.2 + j60.47 Ω
where the subscripts a, b and c denote the three phases. In addition, a three-phase
rectifier is also connected to the PCC with DC side load of 100 + j31.4 Ω. The feeder
impedance is R + jωL = 3.025 + j18.13 Ω. The UPS parameter are Vdg = 2.8 kV (L-L
107
rms), Rf = 1.5 Ω and Cf = 50 µF. The single-phase transformers are rated 1 MVA, 3
kV/11 kV with a leakage inductance of 2.5%. The UPS is connected to grid at time t
= 0 where it is required to maintain the PCC voltage at 11 kV (L-L rms). It is
assumed that the source power remains constant (Mode-1 control) such that balance
power comes from the UPS. The controller parameters chosen are Kps = −0.025, Kis =
−10.0 and Kds = −10×10−6 in (5.5).
To test this system network was torn according to figure 5.2. Three 1 MVA,
11kV/3kV with 10% leakage inductance, step down single phase transformers are
used for the universal load. The PCC’ voltage is maintained at 11 kV (L-L rms), δ is
controlled according to equation (5.5) based on power requirement from source. This
PCC’ voltage is fed in to computer simulation with the help of A/D cards and the
universal load is controlled to draw current i f.
The active power flowing through the circuit is shown in Fig 5.8(a). The error
between power supplied by UPS in actual network and the torn network is shown in
Fig 5.8(b). Since there is a small error in current tracking of amplifier and also there
is some voltage tracking difference between actual and torn network which is bigger
than current error, therefore there is small error in real power between the actual
network and the torn network. It is clear from Fig. 5.8 (b) that average error in real
power between the actual network and the torn network is less than 6%. For the
power recovery, DC bus of the universal load is connected to the DC bus of the UPS
and it boosts the DC bus voltage by small amount. Although the same controller is
used in both the network yet because of the different DC bus voltages of the actual
and the torn network there is a tracking difference between the actual and the torn
network. Fig 5.8(c) shows the tracking capability of current amplifier. Since the
universal load feed the power back to the UPS therefore only the total losses in
whole circuit is supplied by DG. Fig 5.8(d) shows the total power supplied by DG. It
is clear from the Fig 5.8(d) that the net power supplied by the DG is very small
which is equal to total losses in whole system.
108
0 0.05 0.1 0.15 0.2 0.25-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Time (s)
Power (M
W)
Real Power
LoadSourceUPS
(a)
0 0.05 0.1 0.15 0.2 0.250
0.02
0.04
0.06
0.08
0.1
0.12
Time (s)
Error (M
W)
Error in Real Power
(b)
0 0.05 0.1 0.15-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Current (k
A)
Current Tracking of Universal Load
ActualReference
(c)
0 0.1 0.2 0.250
1
2
3
Time (s)
Power (M
W)
Power Consumed in Total Losses
(d) Figure 5. 8 Performance of UPS in torn Network
To test the performance of UPS (DG) and to investigate the behavior of the torn
network at the time of load change, an extra unbalanced load is connected at t=0.15.
It is clear from Fig 5.9(a) that extra amount of power is supplied by UPS and source
109
power remains constant in torn network as desired. Fig 5.9(b) shows the error
between response of UPS in torn network and actual network. This is clear from the
Fig 5.9(b) that error in transient and steady state responses of UPS is about 5%.
0.14 0.16 0.18 0.2 0.22 0.24 0.261
1.5
2
2.5
3
3.5
4
4.5
Time (s)
Pow
er (M
W)
Real Power
LoadSourceUPS
(a)
0.15 0.2 0.25 0.30.04
0.05
0.06
0.07
0.08
0.09
0.1
Time (s)
Error (M
W)
Error in Real Power
(b) Figure 5. 9 Performance of UPS during load change in torn network
Example 5.2: Here we test the UPS performance at the time of asymmetrical sag in
the utility voltage. With the system operating in steady state, an unsymmetrical
voltage sag is created at t= 0.2 s, where the source voltage of the phases a, b and c
decrease to 7 kV, 6 kV and 8 kV (L-N, peak) respectively. The angles of all the
phase voltages also make a jump of −10°. The UPS however regulates the PCC
voltage at 9 kV (L-N, peak). Fig. 5.11 (a) shows the three phase source voltage with
the asymmetrical sag. It is clear from Fig 5.10 (b) that current amplifier is able to
mimic the rest of the power system network which was simulated inside the RTS. Fig
5.10 (c) shows the power supplied by the UPS in actual and torn network. This figure
explains that the performance of UPS is same torn and actual network.
110
(a)
0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Time (s)
Current (
kA)
ActualReference
(b)
0.15 0.2 0.25 0.3 0.35 0.40
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
Power (M
W)
Real Power Supplied by UPS
Actual NetworkTorn Network
(c) Figure 5. 10 Performance evolution during sag
Example 5.3: In this example the performance of torn network is examined in Mode
II operation where the UPS is responsible to supply the constant power. Here at
t=0.25s an extra load is connected and this extra load is removed at t=0.45s. It is
clear from Fig 5.11 that response of torn network follows the response of actual
network in both transient and steady state.
111
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.551
1.5
2
2.5
3
3.5
4
4.5
Time (s)
Real Power
LoadSourceUPS
(a)
0.2 0.25 0.3 0.35 0.4 0.45 0.50
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
Power (M
W)
Real Power
Actual NetworkTorn Network
(b) Figure 5. 11 Performance evolution during Mode II operation
Example 5.4: Using this network tearing concept we can test the effect of utility
feeder change on UPS in Mode II if a nonlinear load is connected in between the
feeder at t=0.2s. As soon as the nonlinear load is connected, the source current
becomes distorted but UPS keeps PCC voltage undistorted which is clear from Fig
5.13(c).
Figure 5. 12 Scheme for utility feeder change
Fig 5.13(a) shows the power supplied by UPS in torn network and in the actual
network. Universal load is capable to track the current supplied by UPS in actual
network as shown in Fig 5.13(b).
112
0.15 0.2 0.25 0.3 0.350
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
Power (M
W)
UPS Power
Torn NetworkActual Network (Reference)
(a)
0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
Current (
kA)
Curent Traccking of Universal Load
ActualReference
(b)
(c) Figure 5. 13 UPS performance during utility feeder change
Example 5.5: In this example performance of UPS is evaluated during change of
modes. As explained before, in Mode I, constant power is taken from utility and any
variation in load power is supplied by UPS.
0.15 0.2 0.25 0.3 0.350
0.5
1
1.5
2
2.5
3
Time (s)
Power (M
W)
Real Power During Mode Change
Mode Change
UPS Power
Source Power
........ Reference_____ Torn network
Figure 5. 14 Performance of torn network during mode change
113
In Mode II, the constant power is taken from the UPS and the variation in load power
is supplied by utility. In this example the reference for constant power is set at 2
MW. It is clear from Fig. 5.14 that at t=0.2s the Mode is changed from I to II and
UPS starts supplying 2MW power to load. Fig 5.11 shows the power responses in
real and torn network both. It is clear from this figure that response of source and
UPS power is very much similar in real and torn network.
Example 5.6: Here we examine the testing of UPS if there is a fault near to PCC.
However if there is a fault near to PCC, UPS will not be able to maintain the
sinusoidal voltage profile at PCC, because the source current and a major part of
UPS current feed the fault current until the fault is removed. Once the faulty portion
is isolated with the help of circuit breaker, UPS supplies the total load power and
maintains sinusoidal voltage profile at PCC. But this network tearing scheme is still
able to test the UPS system when there is fault at utility side.
0.13 0.15 0.17 0.19 0.21-10
-8
-6
-4
-2
0
2
4
6
8
10
Time (s)
Volta
ge (kV
)
Phase A Voltage
Torn NetworkActual
Fault Occurence
CB Opens
(a)
0.15 0.16 0.17 0.18 0.19 0.2-1.5
-1
-0.5
0
0.5
1
Time (s)
Current (
kA)
Phase A UPS Current
Torn N/WActual
(b) Figure 5. 15 Fault evolution using torn network
In this test it is recommended not to have power recovery. Because at the time of
power recovery, DC bus voltage is disturbed slightly. This disturbance in DC bus
voltage reflects to the PCC voltage when there is a fault near to PCC. There for to
match voltage profile during fault it is recommended to disconnected power recovery
114
unit and feed universal load with separate load. However power losses in this case
will not be severe because fault duration is always very small. Once fault is removed,
power recovery unit is connected again.
5.6. Conclusions
This paper provides a solution for testing of distributed generation system with the
help of hardware in loop concept. This testing opens the way to designs the structure
and control of DG system so that it works effectively in the situations that will be
encountered by DG while connected to main grid. The effect of the change in utility
side can also be tested.
A current amplifier in the form of universal load with power regeneration capability
is designed that can mimic any kind of load for DG. Since the universal load has the
power regeneration capability therefore, there are small power losses during the
testing.
References
[1] R. Kuffel et al, “RTDS – a fully digital power system simulator operating in real-
time,” Digital Power System Simulators, ICDS’95, 1995.
[2] G. Sybille and P. Giroux, “Simulation of FACTS controllers using the MATLAB
power system blockset and Hypersim real-time simulator,” IEE PES Panel
Session on Digital Simulations of FACTS and Custom Power Controllers,
Winter Meeting, New York, 2002.
[3] C. A. Rabbath, M. Abdoune and J. Belanger, “Effective real-time simulations of
event-based systems,” Proceedings of the 2000 Winter Simulation Conference,
2000.
[4] C. Zhang, V. K. Vijapurapu, A. K. Srivastava, N. N. Schulz and J. Bastos, “
Hardware-in-the-Loop Simulation of Distance Relay Using RTDS”, Summer
Computer Simulation Conference, San Diego, California, pp. 149-154, 2007.
115
[5] S. Goyal, A. Ghosh and G. Ledwich, “Active Power Flow Control in a
Distribution System Using Discontinuous Voltage Controller”, Electric Power
Systems Research, 2008.
[6] G. Kron, Tensor Analysis of Networks, John Wiley, N.Y., 1939.
[7] B. Han, B. Bae and Y. Jeong, “Load simulator with power recovery capability
based on voltage source converter-inverter set,” Proc. IEE Electric Power
Application, Vol. 153, No. 6, pp. 891-897, 2006.
[8] L. S. Czamecki, G. Chen, H. Ginn and J. Hu, “Phantom Load: A Simulator of
Non-Periodic Currents,” IEEE PES Summer Meeting, Seattle, USA, pp. 988-993,
2000.
[9] I. Ando, I. Takahashi, Y. Tanaka and M. Ikehara, “Electric Load Controlled by
Computer Simulator having Power Regeneration Ability,” Power Conversion
Conference, Nagaoka, Vol. 2, pp. 925-930, 1997.
[10] S. Goyal, A. Ghosh and G. Ledwich, “A Hybrid Discontinuous Voltage
Controller for DSTATCOM Applications”, IEEE PES General Meeting, USA,
2008.
116
CHAPTER 6
CONCLUSIONS AND FUTURE RESEARCH
“Power Network in the Loop” testing opens a new method for testing of power
system networks using the concept of hardware in the loop. This methodology
provides a more realistic testing of power systems network than pure simulation
testing. A solution for power network in the loop testing has been proposed based on
a high bandwidth switching amplifier.
The structure and control of a high bandwidth switching amplifier has been
demonstrated. A new hybrid discontinuous control method is proposed for the
switching amplifier. Simulation and experimental results confirm that the controller
is computationally feasible in real-time control. As a result of comparative study of
different controllers, it has been verified that hybrid discontinuous control provides
the best performance in terms of voltage tracking and minimum switching events per
fundamental cycle among the all controllers tested.
Because of the good tracking capability of this amplifier, it can be used in several
power system applications. The use of this amplifier in different power system
applications has been demonstrated. The efficiency of this amplifier is shown in
DSTATCOM operating in a voltage control mode where DSTATCOM is able to
hold the PCC voltage constant in the face of various system disturbances and load
changes. The study shows that hybrid discontinuous control is comparatively robust
to LC parameter variations and does not need a redesign for the changes in the
remainder of the power system, DSTATCOM parameters and operating conditions.
The application of this amplifier in distributed generation system has been analyzed.
If a DC power source is connected to the DC bus of the amplifier then it can be used
in real power sharing in a distribution system. Again because of amplifier’s good
voltage tracking capability, it mitigates the power quality problems in a distribution
117
system. This amplifier can be easily controlled to operate the DG system utilizing the
most economic source.
A solution for testing the power network subsystem has been proposed using this
novel switching amplifier. The research shows that a subsystem of a power network
can be interfaced with a real-time simulation using the switching amplifier. The
amplifier is capable of amplifying the voltage signal received from the real-time
simulation and represents the effect of the simulated big network to the subsystem.
Using this concept, the effect of different faults and other conditions in the simulated
network can be evaluated on the subsystem under test.
A testing method for distributed generation system is illustrated on a system of a
universal load with power recovery capability. This testing opens the way to design
the structure and control of a DG system so that it works effectively in the situations
that will be encountered by a DG while connected to main grid. The effect of the
change in utility side can also be tested. A current amplifier in the form of universal
load with power regeneration capability is designed that can mimic any kind of load
for DG. Since the universal load has a power regeneration capability, therefore, there
are low power losses during the testing. Extensive case studies have been included to
show that concept of power network in the loop can be effectively used for
subsystem testing.
Some suggestions for future work are:
1. In this research, a solution for “power network in the loop” is presented where a
big network is torn in two parts. One is simulated in the real-time and other is
interfaced with it using a switching amplifier. This work can be extended for the
testing of more than one subsystem with the same big power network. In such
cases, the total power network can be torn in more than two parts and subsystems
can be interfaced with the single simulated network using multiple numbers of
amplifiers.
2. When the voltage signal is transferred to the test side and current signal is
transferred to the supply side, this tearing is called V-I type of tearing and if the
118
current signal is transferred to the test side and voltage signal is transferred to the
supply side then this tearing is called I-V type of tearing. In this research
simulation study of both types of tearing (Chapter 4 and 5) is shown but the
experimental validation is established only for V-I type of tearing. An
experimental setup for I-V type of tearing can be established.
3. In this research, to test the feasibility of power network in the loop, only a simple
system is simulated in real-time using a DSP. But in the future, a large system
can be simulated in a real time system and tested with the same concept and the
full bandwidth performance can be evaluated.
4. In discontinuous control, if the inductor of the LC filter is very small with respect
to capacitor then the peak current in inductor could be very high which could
result high di/dt and hence EMI issues. This inductor current could be reduced by
increasing the size of the inductor and correspondingly reduce the capacitor to
give the same cutoff frequency. A detailed study of EMI issues and core losses in
discontinuous control would be of interest but is beyond the scope of this
research.
