The Semiconductor Research Cor-poration (SRC) is a cooperative effort ofU.S. companies, with government par-ticipation, to strengthen and maintainthe vitality and competitive ability of theU.S. semiconductor industry. Its pur-poses are carried out by a staff basedin Research Triangle Park, NorthCarolina.

The SRC plans and implements anintegrated program of basic researchin university laboratories. The researchhas been conducted by more than 100faculty and over 400 graduate students,and the topics selected for investigationrelate to a set of long-range industrygoals. During 1986, annual funding forthis program’s fourth year of operationexceeded $18 million.

SRC research is accomplishedthrough contracts that are closelymonitored by the SRC technical staff. Inaddition, hundreds of staff membersfrom the participating companies andgovernment agencies enhance thecooperative process by their activerole in advising the SRC on researchcoordination and planning, evaluatingthe SRC research program, and trans-ferring the research results to practicalapplications.

The SRC’s success has set the stagewithin the industry, and between theindustry and government, to implementother cooperative initiatives that willstrengthen the domestic semiconductortechnology base and, thus, the com-petitiveness of this country in micro-electronics.

Photos: FOREGROUND — Loadingwafers into an ion implanter at NorthCarolina State University;BACKGROUND — Photomicrographof the cross section of semi-insulatingpolycrystalline silicon-on-siliconproduced by high resolutiontransmission electron microscopy.

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Message from theChairman of the Board

and President

In this fourth annual report of theSRC, we are tempted to repeat thoseremarks introducing the first threeannual reports. In the report of 1983,the SRC was declared to be a success;in 1984, we noted the major impact ofthe SRC in both universities and indus-try; and in 1985, the accomplishmentsof the SRC in terms of its mission werenoted. Such repetition would be useful,for in each of the previously cited areasthere is more to be reported. Instead, Iwill comment on the state of the U.S.semiconductor industry and on the roleof the SRC in the industry’s future.

My tenure as Chairman of the Boardof Directors has ended. Klaus Bowersof A T&T will succeed me. It has been apleasure working closely with themembers of the SRC board and theSRC staff for over two years. I feel that Ihave been part of an organization thatis important to the industry, and that

every person with whom I have hadcontact in this connection has a strongcommitment to the SRC and its mission.I thank each of you for making mychairmanship both a pleasure and asuccess.

The winds of change are blowingstrongly through the semiconductorindustry. Even now, actions to forge aneffective trade relationship with Japanare being taken at the highest level ofgovernment, the industry is in theprocess of recovering from a largeexcess of production capacity, newtechnology exchange agreementsbetween international companies arepervading the industry, and a height-ened awareness of the importance ofsemiconductors to the long-rangenational security and economic futureof the United States is sweeping thehalls of government. It is apparent thatcooperative responses to the industry’s

competitiveness problems will be cre-ated and that a strategic nationalapproach will surface in the near future.

The SRC’s role in the industry issolidifying and growing. I have askedLarry Sumney in his comments toaddress this issue in more depth. Ibelieve that the seeds of cooperationwhich have been successfully nurturedin the SRC will expand beyond genericresearch, and that the SRC, as thespringboard of cooperation in semi-conductor technology, will play anincreasingly important role in this ex-pansion. All of us participating in theSRC will derive satisfaction from havingbeen part of these changes.

George M. ScaliseChairman, Board of Directors

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At the SRC’s inception, the foundersdefined its mission to be genericresearch and the education of skilledmanpower for the semiconductor indus-try of the United States. In its responseto this mission, the SRC has built astrong integrated research programthat involves meetings of industry anduniversity research representa fives inmany technical areas for planning thedirection and goals, evaluating prog-ress, and assessing the results. Theseforums have provided unique views ofthe technical agenda of the U.S. semi-conductor industry. For example, theSRC has established for the industry10-year goals, which are supported byits research, and is in the course ofevolving a research roadmap. Thisroadmap will apply not just to the activi-ties of the SRC but to all elements of theU.S. research community that supportthese goals.

Because the SRC’s research missionrequires planning and assessment oftechnology on behalf of the industry, ithas become a de facto source ofindustry plans with respect to semi-conductor technology. In this role, theSRC has become involved in addressingneeds of the industry beyondits genericresearch mission. An example is theactivity of the Manufacturing Competi-tiveness Panel (MCP) which is an out-growth of the Manufacturing SciencesProgram. The MCP began because ofthe recognition that broader issues inmanufacturing must be addressed inorder to provide a rational response toindustry needs. The long-range plan ofthe SRC includes recognition of thisexpanded role by initiating industrysupport activities beyond the scope ofthe generic research and educationmissions.

What does this mean? First, the SRCmust view its research as one part of anational semiconductor strategy andintegrated with the government andindustry efforts with which it interfaces.Second, the SRC may be called upon toprovide integrated research support forother cooperative activities such asSEMATECH with resultant impacts onits program. Third, it is important thatthe SRC participate in the formulationof the various components of a nationalstrategy so as to provide an amalga-mated industry input, particularly to theresearch components of this strategy.Finally, through interactions with itsmembers, the SRC must identify needsand priorities that best represent theindustry rather than any one companyor industry sector.

In undertaking this expanded role,the importance of the original missionmust not be lost. Generic research is,and will continue to be, the centralmission of the SRC. However, since anational semiconductor strategy is veryimportant to the industry and its abilityto compete, the SRC has a responsi-bility to provide whatever help it can increating such a strategy. We hope thatour efforts will result in the identificationand creation of mechanisms for addres-sing broad technology questions Asthese changes in the semiconductortechnology base of the U.S. occur,whatever their form, I foresee anexpansion of the SRC, both in itsfunding for generic research and in itsrepresenting the technology of theindustry.

As always, when I refer to the SRC, Iinclude not just the small corporatestaff, but also the industry/governmentrepresentatives who combine theirefforts and cooperation to make theSRC work and ensure its success, andthe faculty and students who performthe research for which the SRC exists.Collectively, we are the SRC.

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Compan iesAT&TAdvanced Micro Devices, IncorporatedApplied Materials, IncorporatedBurroughs CorporationControl Data CorporationDigital Equipment CorporationE.I. du Pont de Nemours & CompanyE-Systems, IncorporatedEastman Kodak CompanyEaton CorporationG CA CorporationGTE Laboratories, IncorporatedGeneral Electric CompanyGeneral Motors CorporationGoodyear Aerospace CorporationHarris CorporationHewlett-Packard CompanyHoneywell Incorporated

IBM CorporationIntel CorporationMonolithic Memories, IncorporatedMonsanto CompanyMotorola, IncorporatedNational Semiconductor CorporationThe Perkin-Elmer CorporationRCA CorporationRockwell International CorporationSEMI, ChapterSilicon Systems, IncorporatedSperry CorporationTexas Instruments IncorporatedUnion Carbide CorporationVarian Associates, IncorporatedWestinghouse Electric CorporationXerox Corporation

*The following companies are included in the Semiconductor Equipment and Materials Institute, Inc., CHAPTER:

ASYST Technologies, Inc. Micrion CorporationDynapert/Amedyne The Micromanipulator Company, Inc.Eagle-Picher Industries, Inc. Micronix CorporationEmergent Technologies Corporation Oneac CorporationFEP Analytic Optical Specialties, Inc.FSI Corporation PT Analytic, Inc.Genus, Inc. Pacific Western Systems, Inc.Gryphon Products Peak Systems, Inc.Hercules Specialty Chemicals Company Sage Enterprises, Inc.Ion Beam Technologies, Inc. The SEMI Group, Inc.Ion Implant Services Silsco, Inc.Lehighton Electronics, Inc. Solid State Equipment CorporationLogical Solutions Technology, Inc. Thermco Systems, Inc.MacDermid, Inc. UTI Instruments CompanyMachine Intelligence Corporation VLSI Standards, inc.Machine Technology, Inc. XMR, Inc.MG Industries/Scientific Gases

**The commitment for individual participation by these companies in the SRC preceded corporate mergers that took place in 1986.

GovernmentDepartment of DefenseNational Science FoundationNational Security Agency

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InstitutionsArizona, University ofArizona State UniversityAuburn UniversityBrown UniversityCalifornia at Berkeley, University ofCalifornia at Los Angeles, University ofCalifornia at Santa Barbara, University ofCalifornia Institute of TechnologyCarnegie-Mellon UniversityCase Western Reserve UniversityClemson UniversityColorado State UniversityColumbia UniversityCornell UniversityDuke UniversityFlorida, University ofFlorida State UniversityGeorgia Institute of TechnologyIllinois at Urbana/Champaign, University ofIowa, University ofThe Johns Hopkins UniversityLehigh University

Massachusetts Institute of TechnologyMichigan, University ofMicroelectronics Center of North CarolinaMinnesota, University ofNebraska at Lincoln, University ofNorth Carolina at Chapel Hill, University ofNorth Carolina State UniversityNotre Dame, University ofOregon Graduate CenterThe Pennsylvania State UniversityPurdue UniversityRensselaer Polytechnic InstituteResearch Triangle InstituteRochester, University ofSouthern California, University ofStanford UniversityTexas at Austin, University ofThe Texas A&M UniversityVermont, University ofWisconsin, University ofYale University

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MissionToward the end of the 1970s, trends

began to indicate that the U.S. waslosing the comfortable margin of worldleadership in microelectronics tech-nology and the ability to compete suc-cessfully for domestic and internationalmarkets which it had enjoyed since theinvention of the transistor four decadesearlier. In response to these trends,eleven companies with an interest inintegrated circuits formed the SRC in1982 as a nonprofit organization throughwhich they could cooperate to maintainthe vitality and competitiveness of theU.S. semiconductor industry.

Two priorities were identified for theSRC’s initial mission: establishing anefficient program of basic research toaccelerate growth of the technologybase for the semiconductor industry,and increasing the supply of well-educated manpower for the industry.

In response to this mission, activitiesof the SRC during the first four years ofoperation have centered around plan-ning and implementing an integratedprogram of cooperative research thatis conducted at already existing re-search facilities on the campuses ofU.S. universities. Since 1982, the SRChas directed cumulative funding inexcess of $60 million to the support ofthis research.

In 1986, the Board of Directorsexpanded the mission in recognition ofa role for the SRC in responding to abroader set of industry needs. Theseare referred to as Industry SupportActivities and include expansion of thecooperative concept, industry inter-actions, and integration with comple-mentary research programs.

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Support and GuidanceThe SRC addresses its assigned

mission by:

using as input the resources, bothfinancial and manpower, madeavailable by the industry and gov-ernment participants, and

providing as output the researchresults from the universities, grad-uates that enter the universitymanpowerpools, and the productsof its Industry Support Activities.

Thirty-five companies providedfunding for the SRC in 1986, including achapter member that is an associationof thirty-three small equipment andmaterials suppliers. Beginning in Sep-tember of 1986, three agencies of theFederal Government became SRC par-ticipants through a Memorandum ofUnderstanding between the SRC andthe National Science Foundation.

The industry and government par-ticipants also contribute thousands ofman-hours by hundreds of staff mem-bers to advise the SRC on the selectionof research initiatives; to establishrelevancy of the research to the needsof the industry; and to transfer new tech-nology from the university laboratoriesto industry for testing, development,and practical application.

THE BOARD OF DIRECTORS is theSRC’s policymaking body; and during1986, the voting membership included16 representatives from member com-panies and the President of the SRC.

THE TECHNICAL ADVISORYBOARD (TAB) is the SRC’s major re-search advisory group and the primetechnical interface to the staff of thefunding participants (see membershiproster on pages 34-35). The TABExecutive Committee addresses globalissues and coordinates the activities ofthe three technical committees thatdeal with the separate science areas ofthe research program. In 1986, theExecutive Committee formed sub-committees on technology transfer,invention review, integration of long-range research roadmaps, and the eval-uation of research projects. The TABtechnical committees review researchproposals for new funding, participatein evaluation of ongoing research con-tracts, and annually review each com-ponent of the overall research programfor continuing relevance, quality, andproductivity, and advise the SRC onappropriate actions.

INDUSTRIAL MENTORS are scien-tists or engineers from member com-panies who maintain an active, con-structive interface with principal SRCfaculty researchers. By the end of the1986 calendar year, 280 mentors from41 companies were assigned. Thementors advise the university researchteams on industry knowledge, consulton research techniques, and highlightsignificant new technology. Each yeara survey of the mentors and theirrespective faculty investigators is con-ducted to evaluate the quality of the

Mentor Program, record the interac-tions that have occurred, and list tech-nologies being accessed by membercompanies. Significant positive inter-actions have been reported, rangingfrom donations of research equipmentto instances of the co-authoring ofpapers by mentors and universityprofessors.

INDUSTRIAL RESIDENTS are em-ployees of member companies whojoin the SRC technical staff for periodsof one to two years. As members of thestaff, the residents provide industryperspective to the research programand participate in monitoring the re-search contracts. Having an employeeon site for continuous access to theresearch is an excellent mechanismfor maximizing technology transfer.

The SRC STAFF in 1986 consisted of28 professional and support personnel—including three industry residents, whoprovided coordination, management,and continuity to the cooperative effort.Ten members of this staff were as-signed to management of the researchprogram, four to technology transfer,three to operation of the computer-based information system, and theremainder to administration and gen-eral operations.

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Information DisseminationA variety of SRC initiatives and on-

going events facilitate technology trans-fer among SRC participants from indus-try, government, and universities;among universities; and among mem-ber companies.

WORKSHOPS are the mechanismsfor gaining a broad perspective on aspecific technical area that is beingconsidered as a research initiative.Experienced scientists and engineersare invited from industry, government,and academia to explore the feasibilityand advisability of pursuing the sug-gested initiative. In 1986, the SRC con-ducted two workshops: Software Port-ability to address issues of softwaretechnology transfer from university toindustry, and Computer-IntegratedManufactur ing archi tecture andimplementation.

TOPICAL RESEARCH CONFER-ENCES (TRCs) are conducted on uni-versity campuses to foster active dia-log among SRC researchers fromindustry, government, and universitieson a specific technical topic. A uniqueforum for cooperation, the conferencesserve as a vehicle for early access toresearch results, input from unpub-lished industrial research efforts, andconstructive criticism of the researcharea. During 1986, four TRCs wereconducted:

Bipolar Device Technology at ArizonaState,Manufacturing Sciences at Stanford,

Packaging at Lehigh, andQuarter-Micron CMOS Technology,Part II, at UCLA.

EARLY AWARENESS TECHNICALBRIEFINGS (EATBs) are held on uni-versity campuses to present a priorityreview of a recent invention or technicalbreakthrough. These briefings can beimportant in an industry where timeli-ness is a major competitive asset. Twobriefings, In Situ Laser Processing atStanford and The Automatic SynthesisProject at UC/Berkeley, were pre-sented in 1986.

T E C H N O L O G Y T R A N S F E RCOURSES (TTCs) are conducted onuniversity campuses to provide stafffrom member companies the oppor-tunity for hands-on experience with anew technology in the university labor-atory. Particularly in the case of soft-ware and analytical techniques, a directtransition can be made from universityresearch to industrial use. Taught byuniversity researchers, TechnologyTransfer Courses have proved verypopular. The courses taught in 1986were:

Advanced Ill-V and Silicon DeviceModeling at Purdue,AlDE2.1: An Analog CAD Package atGeorgia Tech,Kinetic modeling of DirectionalPlasma-Etching Processes at MIT,

Process Modeling with SUPREM,SAMPLE, and SlMPL at UC/Berkeley,CHIEFS at Illinois Urbana/Champaign,

GaAs HEMT Device Models atStanford,

FABRICS at Carnegie-Mellon,

Microstructures: Characterizationand E-Beam Lithography at Cornell.

INFORMATION DISSEMINATIONtakes a variety of forms in order toserve the diverse needs of the SRCcommunity.

The SRC library now contains over2200 publications generated from uni-versity research and by staff of the SRCin addition to several video tapes thatare available to member companiesand research investigators. The num-ber of publication requests has risen toover 1000 a month.

information Central is the SRC’scomputer-based information/commun-ication system that operates on a 24-hour basis and accommodates elec-tronic mail, requests for publications,and event registration for over 300remote and local users. In 1986, theresearch abstract database was mademore accessible by the implementationof a new keyword search capability thathas increased usage dramatically.

The monthly SRC Newsletter reacheda circulation of 3600 by the end of1986.

FABRICS Technology Transfer Course at Carnegie-Mellon

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Research and EducationThe environment of the universities

in semiconductor research varies froma small number of very strong institu-tions with large facility investments andstrong and diverse faculties, to smallerschools with several faculty membersand minimal facilities, attempting, withdifficulty, to maintain a productiveresearch niche. The spread betweenthe top and bottom is very large, and itis not unusual to find university effortscompartmented in such a manner thatmonodisciplinary attitudes prevail.

In this environment, the SRC isattempting to bring together teams ofresearchers, to raise the performancecapabilities of second-tier schools, toinitiate research in nontraditional dis-ciplines, and to orient the researchefforts toward goals defined on thebasis of needs.

The SRC provides a cooperativelydefined window on the future of semi-conductor technology. This windowresults from planning and forecastingof technology trends, particularly asaffected by competition, andprovides aset of goals and objectives for theindustry that must be supported bySRC-funded university research.

The role of the universities is toexplore the nature of the variousapproaches for achieving these objec-tives through research that providesknowledge on materials, processes,phenomena, structures, and devices;on the hierarchy of design too/s andapproaches for advanced integratedcircuits and systems; and on themethodology employed in fabricatingthese designs and delivering them ascompetitive products to customers.Contributions to this knowledge base,characterized by the creativity andinnovation that exist in the multidis-ciplinary environment of the university,are the function of SRC research.

THE SRC FELLOWSHIP PROGRAMbegan support in the fall of 1986 for 19graduate students seeking advanceddegrees in microelectronics. The goalof this program is to increase graduatestudent support (beyond that alreadygoing to graduate students associatedwith SRC contracts) in the specificareas of microelectronics that are ofmost interest to SRC companies.Research in which fellowship recipi-ents participate is directed by SRCinvestigators.

SRC Fellow James Comfort withplasma-enhanced epitaxial silicon

reactor in the new clean room atMIT. (See “Low-Temperature

Epitaxy” research highlight onpage 12.)

THE SRC UNIVERSITY ADVISORYCOMMlTTEE (UAC) is an independentbody of university faculty that meetstwice a year, including an annualmeeting with the SRC Board of Direc-tors and TAB, to give counsel on issuesrelative to the university community.This body has an important role inestablishing policy for the researchprogram. (See membership roster onpage 34.)

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Science AreasThe science areas around which the

SRC is organized — design, manufac-turing, and microstructure — were iden-tified early in its history as the beststructure with which to relate to theindustry and the universities. Thescience areas overlap in their activi-ties, and each is strongly connected tothe others through the research thrustsand the technology vehicles, Thesescience areas provide unified re-sponses to the 1994 research goalsthat are focused on complexity, func-

tionality, reliability, and cost. In brief,these goals are to make possible in1994 the prototype production of chipswith (1) 250 times the complexity ofthose available in 1984 (equivalent to a256 Mbit DRAM), (2) functional through-put rates of 5 x 1015 gate-hertz, (3) areliability such that less than 10 failuresoccur in 1 billion operating hours of anintegrated circuit, and (4) a 500-timesreduction in cost per functional elementrelative to that in 1984.

Industry SupportActivitiesFellowship Program

ManufacturingSciencesDesignSciencesMicrostructureSciences

Research ProgramExpenditures $ in Millions

The DESIGN SCIENCES area in-cludes coordinated efforts in systemsynthesis and verification, design fortestability and reliability, design systemintegration, linear integrated circuits,process and device modeling, physicaldesign, and VLSI architectures. Theobjective is to enable the developmentof design systems by SRC membersthat support the rapid design of manu-facturable IC systems which achievespec i f i ed leve ls o f qua l i t y andperformance. The Design Sciencesarea is characterized by a high degreeof productivity as measured by thenumber of design software packagesbeing produced and transferred to SRCmembers, and by the level of scholarlyachievement.

T h e M A N U F A C T U R I N G S C I -ENCES area deals with the quantifi-cation, control, and understanding ofthe semiconductor manufacturingprocesses necessary to achieve apredictable and profitable product out-put. Research is directed to quality,productivity, cost, packaging, CAD/CAM/CAT, and reliability. Efforts in1986 addressed computer-aided man-ufacturing and advanced processingtechnologies, automation, yield en-hancement and reliability, packaging,metrology, and curricula for the educa-t ion o f manufac tu r ing-o r ien tedengineers.

The MICROSTRUCTURE SCI-ENCES area is concerned with thephenomena, materials, and processesused to fabricate semiconductor de-vices, and the integration of these de-vices into VLSI circuits. Five principalthrusts are being addressed: 0.25micron CMOS, in situ processing, bi-polar technology, gallium arsenideintegrated circuits, and quantum de-vices. The goal of this area is to accel-erate the technology for industry mem-bers by 1994 that will lead to logic andmemory capability levels correspondingto 40 x 106 and 200 x 106 transistors persq cm, respectively,. a switching delayof 50 picoseconds; and a power delayproduct of 5 femtojoules per gate.

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Research PlanningThe research activities of the SRC, TECHNOLOGY VEHICLES that

for planning purposes, are viewed in employ the characteristics of futurethree dimensions.. integated circuit products to define

goals for the SRC,

RESEARCH THRUSTS that are theareas of study involved in the reali-zation of all of the technology vehi-cles, and

SCIENCE AREAS that are discipline-based and are used to provide amanagement structure consistentwith that of the industry anduniversities.

The cells in the space defined bythese three dimensions contain thespecific task, contribution, or objectivein each science area for each researchthrust associated with each technologyvehicle. Some cells are empty whileother represent large efforts of theexisting program. Exploratory SRCresearch is also underway that doesnot map into this planning matrix.Exploratory research will continue tobe an important part of the program.

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CMOS andBiCMOSTechnology

The achievement of a 0.25 micronlow-power, high-performance device/circuit and fabrication CMOS andBiCMOS technology is a key accom-plishment of the SRC industry-established goals for 1994. About one-third of the total SRC research effort isdirected to investigations that are sig-nificant to achieving this objective,which is believed to be at the practicalscaling limit of MOSFETs. The principalresearch projects are being performedat the SRC Centers of Excellence andPrograms at the University of Californiaat Berkeley, Cornell University,Carnegie-Mellon University, and theMassachusetts institute of Technology,aided by individual projects at a largenumber of additional universities. Thisresearch thrust is coordinated by theelements shown in the figure entitled,“One-Quarter Micron CMOS Strategy.”

One-Quarter Micron CMOS Strategy

Low Temperature EpitaxyLow temperature processes are essential

to the development of 0.25 micron CMOScircuits. In particular, epitaxial silicon depo-sition temperatures must be reduced fromthe 1050°C to 1250°C levels conventionallyemployed to below 800°C to control dopantredistribution on a submicron scale whilenot allowing a corresponding degradationof the material quality. The critical step inthe deposition of high quality epitaxial sili-con is the in situ surface clean precedingthe deposition. Under the SRC/MIT Pro-gram, “Novel Processing Technologies forSilicon Integrated Circuits,” researchershave developed an in situ low-energy argonsputter cleaning process to remove nativeoxide from a silicon surface without intro-ducing permanent damage. The process

exploits enhanced sputter efficiencies ob-served for silicon and silicon dioxide above600°C, and has been implemented in aunique plasma-enhanced deposition reac-tor for low temperature silicon epitaxialdeposition. The cross-sectional micro-graphs made by transmission electronmicroscopy (TEM), which are shown in theaccompanying figure, dramatically illustratethe results of this technique. The upperTEM image shows heavily dislocated epi-taxial deposits at 750°C, following a high-energy sputter clean. The lower TEM imageshows a dislocation-free film obtained usinga low-energy process.

Professor L. Rafael ReifMassachusetts Institute of Technology

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0.00 1.00 0.00 1.00

x in microns x in microns

Grid Structure (left) and the Final Oxide Shape (right) on a Trenched Surface, Simulated Using SUPREM-IV A

Process SimulationThe development of VLSI processes is Beyond the two-dimensional effects given

becoming more complex owing to both by using SUPREM-IV A, the problems ofreduced device dimensions and the strong three-dimensional device structures are ofdependence of these dimensions on sur- growing importance. For example, trenchesface physics, e.g., stress-dependent oxide are being used for both storage capacitorsgrowth and the effects of point defects on (DRAMS) and for isolation. Preliminarydopant diffusion are both highly two- results of 3D oxidations simulations havedimensional. In this research project, been achieved through the Stanford pro-SUPREM-IV A has been used for process cess simulation efforts, and future investi-simulations such as that in the accom- gations willcontinue to explore and charac-panying figures which show the grid struc- terize both the physical coefficients andture and final oxide shape on a trenched simulation tools for developing advancedsurface. Based on the stress-dependent 2D and 3D structures.oxidation model of Kao, et al. (IEDM, 1985), Professors J.D. Plummer and R.W. Duttonthe simulations accurately predict thinning Stanford Universityat both convex and concave corners.

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Design SystemsThe design of complex integrated

circuits and chips requires the utiliza-tion of design systems rather thanstand-alone sets of design tools. Designsystems provide an environment forthe linkage of collections of tools, theunderlying data management systems,and support for a well-defined userinterface. Moreover, the design systemshould provide a target set of specifi-cations for the development of new oradditional tools.

Because of the geographical distri-bution of the universities involved in theconduct of SRC research and thediverse end-use community for theresearch results, it has become neces-sary for the SRC to take action todevelop guidelines for the universityresearchers to use in the developmentof software tools. As the result of aWorkshop on Software Portability con-ducted by the SRC in 1986, softwaredevelopment guidelines are being estab-lished for use by university researchers.The focus of the effort emphasizes thedefinition and use of software engi-neering principles such as modularity,clearly identified input/output sectionsof code, and clearly defined machine-dependent parameters rather than thespecification of a specific language oroperating system by university re-searchers, although UNIX and C pre-dominate. A second emphasis is on theuse of graphics standards, such asGKS, and widely accepted windowmanagers like X-Windows. To theextent possible, the SRC will supportthe use by research teams of existinginterchange formats, e.g., EDIF, for elec-tronic design and the emerging physi-cal interchange format, PIF.

Several of the SRC research activi-ties have begun to coalesce into designsystems. During 1986, the SRC/University of California at BerkeleyCenter of Excellence began develop-

ment of an integrated design system forintegrated circuits. A new object-oriented data manager and editor,OCT/VEM, which supports design in adistributed computing environment, hasbeen developed as an integral part ofthe design system (see “Synthesis”research highlight). New macromodulegenerators and multilevel logic minimi-zation tools have resulted from theeffort that used the SPUR chip set atBerkeley as an application target forthe new system.

Work continued on the Design Auto-mation System at the SRC/Carnegie-Mellon University Center of Excellencein 1986. A collection of tools hasresulted from the research program;and ULYSSES, an expert system designenvironment, has been developed toaid the IC designer in selecting andlinking design tools in the DesignAutomation System.

A View of the Design Process

Design Systems are not only neededto execute chip-level synthesis andverification but are also needed at thetechnology levels as well. As an exam-ple, the Process Engineer’s Workbenchthat is being developed at Carnegie-Mellon is a design system that isintended to support the design of pro-cesses to achieve a specified set ofcircuit-level performance characteris-tics in the face of the random distur-bances that can occur at each pro-cessing step. Another effort that isunderway at the SRC/Berkeley Centeris to link the SIMPL and SAMPLE toolsthat model device profiles at arbitrarycross sections and lithography pro-cesses, respectively, to other deviceand process modeling tools such asPISCES and SUPREM at Stanford. Thenew physical interchange format, PIF,will be used to link these tools toprovide an integrated modeling, simu-lation, and diagnostic system for theprocess designer.

Graphic contributed byPallab Chatterjee,Texas Instruments Incorporated

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OCT, Object Oriented Data Manager, University of California at Berkeley

SynthesisUnder SRC support, the Berkeley Syn-

thesis Project is a major effort in the area oflogic synthesis, module generation, andmacrocell placement and routing. The short-term goals are to develop a system with thecapability of implementing a microcomputerdesign, beginning from a combinationallogic and latch description and extending tosilicon without manual intervention, and tocreate a layout that is equal to, or betterthan, a manual design in terms of both areaand timing. To date, the focus has been onthe development of new synthesis tech-niques for multilevel combinational logic,embodied in the program MIS; developmentof a new approach to macrocell placementand routing, implemented in the MOSAICOsystem; and to integrate these tools in ageneral-purpose, computer-aided designframework. The framework consists of anobject-oriented data manager, OCT, and anassociated editor, VEM. In addition, anumber of new module generators havebeen developed for the implementation of

both sequential and combinational logicblocks. The researchers are attempting toreimplement SPUR, a VLSI-based multi-processor under development in the Com-puter Science Division, as a vehicle formeasuring progress. Long-range work onthis project includes emphasis on the timingrequirements of such chips in both thesynthesis and placement/routing phasesof design, and as high-quality power andground routing at the macrocell level. Whenthese “low-level” tools are in place, plansinclude extension of the existing system tothe architectural and behavioral levels ofdesign, using the existing system for testingimplementations. Plans also include usingthe synthesis system for comparison ofdifferent design styles and for retargetingdesigns to the emerging Sea-of-Gates semi-custom approaches.

Professors AR. NewtonA.L. Sangiovanni-Vincentelli,and C.H. Sequin

University of California at Berkeley

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FABLE is a knowledge representation language, specializing in manufacturing processes. FABLE is being created for use asa software tool to automate semiconductor manufacturing.

Manufacturing AutomationIn the Manufacturing Automation project,

new high-level programming languages,such as FABLE, are being designed thatuse several levels of abstraction to obtainthe complete specifications for a sequenceof semiconductor manufacturing opera-tions. To demonstrate that these specifica-tions are correct, they will be applied tocontrol both automated manufacturing andsimulation. This project is developing soft-ware technology to maintain and dissemi-nate information about manufacturing oper-ations. Investigators from both the Com-puter Science and the Electrical Engi-neering Departments are involved. Duringthe 1986 contract year, a set of hardware

and software tools were identified andacquired to support the continued devel-opment of FABLE. Four applications proj-ects have been identified that will serveboth to determine specific requirements forFABLE and to implement specific parts ofFABLE to satisfy these requirements. Acourse in ‘Automation of SemiconductorManufacturing” has been conducted oncampus for the first time; and the researchteam at Stanford has started a nationwideelectronic mailing list, IC-CIM, for discus-sion of topics in computer-integrated manu-facturing of integrated circuits.

Professor Krishna C. SaraswatStanford University

16

Bipolar TechnologyAdvanced bipolar technology, producing

submicron self-aligned device structureswith polysilicon contacts, has created aneed for a new bipolar transistor model withmore sophistication than existing ones. TheSRC has reinitiated research efforts toproduce models adequate for this sub-micron bipolar transistor realm. The newlarge-signal model, being developed by theUniversity of Florida, is physical and charge-based, in contrast to the earlier empirical,capacitance-based Gummel-Poon (GP)model. The high-current effects (in the baseand the epitaxial collector), which becomepronounced in contemporary scaled bipolartransistors, are properly accounted for inthe new model. Both ohmic and non-ohmicquasi-saturation are modeled by allowingfor the formation of a current-inducedspace-charge region with a moving boun-dary in the conductivity-modulated epitaxialcollector. The transport in the quasi-neutralbase is characterized, without resorting tothe empirical GP charge-control represen-tation, by extrapolating the analytical solu-tions for current obtained for low and highinjection, and combining the compositesolution with the fundamental integral-charge-control relation to describe thecharge. The charge-based formalism, inconjunction with proper charge partitioning,readily permits the inclusion of the inherentnonreciprocal transcapacitances whichreflect the time delays in the transistor. Thenew model has been implemented inSPICE2 via user-defined control ledsources. When the development is com-plete, the model will be written into thecircuit-simulator code. The implementedmodel is quasi-static and one-dimensional.Non-quasi-static and multidimensionaleffects will eventually be incorporated semi-empirically. With the limited empiricism, themodel is applicable over a wide range ofoperating conditions, and it facilitatesstraightforward parameter extraction with-out excessive optimization.

Professor J.G. FossumUniversity of Florida

Network Representation of the Charge-Based Bipolar npn Transistor Model (above) withReference to the Regional Charges in the One-Dimensional Structure (below)

QB B =QBE + QBC (charge partitioning)

17

Factory Automationand Manufacturing

The 1994 integrated circuit factorymust demonstrate a three-level hier-archy of control: (1) operation control,(2) process control, and (3) processdesign. Operational control coversprocess flow execution and inventorycontrol. Unit processes and their con-trol must assure that the equipmentyield the anticipated results at theexpected particulate contaminationlevel. The illustration below shows howfuture generations of processing equip-ment will function. The inclusion ofadaptive control will be a result of fully-functional computer-integrated manu-facturing (CIM) and computer-aidedfabrication (CAF). Process designcovers the monitoring and feedbackfunctions to assure that the processparameter targets are met and thatprocess-induced defects are kept incontrol. Inherent in the objective of theSRC Manufacturing Sciences programis the development of scientific andengineering talent that can contributeto this field of knowledge and skills thatcan be applied in the semiconductormanufacturing industry.

In any fabrication fine, two forms ofprocess control are possible: quantitycontrol and quality control. The aim ofquantity controlis to maximize through-put in a given period of time, while theaim of the quality control system is tomaximize the number of acceptablechips by maximizing the productionyield. By developing a realistic profitfunction and formulating an equationfor profit maximization, both types ofprocess control can be simultaneouslyperformed.

Requirements for ultra-large-scaleintegrated (VLSI) products are notconsistent with a slow learning curve.International competition will increasein intensity. The United States musthave and implement a strategy leadingto growth and profitability, even thoughdomestic industry may have to con-cede continuing advantages to foreigncompetitors in the cost of labor and thecost of capital.

Functionality of Future Generations of CIM/CAFUltra-Large-Scale Integrated Processing Equipment

RIE Process Modeling

Automated Reactive Ion EtThe SRC/University of Michigan Pro-

gram in Automated Semiconductor Manu-facturing is using reactive ion etching (RIE)as a process vehicle for examining keyissues associated with automated sensing,control, and facilities integration. A dual-chamber SEMI-1000 RIE is now installedand is being interfaced with a 10Mbs MAPnetwork in Michigan’s new Solid-StateFabrication Facility. This network will beused in a prototype testbed for processautomation, offering a guaranteed responsetime, message prioritization, and a hier-archical facility architecture. Software

18

Photo and Diagram Above: New Solid-State Fabrication Facility, University of Michigan

hingdrivers for this network have now beendeveloped as well as a network interface forthe SECS protocol. Companion work inadvanced RIE process modeling now allowsthe calculation of two-dimensional micro-structure etch topographies for a variety ofetching parameters. These models willfacilitate the automatic fine-tuning of etchcharacteristics and process interpretationvia an RIE expert system, also under devel-opment. Work on monolithic integratedsensors for pressure, gas flow, and gasanalysis will provide additional data forequipment control.

Professor Ken D. WiseUniversity of Michigan

Computer-IntegratedManufacturing (CIM)

Efficient operation of an IC produc-tion process requires the timely acqui-sition, processing and utilization of dataat many levels. At the equipment level,accurate models of the equipment areneeded, and advanced sensing tech-niques are required in order to effec-tively achieve real-time control of theequipment-level component of themanufacturing process. At the opera-tional level, data are required on suchattributes as the status of work in prog-ress, manufactur ing schedules,equipment outages and maintenanceschedules, and process yields. Ideally,expertise on the operation of individualequipment and on sets of equipmentshould be provided by the informationsystem to the operations personnel.The chip designer must also beinformation-linked to the manufacturinginformation system, since a know/edgeof yield and performance-loss mecha-nisms due to anomalies on the manu-facturing line can sometimes be amelio-rated by modification of design stylesand/or design rules. In addition, testpatterns generated at the design levelmust be linked to the test applicationequipment on the manufacturing floor.The implication of the requirement forready access to many kinds of data bymany different end users in order toachieve an overall efficiency in opera-tion has motivated the conduct of SRCresearch on Computer-Integrated Man-ufacturing. CIM is characterized byresearch to define information systemarchitectures, data managementmethods, and communication require-ments andprotocols; by the applicationof Knowledge-Based Engineering Prin-ciples; and by the development of im-proved dynamic scheduling algorithms.

19

One-Quarter Micron NMOS lnverter Array

Device/Circuit TechnologyThe illustration shows the complexity of a

0.25 micron NMOS inverter array recentlyfabricated at Cornell University. Theenhancement mode switch device has aphysicalgate length of 0.25 and a gatewidth of 2 A pair of flipped inverters arelocated between horizontally running VDD

(top), GND (middle), and a flipped VDD

(bottom) lines laid out in global metal (Al).An access transistor connects the outputnode of each inverter to vertical columnlines running in local metal (TiW/Al). Theinverter inputs are connected to columninput lines also running in local metal next toeach output column. The gates of theaccess transistors are controlled via local

metal row lines running between each VDD-GND line pair. The scale marker shows the2 width of the active region of the 0.25

NMOS switch device running verticallybetween the column lines. Since this chiphas been fabricated using hybrid, direct-write electron beam lithography for gates,and optical lithography for all other features,only the active devices have been scaled to0.25 size. Especially, local-metal toglobal-metal contacts are disproportion-ately large. A full electron beam lithographybasedprocess is currently being developed.

Professor J. P. KrusiusCornell University

20

Linear Integrated CircuitsDigital signal processing is widely

expected to assume a crucial role insustaining the growth of semiconductorelectronics. However, the scaling ofMOS VLSI technology that makes digi-tal processing increasingly attractivealso severely constrains the dynamicrange available for implementing theinterfaces between the analog and digi-tal representation of signals within thatsame technology. Oversampled dataconversion architectures offer a meansof resolving this dilemma. In thesearchitectures, sampling at well abovethe Nyquistrate is combined with nega-tive feedback and digital filtering toefficiently exchange resolution in timefor that in amplitude. Such convertersthus exploit the enhanced density andspeed of scaled digital circuits to easethe difficulty of integrating complexanalog circuit functions. An SRC-sponsored research program has beeninitiated at Stanford under the directionof Professor Bruce Wooley to explore indepth the design of oversampled dataacquisition systems within the contextof their implementation in a CMOS VLSItechnology.

Several other projects are underwayto improve the quality of design supportavailable for linear integrated circuitdesigners. At Georgia Tech, an analogdesign platform, called AIDE2, has beendeveloped to explore design method-ologies for switched capacitor circuitsand mixed analog digital application-specific integrated circuits. Analogdesign tools must work in the ‘assistantmode’ for complex designs that pushthe limits ofprecision andperformance

A second project to design dataconverters for digital signal processingapplications is underway at the Mas-sachusetts Institute of Technology. Thisconverter will use the new BiCMOSprocess being developed at MIT inorder to achieve high performance andaccuracy. A self-calibrated pipelineA/D converter architecture, as shownin the accompanying figure, is plannedas the test vehicle for the new BiCMOSprocess. The architecture shown offersreduced complexity over other pipe-lined schemes because sample andhold elements have been eliminatedand an analog multiplier is not required.The immediate design goal of this proj-ect is to develop a 16-bit 500 KHzconverter using a standard three micronCMOS process. The performance char-acteristics of the CMOS Op Amp andcomparator that have been designedare listed in the following Table.

Pipelined Self-Calibrating A/D Converter Showing the First Two Stages

and in the ‘compiler mode’ for simpledesigns requiring a unique grouping orinterconnection of ordinary analogfunctions. A second project to developdesign techniques for switched capaci-tor signal processing circuits, whichtake advantage of scaled technologiesand that close/y approach the funda-mental limits in area and power, isunderway at the University of Californiaat Berkeley. Researchers at Carnegie-Mellon University are investigating theapplication of Knowledge-Based Engi-neering principles to the design of abroad class of operational amplifiersand, ultimately, data converters. Afunctional analog circuit designer’sworkbench that supports incrementalsimulation of complex analog circuitshas resulted from a research activity atthe California Institute of Technology. Aresearch activity at Nebraska is devel-oping design principles for the synthe-sis of balanced, continuous-time, high-performance analog circuits in MOStechnology.

21

Focused Ion Beam System Focused-Ion Beam System at

A major SRC-sponsored program in thearea of focused-ion beam (FIB) technologyis underway at Rensselaer PolytechnicInstitute. This research effort has the overallobjective of developing FIB technology forthe fabrication of novel semiconductordevices. The three major research tasks ofthe overall program are FIB system devel-opment, liquid metal ion source research,and novel devices.

The FIB system shown in the accom-panying photograph was installed at RPI inMarch, 1986, and logged approximately500 hours of “beam” time during its first 12

months of operation. The sample insertionand preparation chamber is located on theright; the ion column and the workingchamber are located in the center; and twohigh-voltage and source-control units, andthe detection and display rack are locatedon the left. ion sources used in the systemhave been Ga, Au/Si, Pd/B. Ion beamdiameter as small as 1500-2000 angstromshas been observed at an acceleratingenergy of 95 Kev.

Rensselaer PolytechnicInstitute. Professor A.J. Steckland graduate student Cheng-Ming Lin are shown observinga focused-ion beam image of

a calibration grid.

Professor A.J. SfecklRensselaer Polyfechnic Institute

22

Technology Transferfrom the Universityo f Arizona

Two software packages with documen-tation, developed by SRC researchers atArizona, were requested by and delivered toseveral member companies in 1986. Thecompanies performed beta testing to proveout the software, and to assess its accuracyand convenience of use.

Software called UAC was developed forcalculating the Maxwellcapacitance matrixfor 2-D systems of conductors of arbitrarycross section, and of arbitrary number,placed in arbitrary positions in one of threepossible dielectric/ground plane geome-tries. UAC also calculates the associatedinductance matrix for the conductor sys-tems. UAC enables the calculation of con-ductor fine capacitance, and in certaincases inductance, for two-dimensionalfine-to-ground and fine-to-fine geometries.Characteristic impedance, and couplingimpedance, can be calculated from theoutput. Companies serving as beta testsites for this software include AT&T BellLaboratories, Burroughs, Du Pont, GTE,Honeywell (three beta test sites), General

Motors/Hughes Aircraft, IBM, Motorola, andRockwell International.

A second design/analysis software pack-age, called PCUAL, enables calculation ofline inductance directly, including caseswhere calculation of the Maxwell capaci-tance matrix may be difficult. Companiesserving as beta test sites for this softwareinclude AT&T Bell Laboratories, Burroughs,Du Pont, Hewlett-Packard, General Motors/Hughes Aircraft, IBM (two beta test sites),Motorola, and Rockwell International. Eachcompany agreed to apply UAC1.1 to prob-lems of the company’s choice and to share(with the University of Arizona) qualitativeand quantitative results of that application.While comparing UAC1.1 with more cum-bersome but well-proven analysis tools,one member company employee has writ-ten, “I am pleased to report that our pre-liminary results indicate that UAC1.1 isquicker, much easier to use, and veryaccurate over our range of application.”

Professor J.L. PrinceUniversity of Arizona

Testable RAM Design

Configuration Used for Inductance Modeling

RAM Organization Designed for Testab ility

Figure illustration for “Testable RAM Design”By P. Mazumder and J.H. Patel,Computer Systems Group.

Conventional testing strategies for ran-dom access memories (RAMs) usuallyrequire a number of test patterns for an n-bitmemory element that is proportional to n2.The implication is that RAM test time, andhence cost, becomes prohibitive as memorysizes continue to increase. Researchersfrom the SRC Program in Reliable VLSIArchitectures have recently proposed atestable RAM design that may drasticallyreduce RAM test time. This design incor-porates a modified bit-line decoder and aparallel comparator so that in test modeseveral hundred bits are accessed andcompared in one cycle. The scheme isquite general and can be used to implementvarious pattern-sensitive test algorithms forRAMs and content-addressable memories,and is also amenable to built-in self-testimplementation.

Professor J.H. PatelUniversity of Illinois at Urbana/Champaign

23

Metrology andSensors

Particle transport to a wafer surfaceand capture by that surface depend onmany variables such as aerosol velocityand particle size. While gravity is aminor mechanism for submicron aero-sol capture by a wafer, it can be thedominant mechanism for capture oflarger aerosol particles. Diffusion, inter-ception, and inertial impaction are theclassical mechanisms by which filterscapture submicron particles; they applyto wafers as well. All the aerosol proper-ties that influence these mechanismswill affect particle deposition on a wafer.In addition, the wafer surface itself maybe a significant variable primarilythrough electrical capture forces. Elec-trical charges on a surface createelectricalcapture forces that can makeup an important mechanism for thedeposition of submicron aerosol parti-cles on that surface.

Electrostatic forces will receivespecial emphasis in upcoming studiesof particle transport at Research Tri-angle Institute. The use of patterned,electrically biased silicon substrates todeliberately create local areas of poten-tially enhanced electrical capture isproposed as part of the test matrix. Thedependence ofparticle deposition uponelectrical forces will thus be studiedwith higher spatial resolution than here-tofore possible. Appropriate test struc-tures include both metallized patternson oxides and oxidized silicon surfaces.

Subsurface imaging methods areimportant for evaluation of devicegeometries which are inherently three-dimensional. Accurate depth profilingmethods are necessary for failureanalysis and process evaluation. SRCresearch at the University of NorthCarolina at Chapel Hill has shown thatthe electron-beam-induced current(ERIC), BSE, and Time-ResolvedCapacitive Coupling Voltage Contrast(TRCCVC) imaging modes provideinformation about buried structures andlayer thickness.

Particulate Research:The Role o f Particles in Yield Considerations

To be competitive, semiconductor manu-facturing processes must achieve highyields. Since particulate contamination isone of the major yield detractors, the abilityto control and reduce particulates on wafersis crucial to success. This project hasfocused on two important aspects of theoverall problem: the measurement of smallparticles on silicon wafer surfaces, and theinfluence of wafers. One of the most sig-nificant accomplishments of this year’swork was the documentation of the non-monotonic relationship between particlesize and scattered light intensity in lasersurface scanning tools. Over the past fiveyears, laser scanners have become routinetools used to measure particulate contami-nation on production silicon wafers. Theydetect and size single particles resting onan unpatterned wafer by measuring theintensity of light scattered through a knownscattering angle or angles. However, theintensity of the light scattered by a surfaceparticle depends not only on its size but alsoits shape, index of refraction, and the reflec-

tivity of the wafer surface. This last depend-ence means that the relative scatteringintensity of a given surface particle varieswith the oxide thickness of the silicon wafer.For example, as shown in SRC-sponsoredresearch at the Microelectronics Center ofNorth Carolina, the relative scatteringintensity of submicron polystyrene latexspheres (a transparent particle) depositedon silicon wafers of varying oxide thick-nesses varies in phase with the calculatedsurface reflectivity. Also noteworthy is theobservation that, over a narrow size rangein which the particle size is similar to that ofthe laser wavelength, smaller particles canscatter more light than larger particles.While complete theoretical solutions to theproblem of light scattering by a transparentparticle resting on a reflecting plane do notyet exist, these data make clear the need forcareful calibration of a laser scanner inorder to correctly interpret light scatteringfrom surface particles.

Dr. R.P. DonovanMCNC/Research Triangle Institute

The effect of water surface reflectivity upon surface particle light scattering.(Spheres are transparent polystyrene latex)

*Tullis, B.J., “Measuring and Specifying Con-tamination by Process Equipment,” Micro-contamination, 4 (1), pp. 51-55, 1986.

2 4

CCVC images of a floating Hall effect device at different times after initial electron beam exposure.The contrast is generated by the depth dependent response of low energy scattered electrons.

Analysis of Microelectronic Devices Using Scanning Electron MicroscopyAt submicron dimensions, mechanical

probing of devices is nearly impossible andusually destructive when applied to inte-grated circuit fabrication technology. Theelectron beam of the scanning electronmicroscope (SEM) is an alternative tomechanicalprobes and is a standard tool inthe microelectronics industry. Unfortu-nately, many of the SEM imaging modescan potentially induce damage in radiation-sensitive devices. Low energy (<1 keV),

nondestructive SEM imaging techniquesthat avoid radiation damage are beingdeveloped and modeled in this SRC project.Capacitive coupling voltage contrast(CCVC) is a low-energy method that pro-vides both voltage and depth informa lion ofstructures buried under passivation. CCVCutilizes the dynamic response of low energyelectrons near the surface to changes involtage or differences in structure depth.Voltage resolutions of 40 mV have been

recorded using this technique, with a spatialresolution of less than one micrometer.Depth profiling has been performed on bothbiased and floating devices. Analysis canbe performed during manufacturing, sinceno bias is required and no mechanicalprobing is needed.

Professor R.H. PropstUniversity of North Carolina at Chapel Hill

25

Inductive Fault Analysis: Abstraction Levels

Inductive Fault AnalysisFor Very Large Scale Integrated Circuits,

exhaustive testing to insure proper func-tional performance is often prohibitivelyexpensive. In order to reduce this cost,faults should be “graded” so that thosemost likely to occur are tested for first.Towards this end, the concept of InductiveFault Analysis (IFA) has been developed.IFA proceeds by determining the set ofdefects most likely to occur in the manu-facturing process and then determining theeffects of these defects on functional per-formance. This information is then used toguide test vector generation. The inductiveFault Analysis procedure consists of fourmajor steps..

1.

2.

3.

4.

1 . Generation andplacement of physicaldefects employing statistical dataobtained from the fabrication process;

2 . Extraction of geometric and structuralfaults caused by those defects;

3 . Abstraction of those faults to the circuitand logic levels of behavior;

4 . Classification of fault types and theranking of faults based on the likeli-hood of their occurrence.

Given the layout of an integrated circuit, anaccurate customized fault model andassociated ranked fault list can be gener-ated automatically by IFA to take intoaccount technology, process, and layoutcharacteristics. While this approach is stillnew, it has shown some surprising results.For example, an investigation of one CMOScircuit yielded the following observations:

Only about two-thirds of the faultscould be characterized with the tradi-tional single and multiple line stuck-at(zero or one) model;

Fewer than five percent of the faultsinvolved transistors stuck at open;

Approximately one-third of the faultswere bridging faults;

Unusual faults, such as the creation ofnew transistors, were possible.

The fault lists generated via the inductivefault analysis method are used as input to aprototype switch-/eve/ test pattern genera-tion and evaluation system consisting ofthree major components:

CG — Cube genera lion program;TG — Test generation program, em-

ploying search and back&acing;and

MMS — An interface to the fault simu-lator, MOSFLS.

Work is underway to extend the prototypesystem to handle test generation for gen-eralized bridging and break faults, inte-grated logical and topological testing, andthe generation of multipattern testsequences immune to delays and hazards.

Professor John P. ShenCarnegie-Mellon University

26

InterconnectThe understanding of the metallurgy of

thin films is key to the use of silicides in thefabrication of integrated circuits. In particu-lar, the stability of silicides on polycrystallinesilicon is important because of the applica-tion of this structure to interconnections onCMOS gates. During investigations by aresearch team in the Department of Mate-rials Science and Engineering at Cornell, ithas been discovered that the polysiliconlayer can be consumed, allowing directcontact between silicide and gate oxide aswell as deformation of the silicide layer. Attemperatures between 850°C and 900°C,depending on the silicide, the fine-grainpolysilicon dissolves in the silicide andrecrystallizes in large grains of 0.1 to 1.0micrometers. This solid phase transportand recrystallization is sensitive to theamount of impurities in the silicide or poly-silicon. Edge effects can dominate in fine-line structures.

Professor J. W. MayerCornell University

A side view of a CrSi2 layer on poly Siannealed at 900°C showing the deforma-tion of the silicide and the formation ofislands.

Removal of the silicide layer shows that thepoly Si layer has been consumed by trans-port through the silicide layer and subse-quent recrystallization along the peripheryof the silicide lines.

An Example nMOS Circuit and its Boolean Representation. Pairs of variables denote theencoded initial states of the input and state nodes. Formulas S.1,S.0, T.1, and T.0 denote theencoded new states of nodes s and t.

COSMOSOne of the activities in multilevel simula-

tion that has made recent progress is theCOSMOS (Compiled Simulator for MOScircuits) project. This project has devel-oped a new method for switch-level simula-tion, a form of logic simulation that repre-sents a MOS transistsor circuit as a networkof discrete switches. This new methodyields high performance on conventionalcomputers and promises an efficient map-ping onto a variety of simulation accelera-tors. A preprocessor transforms the transis-tor circuit into a functionally equivalentBoolean representation. This representa-tion, produced by the symbolic analyzerANAMOS, captures such aspects of MOScircuits as bidirectional transistors, storedcharge, and different signal strengths, Byencoding logic values 0, 1, and X with pairsof Boolean variables, it can also capture theeffect of indeterminate logic values. For

most MOS circuits, ANAMOS can exploittheir sparse structure to create Booleanrepresentations of size proportional to thecircuit size. For simulation on a conventionalcomputer, the LGCC program transformsthe Boolean representation into a set of Clanguage procedures representing the par-titioned circuit functions, along with a set ofinitialized data structures representing thenetwork structure. This code is compiledtogether with code implementing the eventscheduler and user interface to yield a highperformance simulation program. The re-sulting simulator operates an order of mag-nitude faster than such switch-level simu-lators as MOSSIM II. Current researchincludes implementing fault simulation andmapping the Boolean representation ontosimulation accelerators.

Professor R.E. BryantCarnegie-Mellon University

27

New DeviceConcepts

Promising new device concepts arebeing explored that have the potentialto provide improved performance be-yond those which can be projected forachievement by 0.25 micron CMOStechnology. Many of these conceptsare based on quantum domain struc-tures and utilize the flexibility offered byGaAs materials. Additionally, the SRCand the Institute for Theoretical Physicswill be co-sponsoring a workshop toexplore the transport properties ofdevice structures in the realm of meso-scale physics. These investigationscould lead to the basis for computersthat perform with new architecturalconcepts which are not based on theuse of binary elements.

GaAs-Gate Field EffectTransistor Devices

Recently, the joint SRC team of re-searchers from the University of Californiaat Santa Barbara and Stanford Universityhas developed III-V devices that incorporatea semiconductor-insulator-semiconductor(SISFET) type structure which is interestingbecause of its potentially controllable andhighly uniform threshold voltages. Thethreshold voltages of such devices areindependent of the doping and thicknessesof the epitaxial layers, making SlSFETs a

prime candidate for use in future LSI or VLSIIII-V circuits. The incorporation of a SISFET,which operates in the enhancement mode,and depletion-mode MESFET has beensuccessfully demonstrated and is shownschematically in the upper figure. A scan-ning electron micrograph (SEM), showingthe novel self-aligned ohmic metallizationused, is shown in the lower figure.

Professor James L. MerzUniversity of California at Santa Barbara

2 8

ComplementaryHeterojunctionFET Circuit

For the tandem growth chamber equip-ment at Stanford University, molecularbeam epitaxy (MBE) is being used in thefabrication of the complex heterojunctiondevice structures that support the researchof the Gallium Arsenide Program at theUniversity of California at Santa Barbara.One of the limitations of MBE has been theinability to alternate semiconductor pat-terning and epitaxial growth. This limitationhas been partially due to the backsideindium substrate bonding previously usedin MBE growth and partially to poor epitaxialgrowth in small masked windows. During1986 both of these limitations were over-come by using the dual growth chamberMBE system shown in the photograph.

Professors James S. Harris andRobert W. Dutton

Stanford University

Dual Growth Chamber MBE System, Stanford University

Quantum Dot DeviceStructures

At Cornell University, SRC researchersare investigating device structures in whichelectrons are confined to regions, “quantumdots,” of such dimensions that quantizationin all three spatial dimensions is importantto the properties of the device. The struc-ture chosen for investigation is a two-dimensional electron gas in a quantum wellin GaAs/AIGaAs in which lateral confine-ment is achieved by application of suitablepotential to each of a pair of spatiallymodulated gates above the quantum well(see figure). One gate is a buried Schottkygate in a square mesh configuration with an8000-angstrom pitch, the other an n+ gatein the holes of the mesh. Tunneling iscapacitively induced through an AlGaAsbarrier to an n+ substrate beneath thequantum well. Initial characterization hasshown strong evidence for isolation of theelectron in the quantum well into localizedregions under the n+ gate as desired.

Professor Noel C. MacDonaldCornell University

GaAs/AIGaAs Quantum Well Two-Dimensional Electron Gas Structure

29

The SRC is the organization throughwhich most of the U.S. semiconductorindustry, now with government partici-pation, seeks to identify and can-y outgeneric research addressing nationalneeds in semiconductor technology.Two primary challenges have emergedfrom this collective effort. The first is theneed to employ the available resourcesto obtain the highestpositive impact onU.S. semiconductor technology. Thesecond challenge is to interface withother organizations so as to assure thatthe SRC program is part of a broaderstrategy.

With respect to maximizing its impacton the U.S. technology base, the SRChas continued to refine its planning and

forecasting skills, as well as its under-standing of the role of university re-search. Evidence of this effort is dis-tributed throughout this report. Thechallenge is to continue to refine theprocess by which the industry, govern-ment, universities, and the SRC staffcarry out generic semiconductor re-search in order to increase the effec-tiveness of this team effort and toprovide a more productive response tothe need for a continuing flow of newknowledge, creativity, and innovation.Already, U.S. universities are the mostproductive in the world in their contri-butions to technology and science.Progress has been made in thesemanagement processes, and the prod-

uctivity of the universities working withthe SRC has increased considerably.However, more progress is required tomeet competitiveness needs of theU.S. industry.

The roadmap for semiconductortechnology in the U.S. is the central toolforplanning and forecasting. The com-bined technicalinput of the members isused to define technology advancesover the next decade and to provide abasis for R&D investments. For exam-ple, the SRC research program is aninvestment designed to advance theachievement of certain future technicalcapabilities by U.S. industry. The impactof other investments can be related tothe technology roadmap in a similar

manner, and the roadmap can beapplied to the assessment of tech-nology accomplishments in other coun-tries. At present, this roadmap is incom-plete. Only the quarter-micron CMOSbranch exists at a detail level. Both forthe purposes of the SRC and for thepurposes of other efforts addressingthe semiconductor technology base ofthe U.S., the completion of this tech-nology roadmap must be given highpriority by the SRC.

Knowing that the SRC is not alone inaddressing the needs of the U.S. semi-conductor technology base providesthe challenge to work within an overallplan, i.e., a national semiconductorstrategy. A large effort, amounting to

over $2.0 billion a year, is devoted tosemiconductor research and develop-ment in the U.S. A small percentage ofthis is generic research, and an evensmaller portion is carried out by theSRC, approximately one percent of thetotal. Coordination between the SRCand other agencies funding genericresearch is growing, and the interfacesbetween generic research and thelarger efforts in applied research anddevelopment are improving. At present,however, a national strategy does notexist. The SRC is participating in dis-cussions with various bodies to evolvesuch a plan so as to increase theefficiency of all of the national efforts insemiconductors.

Photos: LEFT — Professor Toh-Ming Lu operating the Cluster tonBeam system at Rensselaer Polytechnic Institute; CENTER — the new

Integrated Circuits Laboratory in the Center for Integrated systems,Stanford University; RIGHT — semiconductor research at North

Carolina State University.

University Advisory Committee (UAC)Professor Charles E. Backus

Arizona State UniversityProfessor John G. Linvill

Stanford UniversityProfessor Joseph Stach

Massachusetts Technology Park CorporationProfessor Andrew J. Steckl

Professor David A. Hodges, ChairmanClemson University

University of California at BerkeleyProfessor W.W. Lindemann,

University of Minnesota

Dr. Ralph K. Cavin IIISemiconductor Research Corporation

Professor Stephen W. DirectorCarnegie-Mellon University

Professor David J. Dumin

Professor Paul Penfield Jr.University of California at Santa Barbara

Massachusetts Institute of Technology

Professor Noel C. MacDonaldCornell University

Professor Nino A. MasnariNorth Carolina State University

Professor James L. Merz

Rensselaer Polytechnic InstituteProfessor Ben G. Streetman

University of Texas at AustinProfessor Timothy N. Trick

Professor Kensall D. WiseUniversity of Illinois at Urbana-Champaign

University of Michigan

Technical Advisory Board (TAB)Executive CommitteeAT& T Bell Laboratories

Richard M. GoldsteinAdvanced Micro Devices, Incorporated

J. Philip DowningControl Data Corporation

James R. KeyDigital Equipment Corporation

Kenneth H. SlaterEaton Corporation

Stanley V. JaskolskiGeneral Electric Company

Marvin Garfinkel

Goodyear Aerospace CorporationMelvin H. Davis

Harris CorporationTom L. Haycock

Hewlett-Packard CompanyDragan Ilic, TAB Co-Chairman

Honeywell IncorporatedJames M. Daughton

IBM CorporationBilly Lee Crowder

Intel CorporationAlan Baldwin

Ex Officio MembersGeneral Motors Corporation The Perkin-Elmer Corporation

J. Charles Tracy Donald R. HerriottGeneral Motors/Hughes Aircraft RCA Corporation

Sheldon J. Welles William M. Webster

Monolithic Memories, IncorporatedRobert Bortfeld

Motorola, IncorporatedL. David Sikes

National Semiconductor CorporationCourt Skinner

Semiconductor Research CorporationRobert M. Burger, TAB Co-Chairman

Texas Instruments IncorporatedRobert A. Stehlin

Varian Associates, IncorporatedLarry L. Hansen

The SEMI Group, IncorporatedLarry A. Kolito

34

Technical Advisory Board (TAB) (Continued)

Design Sciences CommitteeAT&T Bell Laboratories Goodyear Aerospace Corporation

Richard M. Goldstein Robert ParkerAdvanced Micro Devices, Incorporated Harris Corporation

Jerry D. Moench James P. SpotoControl Data Corporation Hewlett-Packard Company

Wally B. Edwards James DuleyDigital Equipment Corporation Honeywell Incorporated

Kenneth H. Slater Robert PayneE-Systems, Incorporated IBM Corporation

Charles T. Brodnax Allan A. Anderson, ChairmanEastman Kodak Company Intel Corporation

Teh-Hsuang Lee Henry BlumeGenera/ Electric Company Monolithic Memories, Incorporated

Gary W. Leive William E. MossGeneral Motors Corporation Motorola, Incorporated

Paul J. Ainslie Roger KungGeneral Motors/Hughes Aircraft National Science Foundation

Joseph A. Muslin Bernie Chern

Manufacturing Sciences CommitteeAT& T Bell Laboratories General Motors/Hughes Aircraft

David J. Lando William “Ed” ArmstrongAdvanced Micro Devices, Incorporated Harris Corporation

Colin W.T. Knight John E. MainzerApplied Materials, Incorporated Hewlett-Packard Company

John G. Stewart Robert TillmanControl Data Corporation Honeywell Incorporated

James R. Key Lawrence WelliverE.I. du Pont de Nemours & Company IBM Corporation

Grant A. Beske Billy Lee CrowderEastman Kodak Company Intel Corporation

Rajinder P. Khosla Richard C. DehmelEaton Corporation Monolithic Memories, Incorporated

Stanley V. Jaskolski, Chairman George KernGCA Corporation Motorola, Incorporated

John Bruning Jack L. SaltichGTE Laboratories, Incorporated National Science Foundation

Kothandaraman Ravindhran Michael WoznyGeneral Motors Corporation National Security Agency

Ronald K. Reger Clinton Brooks

Microstructure Sciences CommitteeA T&T Bell Laboratories Hewlett-Packard Company

H.J. Levinstein, Chairman Skip RungAdvanced Micro Devices, Incorporated Honeywell Incorporated

Ron Das Jack HuangBurroughs Corporation IBM Corporation

Rakesh Kumar E.J. RymaszewskiControl Data Corporation lntel Corporation

C.T. Naber Alan BaldwinE. I. du Pont de Nemours & Company Monolithic Memories, Incorporated

Denis G. Kelemen Robert BortfeldEastman Kodak Company Monsanto Company

David L. Losee Harold W. KorbGeneral Electric Company Motorola, Incorporated

Marvin Garfinkel, Vice Chairman Jim RuggGeneral Motors Corporation National Science Foundation

Edward G. Whitaker Donald J. SilversmithGeneral Motors/Hughes Aircraft National Security Agency

Richard C. Henderson Nancy WelkerHarris Corporation National Semiconductor Corporation

A.L. Rivoli Court Skinner

National Security AgencyDennis Heinbuch

National Semiconductor CorporationJim Gordon

Rockwell International CorporationMoiz M. Beguwala

Silicon Systems, IncorporatedGary Kelson

Sperry CorporationAsh Patel

Texas Instruments IncorporatedPallab Chatferjee, Vice Chairman

Westinghouse Electric CorporationVincent Zagardo

Xerox CorporationDavid Franco

National Semiconductor CorporationManuel Yuen

Rockwell International CorporationMoiz M. Beguwala, Vice Chairman

SEMI/Pacific Western Systems, Inc.William Snow

Silicon Systems, IncorporatedWilliam L. Healey

Texas Instruments IncorporatedP.B. Ghate

Union Carbide CorporationRaymond P. Roberge

Varian Associates, incorporatedIra Weissman

Westinghouse Electric CorporationMichael E. Michael

Xerox CorporationMichael J. Lo

The Perkin-Elmer CorporationHarry Sewell

RCA CorporationNorman Goldsmith

Rockwell International CorporationMoiz M. Beguwala

SEMI/Micrion CorporationJohn Doherty

SEMI/Pacific Western Systems, Inc.William Snow

Sperry CorporationTushar R. Gheewala

Texas Instruments IncorporatedRobert A. Stehlin

Union Carbide CorporationDennis F. Brestovansky

Xerox CorporationJames Vesely

35

36

Board of Directors (Elected May, 1986)

AT&TKlaus D. BowersMichael J. Thompson*

Advanced Micro Devices, Inc.George M. Scalise (Chairman)Anthony B. Holbrook*

Digital Equipment CorporationJeffrey C. KalbRobert B. Palmer*

General Electric/RCAJames E. DykesRichard A. Santilli*

General Motors CorporationRobert J. McMillinNils L. Muench*

Harris CorporationJon E. CornellThomas J. Sanders*

Hewlett-Packard CompanyFred SchwettmannChuck E. Tyler*

IBM CorporationPaul R. LowWilliam T. Siegle*

Intel CorporationGerhard ParkerRobert N. Noyce*

Motorola, Incorpora tedBob J. JenkinsW.J. Kitchen*

National Semiconductor CorporationE. R. ParkerJames B. Owens Jr.*

Semiconductor Research CorporationLarry W. Sumney

Silicon Systems, IncorporatedCarmelo J. SantoroSteve Cooper*

Sperry CorporationJoseph S. Mathias

Texas lnstruments IncorporatedG.R. Mohan RaoDennis D. Buss*

The Perkin-Elmer CorporationGaynor N. Kelley

Xerox CorporationArnold Miller

Ralph E. Darby, Jr., Corporate Secretary (SRC)Jonathan Greenfield (SRC Legal Counsel)

*Alternate Member

SRC Personnel (March, 1987)

Research StaffLarry W. SumneyPresidentMay, 1982

Robert M. BurgerStaff Vice President, ResearchSeptember, 1982

Ralph K. Cavin, IIIDirector, Design SciencesAugust, 1983

William C. HoltonDirector, Microstructure SciencesMarch, 1984

D. Howard PhillipsDirector, Manufacturing SciencesApril, 1985

Richard A. LucicDirector, Technology TransferJanuary, 1986

Jeffrey A. Coriale(Resident from Harris)Program Manager, Microstructure SciencesNovember, 1984

Shakir A. Abbas(Resident from IBM)Program Manager,

Microstructure/Manufacturing SciencesSeptember, 1985

Phillip A. Lutz(Resident from General Motors)Program Manager, Manufacturing SciencesFebruary, 1986

Administrative and Support StaffRalph E. Darby, Jr.Director, AdministrationFebruary, 1983

Michael D. ConnellyManager, lnformation SystemsDecember, 1983

Richard D. LaScalaManager, Contracts and GrantsFebruary, 1984

Wayne M. WagonerManager, FinanceApril, 1983

Administrative and Support Staff (continued)

Marian U. ReganEditorial CoordinatorNovember, 1982

Cheryl L. TaylorAdministrative AssistantOctober, 1984

Kimberly A. OliveFinancial AssistantOctober, 1984

Brian T.N. Stokeslnformation Systems AnalystOctober, 1984

Barbara H. NelsonApplications AnalystOctober, 1985

Judy B. SmithEvents CoordinatorJanuary, 1986

Kathy W. BarbourPublications CoordinatorFebruary, 1986

Bonnie A. BeattyResearch AssistantNovember, 1986

Ruth G. PoleyPublications CoordinatorNovember, 1986

Krista A. LindaberySecretaryNovember, 1984

Adrienne M. SeverinoSecretaryOctober, 1986

Cindy W. RaySecretaryNovember, 1986

Shirley B. WorleySecretaryJanuary, 1987

Linda F. CarterReceptionistJanuary, 1987

Debra H. BallardClerical AssistantJanuary, 1987

37