The Hardware/Software Interface Editionmenasce/cs465/slides-new/Chapter_04.pdfThe Hardware/Software...
Transcript of The Hardware/Software Interface Editionmenasce/cs465/slides-new/Chapter_04.pdfThe Hardware/Software...
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface
5th Edition
Chapter 4
The Processor
Chapter 4 — The Processor — 2
Introduction n CPU performance factors
n Instruction count n Determined by ISA and compiler
n CPI and Cycle time n Determined by CPU hardware
n We will examine two MIPS implementations n A simplified version n A more realistic pipelined version
n Simple subset, shows most aspects n Memory reference: lw, sw n Arithmetic/logical: add, sub, and, or, slt n Control transfer: beq, j
§4.1 Introduction
Chapter 4 — The Processor — 3
Instruction Execution n PC → instruction memory, fetch instruction n Register numbers → register file, read registers n Depending on instruction class
n Use ALU to calculate n Arithmetic result n Memory address for load/store n Branch target address
n Access data memory for load/store n PC ← target address (for jumps) or PC + 4 (for next
instruction)
Chapter 4 — The Processor — 4
CPU Overview
Chapter 4 — The Processor — 5
Multiplexers n Can’t just join
wires together n Use multiplexers
Chapter 4 — The Processor — 6
A Multiplexer
AND
AND
OR
A
B
S
C A
B
C 0
1
M U X
S
inverter
Chapter 4 — The Processor — 7
A Multiplexer
AND
AND
OR
A
B
S
A A
B
C 0
1
M U X
S
0
1 A
0
Chapter 4 — The Processor — 8
A Multiplexer
AND
AND
OR
A
B
S
B A
B
C 0
1
M U X
S
1
0 0
B
Chapter 4 — The Processor — 9
Control
Chapter 4 — The Processor — 10
Logic Design Basics §4.2 Logic D
esign Conventions
n Information encoded in binary n Low voltage = 0, High voltage = 1 n One wire per bit n Multi-bit data encoded on multi-wire buses
n Combinational element n Operate on data n Output is a function of input (no internal
storage) n State (sequential) elements
n Store information
Chapter 4 — The Processor — 11
Combinational Elements
n AND-gate n Y = A & B A B Y
I0 I1 Y
M u x
S
n Multiplexer n Y = S ? I1 : I0
A
B Y +
A
B
Y ALU
F
n Adder n Y = A + B
n Arithmetic/Logic Unit n Y = F(A, B)
Chapter 4 — The Processor — 12
Sequential Elements n Register: stores data in a circuit
n Uses a clock signal to determine when to update the stored value
n Edge-triggered: update when Clk changes from 0 to 1
D
Clk
Q Clk
D
Q
Chapter 4 — The Processor — 13
Sequential Elements n Register with write control
n Only updates on clock edge when write control input is 1
n Used when stored value is required later
D
Clk
Q Write
Write
D
Q
Clk
Chapter 4 — The Processor — 14
Clocking Methodology n Combinational logic transforms data during
clock cycles n Between clock edges n Input from state elements, output to state
element n Longest delay determines clock period
Chapter 4 — The Processor — 15
Building a Datapath n Datapath
n Elements that process data and addresses in the CPU
n Registers, ALUs, mux’s, memories, …
n We will build a MIPS datapath incrementally n Refining the overview design
§4.3 Building a D
atapath
Chapter 4 — The Processor — 16
Instruction Fetch
32-bit register
Increment by 4 for next instruction
Chapter 4 — The Processor — 17
R-Format Instructions n Read two register operands (e.g., $t2, $t3) n Perform arithmetic/logical operation n Write register result (e.g., $t1)
add $t1, $t2, $t3
Chapter 4 — The Processor — 18
Load/Store Instructions n Read register operands ($t2) n Calculate address using 16-bit offset
n Use ALU, but sign-extend offset n Load: Read memory and update register (e.g.,
$t1) n Store: Write register value to memory
lw $t1, off($t2)
Chapter 4 — The Processor — 19
Branch Instructions n Read register operands ($t1, $t2) n Compare operands
n Use ALU, subtract and check Zero output n Calculate target address
n Sign-extend displacement n Shift left 2 places (word displacement) n Add to PC + 4
n Already calculated by instruction fetch
beq $t1, $t2, offset
Chapter 4 — The Processor — 20
Branch Instructions
Just re-routes
wires
Sign-bit wire replicated
beq $t1, $t2, offset
Chapter 4 — The Processor — 21
Composing the Elements n First-cut data path does an instruction in
one clock cycle n Each datapath element can only do one
function at a time n Hence, we need separate instruction and data
memories n Use multiplexers where alternate data
sources are used for different instructions
Chapter 4 — The Processor — 22
R-Type/Load/Store Datapath
add $t1, $t2, $t3 lw $t1, off($t2) sw $t1, off($t2)
0
0
Chapter 4 — The Processor — 23
R-Type/Load/Store Datapath
add $t1, $t2, $t3
$t2
$t3
$t1
0
0
Chapter 4 — The Processor — 24
R-Type/Load/Store Datapath
add $t1, $t2, $t3
$t2
$t3
$t1
$t2
$t3
0
0
0
Chapter 4 — The Processor — 25
R-Type/Load/Store Datapath
add $t1, $t2, $t3
$t2
$t3
$t1
$t2
$t3
0
add
0
$t2+$t3
0
0
Chapter 4 — The Processor — 26
R-Type/Load/Store Datapath
add $t1, $t2, $t3
$t2
$t3
$t1
$t2
$t3
0
add
0
$t2+$t3
$t2+$t3
1
0
0
Chapter 4 — The Processor — 27
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
0
1
Chapter 4 — The Processor — 28
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
0
1
Chapter 4 — The Processor — 29
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
$t2+off add 0
1
Chapter 4 — The Processor — 30
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
$t2+off add
1
1
0
Chapter 4 — The Processor — 31
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
$t2+off add
1
1
0
Mem [$t2+off]
Chapter 4 — The Processor — 32
R-Type/Load/Store Datapath
lw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
$t2+off add
1
1
0
Mem [$t2+off]
1
Chapter 4 — The Processor — 33
R-Type/Load/Store Datapath
sw $t1, off($t2)
$t2
$t1
off
1
0
Chapter 4 — The Processor — 34
R-Type/Load/Store Datapath
sw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
1
0
$t1
Chapter 4 — The Processor — 35
R-Type/Load/Store Datapath
sw $t1, off($t2)
$t2
$t1
off
32-bit off
$t2
1
$t2+off add 1
0
$t1
Chapter 4 — The Processor — 36
Full Datapath
Chapter 4 — The Processor — 37
ALU Control n ALU used for
n Load/Store: F = add n Branch: F = subtract n R-type: F depends on funct field
§4.4 A Sim
ple Implem
entation Schem
e
ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR
Chapter 4 — The Processor — 38
ALU Control n Assume 2-bit ALUOp derived from opcode
n Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010
subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
Chapter 4 — The Processor — 39
The Main Control Unit n Control signals derived from instruction
0 rs rt rd shamt funct 31:26 5:0 25:21 20:16 15:11 10:6
35 or 43 rs rt address 31:26 25:21 20:16 15:0
4 rs rt address 31:26 25:21 20:16 15:0
R-type
Load/ Store
Branch
opcode always read
read, except for load
write for R-type
and load
sign-extend and add
Chapter 4 — The Processor — 40
Datapath With Control
2
4
Chapter 4 — The Processor — 41
R-Type 0 rs rt rd shamt funct 31:26 5:0 25:21 20:16 15:11 10:6
2
4
Chapter 4 — The Processor — 42
Load 35 or 43 rs rt address 31:26 25:21 20:16 15:0
2
4
Chapter 4 — The Processor — 43
BEQ
2
4
4 rs rt address 31:26 25:21 20:16 15:0
Chapter 4 — The Processor — 44
Implementing Jumps
n Jump uses word address n Update PC with concatenation of
n Top 4 bits of old PC n 26-bit jump address n 00
n Need an extra control signal decoded from opcode
2 address 31:26 25:0
Jump
Chapter 4 — The Processor — 45
Jump 2 address 31:26 25:0
2
4
Chapter 4 — The Processor — 46
ALU Control ALU Control Lines Function
0000 AND 0001 OR 0010 add 0110 subtract 0111 set on less than 1100 NOR
ALUOp Operation 00 Add (lw/sw) 01 Subtract (beq) 10 Operation determined by
function field (0-5) of R-type instructions
Chapter 4 — The Processor — 47
ALU Control Instruction op code
ALUOp Instruction operation
Func Field Desired ALU operation
ALU control input
LW 00 Load word XXXXXX Add 0010 SW 00 Store word XXXXXX Add 0010 Branch eq 01 Branch eq XXXXXX Subtract 0110 R-type 10 Add 100000 Add 0010 R-type 10 Subtract 100010 Subtract 0110 R-type 10 AND 100100 AND 0000 R-type 10 OR 100101 OR 0001 R-type 10 Set on < 101010 Set on < 0111
Chapter 4 — The Processor — 48
Control Unit Design
Instr. RegDst ALU- Src
Mem-to Reg
Reg- Write
MemRead
Mem- Write
Branch ALU Op1
ALU Op0
R-type
1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0 sw X 1 X 0 0 1 0 0 0 beq X 0 X 0 0 0 1 0 1
Chapter 4 — The Processor — 49
Performance Issues n Longest delay determines clock period
n Critical path: load instruction n Instruction memory → register file → ALU →
data memory → register file n Not feasible to vary period for different
instructions n Violates design principle
n Making the common case fast n We will improve performance by pipelining
Chapter 4 — The Processor — 50
Pipelining Analogy n Pipelined laundry: overlapping execution
n Parallelism improves performance
§4.5 An O
verview of P
ipelining n Four loads: n Speedup
= 8/3.5 = 2.3 n Non-stop:
n Speedup = 2n/0.5n + 1.5 ≈ 4 = number of stages
Chapter 4 — The Processor — 51
Pipelining Analogy n With pipelining, how long does it take for a
full load to be ready (from washing to being put away) assuming that each of the four steps takes 30 minutes?
n In steady state, what is the rate (i.e., throughput) at which full loads are complete?
§4.5 An O
verview of P
ipelining
Chapter 4 — The Processor — 52
Pipelining Analogy n With pipelining, how long does it take for a
full load to be ready (from washing to being put away) assuming that each of the four steps takes 30 minutes? n A: 4 x 30 minutes = 2 hours. Same as without pipelining!
n In steady state, what is the rate (i.e., throughput) at which full loads are complete? n A: 1/30 minutes. Four times the throughput without
pipelining.
§4.5 An O
verview of P
ipelining
Chapter 4 — The Processor — 53
MIPS Pipeline n Five stages, one step per stage
1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register
Chapter 4 — The Processor — 54
Pipeline Performance n Assume time for stages is
n 100ps for register read or write n 200ps for other stages
n Compare pipelined datapath with single-cycle datapath
Instr Instr fetch Register read
ALU op Memory access
Register write
Total time
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps
Chapter 4 — The Processor — 55
Pipeline Performance Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 — The Processor — 56
Pipeline Performance Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 — The Processor — 57
Pipeline Performance Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 — The Processor — 58
Pipeline Performance Assume as before that a single cycle implementation takes 800 ps per instruction and that a 5-stage pipeline completes one instruction each 200 ps. How long does it take to execute a program with 1,000,000 instructions in each case? What is the speedup of the pipelining implementation?
Chapter 4 — The Processor — 59
Pipeline Performance Assume as before that a single cycle implementation takes 800 ps per instruction and that a 5-stage pipeline completes one instruction each 200 ps. How long does it take to execute a program with 1,000,000 instructions in each case? A: no pipelined implementation: 1,000,000 * 800 ps = 8 * 108 ps = 8 * 108 * 10-12 sec = 0.0008 sec pipelined implementation 1,000,000 * 200 ps = 2 * 108 ps = 2 * 108 * 10-12 sec = 0.0002 sec What is the speedup of the pipelining implementation? A: 0.0008 / 0.0002 = 4
Chapter 4 — The Processor — 60
Pipeline Speedup n If all stages are balanced
n i.e., all take the same time n Time between instructionspipelined
= Time between instructionsnonpipelined Number of stages
n If not balanced, speedup is less n Speedup due to increased throughput
n Latency (time for each instruction) does not decrease
Chapter 4 — The Processor — 61
Pipelining and ISA Design n MIPS ISA designed for pipelining
n All instructions are 32-bits n Easier to fetch and decode in one cycle n c.f. x86: 1- to 17-byte instructions
n Few and regular instruction formats n Can decode and read registers in one step
n Load/store addressing n Can calculate address in 3rd stage, access memory
in 4th stage n Alignment of memory operands
n Memory access takes only one cycle
Chapter 4 — The Processor — 62
Hazards n Situations that prevent starting the next
instruction in the next cycle n Structural hazards
n A required resource is busy n Data hazard
n Need to wait for previous instruction to complete its data read/write
n Control hazard n Deciding on control action depends on
previous instruction
Chapter 4 — The Processor — 63
Hazards n Situations that prevent starting the next
instruction in the next cycle n Structural hazards
n A required resource is busy n Data hazard
n Need to wait for previous instruction to complete its data read/write
n Control hazard n Deciding on control action depends on
previous instruction
Chapter 4 — The Processor — 64
Structural Hazards n Conflict for use of a resource n In MIPS pipeline with a single memory
n Load/store requires data access n Instruction fetch would have to stall for that
cycle n Would cause a pipeline “bubble”
n Hence, pipelined datapaths require separate instruction/data memories n Or separate instruction/data caches
Chapter 4 — The Processor — 65
Structural Hazard with Single Memory
Resource conflict if instruction and data memory are the same!
Chapter 4 — The Processor — 66
Hazards n Situations that prevent starting the next
instruction in the next cycle n Structural hazards
n A required resource is busy n Data hazard
n Need to wait for previous instruction to complete its data read/write
n Control hazard n Deciding on control action depends on
previous instruction
Chapter 4 — The Processor — 67
Data Hazards n An instruction depends on completion of
data access by a previous instruction n add $s0, $t0, $t1 sub $t2, $s0, $t3
Chapter 4 — The Processor — 68
Forwarding (aka Bypassing) n Use result when it is computed
n Don’t wait for it to be stored in a register n Requires extra connections in the datapath
Chapter 4 — The Processor — 69
Load-Use Data Hazard n Can’t always avoid stalls by forwarding
n If value not computed when needed n Can’t forward backward in time!
Chapter 4 — The Processor — 70
Code Scheduling to Avoid Stalls n Reorder code to avoid use of load result in
the next instruction n C code for A = B + E; C = B + F;
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1, $t4
sw $t5, 16($t0)
stall
stall
lw $t1, 0($t0)
lw $t2, 4($t0)
lw $t4, 8($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
add $t5, $t1, $t4
sw $t5, 16($t0)
11 cycles 13 cycles
Chapter 4 — The Processor — 71
Hazards n Situations that prevent starting the next
instruction in the next cycle n Structural hazards
n A required resource is busy n Data hazard
n Need to wait for previous instruction to complete its data read/write
n Control hazard n Deciding on control action depends on
previous instruction
Chapter 4 — The Processor — 72
Control Hazards n Branch determines flow of control
n Fetching next instruction depends on branch outcome
n Pipeline can’t always fetch correct instruction n Still working on ID stage of branch
n In MIPS pipeline n Need to compare registers and compute
target early in the pipeline n Add hardware to do it in ID stage
Chapter 4 — The Processor — 73
Stall on Branch n Wait until branch outcome determined
before fetching next instruction
Assumes extra hardware to compare registers in the ID stage.
Chapter 4 — The Processor — 74
Stall on Branch Increases CPI n Branch instructions represent 17% of
SPECint2006 benchmark. If they took two clock cycles and the other instructions one clock cycle, what is the CPI?
Chapter 4 — The Processor — 75
Stall on Branch Increases CPI n Branch instructions represent 17% of
SPECint2006 benchmark. If they took two clock cycles and the other instructions one clock cycle, what is the CPI?
n A: CPI = 0.17 * 2 + 0.83 * 1 = 1.17
Chapter 4 — The Processor — 76
Branch Prediction n Longer pipelines can’t readily determine
branch outcome early n Stall penalty becomes unacceptable
n Predict outcome of branch n Only stall if prediction is wrong
n In MIPS pipeline n Can predict branches not taken n Fetch instruction after branch, with no delay
Chapter 4 — The Processor — 77
MIPS with Predict Not Taken
Prediction correct
Prediction incorrect
Chapter 4 — The Processor — 78
More-Realistic Branch Prediction n Static branch prediction
n Based on typical branch behavior n Example: loop and if-statement branches
n Predict backward branches taken n Predict forward branches not taken
n Dynamic branch prediction n Hardware measures actual branch behavior
n e.g., record recent history of each branch
n Assume future behavior will continue the trend n When wrong, stall while re-fetching, and update history
Chapter 4 — The Processor — 79
Pipeline Summary
n Pipelining improves performance by increasing instruction throughput n Executes multiple instructions in parallel n Each instruction has the same latency
n Subject to hazards n Structure, data, control
n Instruction set design affects complexity of pipeline implementation
The BIG Picture
Chapter 4 — The Processor — 80
Checking Pipeline Understanding
n lw $t0, 0($t0) n add $t1, $t0, $t0
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
Chapter 4 — The Processor — 81
Checking Pipeline Understanding
n lw $t0, 0($t0) n add $t1, $t0, $t0
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
$t0 available
$t0 needed
must stall
Chapter 4 — The Processor — 82
Checking Pipeline Understanding
n add $t1, $t0, $t0 n addi $t2, $t0, #5 n addi $t4, $t1, #5
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
Chapter 4 — The Processor — 83
Checking Pipeline Understanding
n add $t1, $t0, $t0 n addi $t2, $t0, #5 n addi $t4, $t1, #5
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
$t1 needed
$t2 available
$t1 available
Chapter 4 — The Processor — 84
Checking Pipeline Understanding
n add $t1, $t0, $t0 n addi $t2, $t0, #5 n addi $t4, $t1, #5
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
$t1 needed
$t2 available
$t1 computed > forward
Chapter 4 — The Processor — 85
Checking Pipeline Understanding
n addi $t1, $t0, #1 n addi $t2, $t0, #2 n addi $t3, $t0, #2 n addi $t3, $t0, #4 n add $t5, $t2, $t1
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
Chapter 4 — The Processor — 86
Checking Pipeline Understanding
n addi $t1, $t0, #1 n addi $t2, $t0, #2 n addi $t3, $t0, #2 n addi $t3, $t0, #4 n add $t5, $t2, $t1
Does the following code sequence must stall, can avoid stalls using forwarding only, or can execute without stalling or forwarding?
$t1 available
$t2 available
$t3 available
$t3 available
$t5 av.
No stalling or forwarding needed.
Chapter 4 — The Processor — 87
MIPS Pipelined Datapath §4.6 P
ipelined Datapath and C
ontrol
WB
MEM
Right-to-left flow leads to hazards
Chapter 4 — The Processor — 88
Pipeline registers n Need registers between stages
n To hold information produced in previous cycle
Chapter 4 — The Processor — 89
Pipeline Operation n Cycle-by-cycle flow of instructions through
the pipelined datapath n “Single-clock-cycle” pipeline diagram
n Shows pipeline usage in a single cycle n Highlight resources used
n c.f. “multi-clock-cycle” diagram n Graph of operation over time
n We’ll look at “single-clock-cycle” diagrams for load & store
Chapter 4 — The Processor — 90
IF for Load, Store, …
Chapter 4 — The Processor — 91
ID for Load, Store, …
Chapter 4 — The Processor — 92
EX for Load
Chapter 4 — The Processor — 93
MEM for Load
Chapter 4 — The Processor — 94
WB for Load
Wrong register number
Chapter 4 — The Processor — 95
Corrected Datapath for Load
Chapter 4 — The Processor — 96
EX for Store
Chapter 4 — The Processor — 97
MEM for Store
Chapter 4 — The Processor — 98
WB for Store
Chapter 4 — The Processor — 99
Multi-Cycle Pipeline Diagram n Form showing resource usage
Chapter 4 — The Processor — 100
Multi-Cycle Pipeline Diagram n Traditional form
Chapter 4 — The Processor — 101
Single-Cycle Pipeline Diagram n State of pipeline in a given cycle
Chapter 4 — The Processor — 102
Pipelined Control (Simplified)
Chapter 4 — The Processor — 103
Pipelined Control n Control signals derived from instruction
n As in single-cycle implementation
Chapter 4 — The Processor — 104
Pipelined Control
Chapter 4 — The Processor — 105
Data Hazards in ALU Instructions n Consider this sequence:
sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2)
n We can resolve hazards with forwarding n How do we detect when to forward?
§4.7 Data H
azards: Forwarding vs. S
talling
Chapter 4 — The Processor — 106
Dependencies & Forwarding
Chapter 4 — The Processor — 107
Remembering n Control signals derived from instruction
0 rs rt rd shamt funct 31:26 5:0 25:21 20:16 15:11 10:6
35 or 43 rs rt address 31:26 25:21 20:16 15:0
4 rs rt address 31:26 25:21 20:16 15:0
R-type
Load/ Store
Branch
opcode always read
read, except for load
write for R-type
and load
sign-extend and add
Chapter 4 — The Processor — 108
Detecting the Need to Forward
n Pass register numbers along pipeline n e.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register n ALU operand register numbers in EX stage
are given by n ID/EX.RegisterRs, ID/EX.RegisterRt
n Data hazards when 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Fwd from EX/MEM pipeline reg
Fwd from MEM/WB pipeline reg
Chapter 4 — The Processor — 109
Pipelined Control add $t1, $t2, $t5 sub $t3, $t1, $t4
add rd=$t1 rs=$t2 rt = $t5
Chapter 4 — The Processor — 110
Pipelined Control add $t1, $t2, $t5 sub $t3, $t1, $t4
add rd=$t1
sub rd=$t3 rs=$t1 rt = $t4
Chapter 4 — The Processor — 111
Pipelined Control add $t1, $t2, $t5 sub $t3, $t1, $t4
add rd=$t1
sub rd=$t3 rs=$t1 rt = $t4
Forward from the EX/MEM pipeline register
Chapter 4 — The Processor — 112
Detecting the Need to Forward n But only if forwarding instruction will write
to a register! n EX/MEM.RegWrite, MEM/WB.RegWrite
n And only if Rd for that instruction is not $zero n EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0
Chapter 4 — The Processor — 113
Forwarding Paths
00
10 01
00
10 01
Chapter 4 — The Processor — 114
Forwarding Conditions Mux Control Source Explanation ForwardA = 00 ID/EX The first ALU operand comes from the register
file. ForwardA = 10 EX/MEM The first ALU operand is forwarded from the
prior ALU result.
ForwardA = 01 MEM/WB The first ALU operand is forwarded from data memory or an earlier ALU result.
ForwardB = 00 ID/EX The second ALU operand comes from the register file.
ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior ALU result.
ForwardB = 01 MEM/WB The second ALU operand is forwarded from data memory or an earlier ALU result.
Chapter 4 — The Processor — 115
Forwarding Conditions n EX hazard
n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 <from prior ALU result>
n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 <from prior ALU result>
n MEM hazard n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 <from data memory or earlier ALU result>
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 <from data memory or earlier ALU result>
Chapter 4 — The Processor — 116
Double Data Hazard n Consider the sequence:
add $1,$1,$2 add $1,$1,$3 add $1,$1,$4
n Both hazards occur n Want to use the most recent
n Revise MEM hazard condition n Only fwd if EX hazard condition isn’t true
Chapter 4 — The Processor — 117
Revised Forwarding Condition n MEM hazard
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 <from data memory or earlier ALU result>
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 <from data memory or earlier ALU result>
Chapter 4 — The Processor — 118
Datapath with Forwarding
Chapter 4 — The Processor — 119
Load-Use Data Hazard
Need to stall for one cycle
Chapter 4 — The Processor — 120
Load-Use Hazard Detection n Check when using instruction is decoded
in ID stage n ALU operand register numbers in ID stage
are given by n IF/ID.RegisterRs, IF/ID.RegisterRt
n Load-use hazard when n ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))
n If detected, stall and insert bubble
Chapter 4 — The Processor — 121
How to Stall the Pipeline n Force control values in ID/EX register
to 0 n EX, MEM and WB do nop (no-operation)
n Prevent update of PC and IF/ID register n Using instruction is decoded again n Following instruction is fetched again n 1-cycle stall allows MEM to read data for lw
n Can subsequently forward to EX stage
Chapter 4 — The Processor — 122
Stall/Bubble in the Pipeline
Stall inserted here
Chapter 4 — The Processor — 123
Stall/Bubble in the Pipeline
Or, more accurately…
Chapter 4 — The Processor — 124
Datapath with Hazard Detection
Chapter 4 — The Processor — 125
Stalls and Performance
n Stalls reduce performance n But are required to get correct results
n Compiler can arrange code to avoid hazards and stalls n Requires knowledge of the pipeline structure
The BIG Picture
Chapter 4 — The Processor — 126
Branch Hazards n If branch outcome determined in MEM
§4.8 Control H
azards
PC
Flush these instructions (Set control values to 0)
Chapter 4 — The Processor — 127
Reducing Branch Delay n Move hardware to determine outcome to ID
stage n Target address adder n Register comparator
n Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7 ... 72: lw $4, 50($7)
Chapter 4 — The Processor — 128
Example: Branch Taken
Chapter 4 — The Processor — 129
Example: Branch Taken
Chapter 4 — The Processor — 130
Data Hazards for Branches n If a comparison register is a destination of
2nd or 3rd preceding ALU instruction
…
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
add $4, $5, $6
add $1, $2, $3
beq $1, $4, target
n Can resolve using forwarding
Chapter 4 — The Processor — 131
Data Hazards for Branches n If a comparison register is a destination of
preceding ALU instruction or 2nd preceding load instruction n Need 1 stall cycle
beq stalled
IF ID EX MEM WB
IF ID EX MEM WB
IF ID
ID EX MEM WB
add $4, $5, $6
lw $1, addr
beq $1, $4, target
Chapter 4 — The Processor — 132
Data Hazards for Branches n If a comparison register is a destination of
immediately preceding load instruction n Need 2 stall cycles
beq stalled
IF ID EX MEM WB
IF ID
ID
ID EX MEM WB
beq stalled
lw $1, addr
beq $1, $0, target
Chapter 4 — The Processor — 133
Dynamic Branch Prediction n In deeper and superscalar pipelines, branch
penalty is more significant n Use dynamic prediction
n Branch prediction buffer (aka branch history table) n Indexed by recent branch instruction addresses n Stores outcome (taken/not taken) n To execute a branch
n Check table, expect the same outcome n Start fetching from fall-through or target n If wrong, flush pipeline and flip prediction
Chapter 4 — The Processor — 134
1-Bit Predictor: Shortcoming n Inner loop branches mispredicted twice!
outer: … … inner: … … beq …, …, inner … beq …, …, outer
n Mispredict as taken on last iteration of inner loop
n Then mispredict as not taken on first iteration of inner loop next time around
Chapter 4 — The Processor — 135
1-Bit Predictor: Shortcoming n Assume inner loop branch is executed 10
times. outer: … … inner: … … beq …, …, inner … beq …, …, outer
n Correctly predict branch is taken 80% of the time.
n But, branch is taken 90% of the time!
Chapter 4 — The Processor — 136
2-Bit Predictor (improvement) n Only change prediction on two successive
mispredictions 4 states: 2 bits
Chapter 4 — The Processor — 137
Calculating the Branch Target n Even with predictor, still need to calculate
the target address n 1-cycle penalty for a taken branch
n Branch target buffer n Cache of target addresses n Indexed by PC when instruction fetched
n If hit and instruction is branch predicted taken, can fetch target immediately
Chapter 4 — The Processor — 138
Exceptions and Interrupts n “Unexpected” events requiring change
in flow of control n Different ISAs use the terms differently
n Exception n Arises within the CPU
n e.g., undefined opcode, overflow, syscall, …
n Interrupt n From an external I/O controller
n Dealing with them without sacrificing performance is hard
§4.9 Exceptions
Chapter 4 — The Processor — 139
Handling Exceptions n In MIPS, exceptions managed by a System
Control Coprocessor (CP0) n Save PC of offending (or interrupted) instruction
n In MIPS: Exception Program Counter (EPC) n Save indication of the problem
n In MIPS: Cause register n We’ll assume 1-bit
n 0 for undefined opcode, 1 for overflow
n Jump to handler at 8000 00180
Chapter 4 — The Processor — 140
An Alternate Mechanism n Vectored Interrupts
n Handler address determined by the cause n Example:
n Undefined opcode: C000 0000 n Overflow: C000 0020 n …: C000 0040
n Instructions either n Deal with the interrupt, or n Jump to real handler
Chapter 4 — The Processor — 141
Handler Actions n Read cause, and transfer to relevant
handler n Determine action required n If restartable
n Take corrective action n use EPC to return to program
n Otherwise n Terminate program n Report error using EPC, cause, …
Chapter 4 — The Processor — 142
Exceptions in a Pipeline n Another form of control hazard n Consider overflow on add in EX stage
add $1, $2, $1
n Prevent $1 from being clobbered n Complete previous instructions n Flush add and subsequent instructions n Set Cause and EPC register values n Transfer control to handler
n Similar to mispredicted branch n Use much of the same hardware
Chapter 4 — The Processor — 143
Pipeline with Exceptions
Chapter 4 — The Processor — 144
Pipeline with Exceptions
Initial address of exception handler
Chapter 4 — The Processor — 145
Exception Properties n Restartable exceptions
n Pipeline can flush the instruction n Handler executes, then returns to the
instruction n Refetched and executed from scratch
n PC saved in EPC register n Identifies causing instruction n Actually PC + 4 is saved
n Handler must adjust by subtracting 4 from EPC
Chapter 4 — The Processor — 146
Exception Example n Exception on add in
40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7) …
n Handler 80000180 sw $25, 1000($0) 80000184 sw $26, 1004($0) …
Chapter 4 — The Processor — 147
Exception Example
Chapter 4 — The Processor — 148
Exception Example
Chapter 4 — The Processor — 149
Multiple Exceptions n Pipelining overlaps multiple instructions
n Could have multiple exceptions at once
n Simple approach: deal with exception from earliest instruction n Flush subsequent instructions n “Precise” exceptions
n In complex pipelines n Multiple instructions issued per cycle n Out-of-order completion n Maintaining precise exceptions is difficult!
Chapter 4 — The Processor — 150
Imprecise Exceptions n Just stop pipeline and save state
n Including exception cause(s)
n Let the handler work out n Which instruction(s) had exceptions n Which to complete or flush
n May require “manual” completion
n Simplifies hardware, but more complex handler software
n Not feasible for complex multiple-issue out-of-order pipelines
Chapter 4 — The Processor — 151
Instruction-Level Parallelism (ILP) n Pipelining: executing multiple instructions in
parallel n To increase ILP
n Deeper pipeline n Less work per stage ⇒ shorter clock cycle
n Multiple issue n Replicate pipeline stages ⇒ multiple pipelines n Start multiple instructions per clock cycle n CPI < 1, so use Instructions Per Cycle (IPC) n E.g., 4GHz 4-way multiple-issue
n 16 BIPS, peak CPI = 0.25, peak IPC = 4 n But dependencies reduce this in practice
§4.10 Parallelism
via Instructions
Chapter 4 — The Processor — 152
Multiple Issue n Static multiple issue
n Compiler groups instructions to be issued together n Packages them into “issue slots” n Compiler detects and avoids hazards
n Dynamic multiple issue n CPU examines instruction stream and chooses
instructions to issue each cycle n Compiler can help by reordering instructions n CPU resolves hazards using advanced techniques at
runtime
Chapter 4 — The Processor — 153
Speculation n “Guess” what to do with an instruction
n Start operation as soon as possible n Check whether guess was right
n If so, complete the operation n If not, roll-back and do the right thing
n Common to static and dynamic multiple issue n Examples
n Speculate on branch outcome n Roll back if path taken is different
n Speculate on load n Roll back if location is updated
Chapter 4 — The Processor — 154
Compiler/Hardware Speculation n Compiler can reorder instructions
n e.g., move load before branch n Can include “fix-up” instructions to recover
from incorrect guess n Hardware can look ahead for instructions
to execute n Buffer results until it determines they are
actually needed n Flush buffers on incorrect speculation
Chapter 4 — The Processor — 155
Speculation and Exceptions n What if exception occurs on a
speculatively executed instruction? n e.g., speculative load before null-pointer check
n Static speculation n Can add ISA support for deferring exceptions
n Dynamic speculation n Can buffer exceptions until instruction
completion (which may not occur)
Chapter 4 — The Processor — 156
Static Multiple Issue n Compiler groups instructions into “issue
packets” n Group of instructions that can be issued on a
single cycle n Determined by pipeline resources required
n Think of an issue packet as a very long instruction n Specifies multiple concurrent operations n ⇒ Very Long Instruction Word (VLIW)
Chapter 4 — The Processor — 157
Scheduling Static Multiple Issue n Compiler must remove some/all hazards
n Reorder instructions into issue packets n No dependencies with a packet n Possibly some dependencies between
packets n Varies between ISAs; compiler must know!
n Pad with nop if necessary
Chapter 4 — The Processor — 158
MIPS with Static Dual Issue n Two-issue packets
n One ALU/branch instruction n One load/store instruction n 64-bit aligned
n ALU/branch, then load/store n Pad an unused instruction with nop
Address Instruction type Pipeline Stages
n ALU/branch IF ID EX MEM WB
n + 4 Load/store IF ID EX MEM WB
n + 8 ALU/branch IF ID EX MEM WB
n + 12 Load/store IF ID EX MEM WB
n + 16 ALU/branch IF ID EX MEM WB
n + 20 Load/store IF ID EX MEM WB
Chapter 4 — The Processor — 159
MIPS with Static Dual Issue
Chapter 4 — The Processor — 160
Hazards in the Dual-Issue MIPS n More instructions executing in parallel n EX data hazard
n Forwarding avoided stalls with single-issue n Now can’t use ALU result in load/store in same packet
n add $t0, $s0, $s1 load $s2, 0($t0)
n Split into two packets, effectively a stall
n Load-use hazard n Still one cycle use latency, but now two instructions
n More aggressive scheduling required
Chapter 4 — The Processor — 161
Scheduling Example n Schedule this for dual-issue MIPS
Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1,–4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0
ALU/branch Load/store cycle Loop: nop lw $t0, 0($s1) 1
addi $s1, $s1,–4 nop 2
addu $t0, $t0, $s2 nop 3
bne $s1, $zero, Loop sw $t0, 4($s1) 4
n IPC = 5/4 = 1.25 (c.f. peak IPC = 2)
Best schedule
Chapter 4 — The Processor — 162
Loop Unrolling n Replicate loop body to expose more
parallelism n Reduces loop-control overhead
n Use different registers per replication n Called “register renaming” n Avoid loop-carried “anti-dependencies”
n Store followed by a load of the same register n Aka “name dependence”
n Reuse of a register name
Chapter 4 — The Processor — 163
Loop Unrolling Example
n IPC = 14/8 = 1.75 n Closer to 2, but at cost of registers and code size
ALU/branch Load/store cycle Loop: addi $s1, $s1,–16 lw $t0, 0($s1) 1
nop lw $t1, 12($s1) 2
addu $t0, $t0, $s2 lw $t2, 8($s1) 3
addu $t1, $t1, $s2 lw $t3, 4($s1) 4
addu $t2, $t2, $s2 sw $t0, 16($s1) 5
addu $t3, $t4, $s2 sw $t1, 12($s1) 6
nop sw $t2, 8($s1) 7
bne $s1, $zero, Loop sw $t3, 4($s1) 8
Chapter 4 — The Processor — 164
Dynamic Multiple Issue n “Superscalar” processors n CPU decides whether to issue 0, 1, 2, …
each cycle n Avoiding structural and data hazards
n Avoids the need for compiler scheduling n Though it may still help n Code semantics ensured by the CPU
Chapter 4 — The Processor — 165
Dynamic Pipeline Scheduling n Allow the CPU to execute instructions out
of order to avoid stalls n But commit result to registers in order
n Example lw $t0, 20($s2) addu $t1, $t0, $t2 sub $s4, $s4, $t3 slti $t5, $s4, 20
n Can start sub while addu is waiting for lw
Chapter 4 — The Processor — 166
Dynamically Scheduled CPU
Results also sent to any waiting
reservation stations
Reorders buffer for register writes
Can supply operands for
issued instructions
Preserves dependencies
Hold pending operands
In-order commit
Chapter 4 — The Processor — 167
Register Renaming n Reservation stations and reorder buffer
effectively provide register renaming n On instruction issue to reservation station
n If operand is available in register file or reorder buffer
n Copied to reservation station n No longer required in the register; can be
overwritten n If operand is not yet available
n It will be provided to the reservation station by a function unit
n Register update may not be required
Chapter 4 — The Processor — 168
Speculation n Predict branch and continue issuing
n Don’t commit until branch outcome determined
n Load speculation n Avoid load and cache miss delay
n Predict the effective address n Predict loaded value n Load before completing outstanding stores n Bypass stored values to load unit
n Don’t commit load until speculation cleared
Chapter 4 — The Processor — 169
Why Do Dynamic Scheduling? n Why not just let the compiler schedule
code? n Not all stalls are predicable
n e.g., cache misses n Can’t always schedule around branches
n Branch outcome is dynamically determined n Different implementations of an ISA have
different latencies and hazards
Chapter 4 — The Processor — 170
Does Multiple Issue Work?
n Yes, but not as much as we’d like n Programs have real dependencies that limit ILP n Some dependencies are hard to eliminate
n e.g., pointer aliasing n Some parallelism is hard to expose
n Limited window size during instruction issue n Memory delays and limited bandwidth
n Hard to keep pipelines full n Speculation can help if done well
The BIG Picture
Chapter 4 — The Processor — 171
Power Efficiency n Complexity of dynamic scheduling and
speculations requires power n Multiple simpler cores may be better Microprocessor Year Clock Rate Pipeline
Stages Issue width
Out-of-order/ Speculation
Cores Power
i486 1989 25MHz 5 1 No 1 5W
Pentium 1993 66MHz 5 2 No 1 10W
Pentium Pro 1997 200MHz 10 3 Yes 1 29W
P4 Willamette 2001 2000MHz 22 3 Yes 1 75W
P4 Prescott 2004 3600MHz 31 3 Yes 1 103W
Core 2006 2930MHz 14 4 Yes 2 75W
UltraSparc III 2003 1950MHz 14 4 No 1 90W
UltraSparc T1 2005 1200MHz 6 1 No 8 70W
Cortex A8 and Intel i7 Processor ARM A8 Intel Core i7 920
Market Personal Mobile Device Server, cloud Thermal design power 2 Watts 130 Watts Clock rate 1 GHz 2.66 GHz Cores/Chip 1 4 Floating point? No Yes Multiple issue? Dynamic Dynamic Peak instructions/clock cycle 2 4 Pipeline stages 14 14 Pipeline schedule Static in-order Dynamic out-of-order
with speculation Branch prediction 2-level 2-level 1st level caches/core 32 KiB I, 32 KiB D 32 KiB I, 32 KiB D 2nd level caches/core 128-1024 KiB 256 KiB 3rd level caches (shared) - 2- 8 MB
Chapter 4 — The Processor — 172
§4.11 Real S
tuff: The AR
M C
ortex-A8 and Intel C
ore i7 Pipelines
ARM Cortex-A8 Pipeline
Chapter 4 — The Processor — 173
ARM Cortex-A8 Performance
Chapter 4 — The Processor — 174
Core i7 Pipeline
Chapter 4 — The Processor — 175
Core i7 Performance
Chapter 4 — The Processor — 176
SPEC2006 integer benchmark programs
Matrix Multiply n Unrolled C code 1 #include <x86intrin.h>
2 #define UNROLL (4)
3 4 void dgemm (int n, double* A, double* B, double* C)
5 {
6 for ( int i = 0; i < n; i+=UNROLL*4 )
7 for ( int j = 0; j < n; j++ ) {
8 __m256d c[4];
9 for ( int x = 0; x < UNROLL; x++ ) 10 c[x] = _mm256_load_pd(C+i+x*4+j*n);
11
12 for( int k = 0; k < n; k++ )
13 {
14 __m256d b = _mm256_broadcast_sd(B+k+j*n);
15 for (int x = 0; x < UNROLL; x++)
16 c[x] = _mm256_add_pd(c[x], 17 _mm256_mul_pd(_mm256_load_pd(A+n*k+x*4+i), b));
18 }
19
20 for ( int x = 0; x < UNROLL; x++ )
21 _mm256_store_pd(C+i+x*4+j*n, c[x]);
22 } 23 }
Chapter 4 — The Processor — 177
§4.12 Instruction-Level Parallelism
and Matrix M
ultiply
Matrix Multiply n Assembly code: 1 vmovapd (%r11),%ymm4 # Load 4 elements of C into %ymm4
2 mov %rbx,%rax # register %rax = %rbx
3 xor %ecx,%ecx # register %ecx = 0
4 vmovapd 0x20(%r11),%ymm3 # Load 4 elements of C into %ymm3
5 vmovapd 0x40(%r11),%ymm2 # Load 4 elements of C into %ymm2
6 vmovapd 0x60(%r11),%ymm1 # Load 4 elements of C into %ymm1
7 vbroadcastsd (%rcx,%r9,1),%ymm0 # Make 4 copies of B element
8 add $0x8,%rcx # register %rcx = %rcx + 8
9 vmulpd (%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements
10 vaddpd %ymm5,%ymm4,%ymm4 # Parallel add %ymm5, %ymm4
11 vmulpd 0x20(%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements
12 vaddpd %ymm5,%ymm3,%ymm3 # Parallel add %ymm5, %ymm3
13 vmulpd 0x40(%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements
14 vmulpd 0x60(%rax),%ymm0,%ymm0 # Parallel mul %ymm1,4 A elements
15 add %r8,%rax # register %rax = %rax + %r8
16 cmp %r10,%rcx # compare %r8 to %rax
17 vaddpd %ymm5,%ymm2,%ymm2 # Parallel add %ymm5, %ymm2
18 vaddpd %ymm0,%ymm1,%ymm1 # Parallel add %ymm0, %ymm1
19 jne 68 <dgemm+0x68> # jump if not %r8 != %rax
20 add $0x1,%esi # register % esi = % esi + 1
21 vmovapd %ymm4,(%r11) # Store %ymm4 into 4 C elements
22 vmovapd %ymm3,0x20(%r11) # Store %ymm3 into 4 C elements
23 vmovapd %ymm2,0x40(%r11) # Store %ymm2 into 4 C elements
24 vmovapd %ymm1,0x60(%r11) # Store %ymm1 into 4 C elements
Chapter 4 — The Processor — 178
§4.12 Instruction-Level Parallelism
and Matrix M
ultiply
Performance Impact
Chapter 4 — The Processor — 179
Chapter 4 — The Processor — 180
Fallacies n Pipelining is easy (!)
n The basic idea is easy n The devil is in the details
n e.g., detecting data hazards
n Pipelining is independent of technology n So why haven’t we always done pipelining? n More transistors make more advanced techniques
feasible n Pipeline-related ISA design needs to take account of
technology trends n e.g., predicted instructions
§4.14 Fallacies and Pitfalls
Chapter 4 — The Processor — 181
Pitfalls n Poor ISA design can make pipelining
harder n e.g., complex instruction sets (VAX, IA-32)
n Significant overhead to make pipelining work n IA-32 micro-op approach
n e.g., complex addressing modes n Register update side effects, memory indirection
n e.g., delayed branches n Advanced pipelines have long delay slots
Chapter 4 — The Processor — 182
Concluding Remarks n ISA influences design of datapath and control n Datapath and control influence design of ISA n Pipelining improves instruction throughput
using parallelism n More instructions completed per second n Latency for each instruction not reduced
n Hazards: structural, data, control n Multiple issue and dynamic scheduling (ILP)
n Dependencies limit achievable parallelism n Complexity leads to the power wall
§4.14 Concluding R
emarks