Texas A&M University 1...Texas A&M University 24 LNA Design Target Robust input matching 50 Ohm...

Texas A&M University 1

BLUETOOTH RECEIVER DESIGN

AND WIRELESS LAN RECEIVER

Bluetooth Receiver Design and Wireless LAN Receiver Considerations

Edgar Sánchez-SinencioTI J. Kilby Chair Professor

Department of Electrical EngineeringAnalog and Mixed-Signal CenterTexas A&M Universityhttp://amsc.tamu.edu/ A M S C


OutlineIntroduction to the Wireless TechnologySystem Level DesignBuilding Blocks Design HighlightsBuilding Blocks Design Details

LNAMixerFrequency Synthesizer & VCOActive Complex FilterLimiter & GFSK DemodulatorDC Offset Tracking and Canceling

Bluetooth – Wireless LAN Receiver


Introduction to the Wireless TechnologySystem Level DesignBuilding Blocks Design HighlightsBuilding Blocks Design Detail

LNAMixerFrequency Synthesizer & VCOActive Complex FilterLimiter & GFSK DemodulatorDC Offset Tracking and Canceling

Bluetooth – Wireless LAN Receiver


Applications of Wireless Technology

VoiceInternetMeasurementInventoryTelemetryHealth Care AutomotiveData SharingRemote Instrumentation

Remote PrintingMilitaryBio ImplantWireless PenCommerceUniversal Remote ControlGames and MusicOthers to come . . .


WPAN : BluetoothBluetooth wireless technology is a worldwide specification for a small-form factor, low-cost radio solution that provides links between mobile computers, mobile phones, other portable handheld devices, and connectivity to the Internet.


What can one do with a Bluetooth enabled product?

Eliminating the need for wired connections between electronic products and accessories Exchanging files, business cards, calendar appointments, etc. with groups of Bluetooth users Transferring and synchronizing files between devices Connecting to localized content services in public areas Functioning as remote controls, keys, tickets and e-cash wallets


Overview of Bluetooth

2.4GHz - 2.48 GHz ISM band.GFSK modulation: index = 0.28 - 0.35.1 Mb/s data rate and 1 MHz channel spacing.The market size for Bluetooth chip to be $1.2 billion by 2005 (Merrill Lynch)The Bluetooth special interest group has signed up 2491 member companies


Forecast for Bluetooth

Source: Micrologic Research


The Design of a Bluetooth Receiver

This project involved 6 Ph. D. students and one faculty member, the duration was 12 months from the conceptual idea to the testing of the designed CMOS integrated circuit in 0.35 um. This work generated 3 journal papers and 4 conference papers, and received the best student paper award in the IEEE RF-IC Conference in 2002.

It was the first time a project of this nature was carried out in a university environment.

System Level Design


Receiver Architecture Selection

The choice of architecture depends on:Radio frequencyModulation schemeRequired Signal-to-Noise ratio (SNR) and interference ratioProcess technologyApplication


Monolithic Receiver Architectures

Direct-Conversion ReceiverDC offset and flicker noise problem: 99% of signal power is within DC to 430kHz.A fast settling AGC may be required for GFSK demodulation.

LNA

AGC ADC

AGC ADC

90

PLL

Low-IF ReceiverGreatly alleviated DC offset and Flicker noise problem.Relaxed image rejection requirement (~33 dB).

LNA 90

PLL

AGC ADC


Potential Receiver Architectures (1) Direct Conversion Receiver

LNA 90 DSP

VCO

ADC

ADC

AGC

AGC

/N

High level integration.No image rejection required.Less components, possible low power consumptionDC offset.Flicker Noise.


Potential Receiver Architectures (2) Low IF Receiver Architecture

LNA 90 Polyphase

Filter

DSPADCAGC

VCO

/N

High level integration and possible low power design.Flicker noise less significant in signal band.DC offset can be easily removed.Image rejection.Folded-back interference.


Which architecture to choose?

Low IF is favored in Bluetooth specifications

Image interference exception alleviates the image rejection requirement

Flicker noise is hard to avoid in CMOS implementation

Alternative technology (e.g. SiGe) may perform better with direct conversion architecture

Low IF is the way to go for CMOSBluetooth receiver!


Problems to Solve in Low IF Receiver

Choice of IFTrade-off between having relatively high or low IF should be taken into consideration

Image rejection+9dB image signal need to be suppressed

Folded-in interference rejectionIt could be worse interferer than image signal


Problems to Solve in Low IF Receiver :Trade-off of IF

Lower IFrelaxed image rejection requirementlower folded back interference levellower Q requirement of the filterlower power consumption of baseband blocks

Higher IFimproved FM demodulator performanceeasily removed DC offset and less flicker noise

2 MHz IF is chosen for a good compromise.


Image Rejection :Active Complex Filter

Not like the traditional nonlinear lowpass to bandpass frequency transformation, linear frequency transformation,

H(jw) ---> H(j(w-w0)obtain a complex bandpass filter.

IRR > 60 dB

w0

H(jw)

5th Order Chebyshev Polyphase Filter


Folded-in Interference

LO

IF IF

SignalImage

IFFolded backInterference

RF LO finf

IF f1

IF f1

5 MHz

1 MHz

Assuming IF is 2 MHz, a strong interference 5 MHz away from desired signal at RF is folded in to 1 MHz away at IF. The interference can be 40 dB higher than the signal. Channel select filter stopband attenuation requirement can be stringent.


Receiver Noise Figure and IIP3Receiver sensitivity -85 dBmRequired SNR at baseband 15 dBNoise Bandwidth 1.35 MHzRF filter insertion loss 2.5 dB

Receiver Noise Figure 10.2 dBReceiver IIP3 -14 dBmPower Consumption <50 mA (3V

supply)


Complete Receiver Diagram

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator

DC OffsetCancellation

Mixers

Limiter& RSSI

Digital BitStreams2.45GHz

2.45GHz

2 MHz 2 MHz

Note that no ADC, nor AGC are involved

Building Blocks DesignLow Noise Amplifier

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


LNA Design TargetRobust input matching

50 Ohm input impedance to provide the termination for preceding external compents

High gainSince LNA is the first block of the entire receiver, high gain of the LNA helps to reduce overall noise figure

Low noiseNoise figure of LNA sets lower bound of the system noise figure

Sufficient linearity, low power consumption


Inductive Source Degeneration Type LNA

Input impedance is proportional to LsCascode (M1-M2) structure for high gainM1, M2 must be optimized for lowest noise

M1

M2

Ls0.3nH

Lg

Vb

Ld2.6nH

134/0.4

134/0.4


On Chip Spiral InductorOn chip spiral inductor is utilized for source degeneration (Ls) and inductive load (Ld)Software ASITIC is used to characterize the on chip spiral inductor.


Simulation ResultsGain and Noise

Noise figure: 2.6 dBVoltage gain: 18.2 dB

Building Blocks DesignMixer

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


Mixer Design Consideration

Different types of mixers are availablePassive mixer – lower power consumptionActive mixer – conversion gain reduces the requirement of LNA

Low noise design is still important since mixer is one of the front end blockLinearity requirement is higher than that of LNA


Schematic of the mixer

Double balanced Gilbert Cell mixerCurrent injection to alleviate the trade off between the linearity and power supply voltageRF+ RF-

LO-

LO+LO+

Building Blocks DesignFrequency Synthesizer

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


Frequency Synthesizer Design Target

Must be able to cover the entire bandMinimize power consumption

Make it as simple as possible – integer-N typeSettling time is relaxed in Bluetooth specification

No need for more complex fractional-N type PLLThe design of prescaler can be challenging since it has to work at carrier frequency


The Synthesizer StructureAn integer N architecture is preferred for the synthesizer to minimize power consumptionCurrent steering logic prescalerSettling time 120µsPhase noise 130dBc@3MHz

PFD CP LPF1MHz 2.402~2.480GHz

15/16ProgrammableDivider

Prescaler

N = 2450


Prescaler Design

Vdd

A

CLK CLK

Vb

Vbias

R R

Q

Q

CLK CLK

R

B

R

Amplifier Latch

Nor Gate

Q

QSET

CLR

D

Q

QSET

CLR

D

MC

Vout

CLK

Divide by 3/4 (High frequency block of prescaler)

Current steering dividers are used in the prescaler to reduce power consumption


Synthesizer Simulations

Settling time: 120 µs (to a frequency step)Complete PLL transistor level simulationSimulation time: 20 hrs.

Building Blocks DesignVoltage Controlled Oscillator

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


VCO Design TargetMust be able to cover the entire band and some more to compensate process variationQuadrature (I/Q) output is required for modulationTuning sensitivity must be high enough to cover the range but low enough to reduce noise due to control signalPhase noise requirement came from third and higher interference specifications


2nd-orderPolyphaseNetwork

I+I-Q+Q-VC

VO+

VO-

IB = 4mA

140/0.4

60/0.4

140/0.4

400/0.4

2nH (Q=4.8)

Tune

−I

+I

+Q

−Q

+IV

−IV

VCO Schematics


Discrete Tunable Bank VaractorVaractor

VcD0D1

The varactor has 2bit discrete tuningThey can provide 4 steps of coarse tuning rangeCoarse tuning is mainly for compensating process variation

Building Blocks DesignComplex Filter

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


How Does Complex Filter work?

LO

IF IF

SignalImage

IFFolded backInterference

Bandpass filter for signal side, attenuator for image side


How to implement complex filters?Design a LPF prototype by frequency shifting the desired BPF response to DC

Frequency translation (s→s-jωc), by replacing each integrator by its complex equivalent

0 fc

LPFprototype

DesiredBPF

Σ

Σ

Ii

Qi

Io

Qo

xi xoxi xo

sOω

sOω

O

IF

ωω−

O

IF

ωωs

OωIF

O

js ωω−


How to implement complex filters?For OTA-C filters,

two cross coupled OTA’s are used

Butterworth approximationis preferred because:

good group delayresponseall poles have the same magnitude

Equal C designEqual cross coupled OTA’sGood matching

V

I

C

C

Q

C

CIFω−CIFω


Complex Filter Design TargetImage rejection depends on matching between I and Q branches (30dB image rejections requires 5% gain error and 3o phase error).The LPF prototype is a 6th order Butterworth filter. The Corresponding BPF is 12th order.Due to the tough noise requirements, a very simple OTA is used.A simple input gain stage (15dB) is used to minimize the input referred noiseLarge channel lengths (6µm) are used to minimize flicker noise, improve matching, improve linearity, and avoid using cascode transistors.


Complex Filter Overall Block Diagram

BiQuad 1Q = 0.52

BiQuad 2Q = 0.71

BiQuad 3Q = 1.93

I

Q

I

Q15dB

FrequencyComparison

RelaxationOscillatorfref

6th order Butterworth approximationBiquadratic OTA-C filterAutomatic frequency tuning by relaxation oscillator


Single BiQuad Stage

gm gm

OTA1

gm gm

βgm

CM

D2

CMD1

OTA2

OTA3 OTA4

1Q

βgm

OTA5 OTA6

From QChannel

From QChannel

1 2

To Q Channel

To Q Channel

Ii

Io

VCM

Complex BiQuad

LP biquadprototype

1 2

LP biquadprototype

gmβ1

1 2

gmβ1gmβ

1 gmβ1

iiI ioI

iiQ ioQ


OTA architecture

gm is controlled by the common mode voltage.The CM voltage is stabilized using VCM

VCM is controlled by the common mode detector at the input (CMFF) or the output (CMFB) of the OTA.

VDD

M1M2

M3M4

VCM

VI+ VI-

IO- IO+


Tuning Circuit

Only frequency tuning is required since the maximum Q in the filter is 2, which is low enoughThe tuning circuit is run at 1MHz to minimize coupling to the complex filter

FrequencyComparison

RelaxationOscillatorfref

RelaxationOscillator Comparator

=Counter

D/ATo complexfilter

Vc

Systemreset

Dref

Overflow

Equal to 64

OscillatorCounter

ClkR

ReferenceCounter

ClkR

fref

OF

Clk

><

Up/Dn

Freeze


Complex Filter MeasurementImage Rejection Ratio 45dBSignal side attenuation –27dBc @ 1MHz–58dBc @ 2MHzImage side attenuation-79dBc @ 1MHz-95dBc @ 2MHz

Building Blocks DesignGFSK Demodulator

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


Motivation to Build a Mixed-Mode Demodulator

AGC difficult to handle in frequency hopping system.Short preample (4 symbols) requires extremely fast settling of AGC.Constant envelope GFSK modulation allow use of simple limiting receivers and non-coherent detection.By replacing AGC and ADC with a demodulator, power consumption can be lowered


GFSK (Gaussian Frequency Shift Keying)

Gaussian Filter

FrequencyModulator

DigitalData Filtered

Data

Modulated Data(Before limiter)

The information is modulated by changing the frequency of the carrier.The digital information is passed through a Gaussian filter and then frequency modulated


Digital Demodulator

The information is contained in zero crossing point.Using rail-to-rail square wave eliminates the amplitude effect.The tunable one-shot at the output stage guarantee proper pulse widthSub-optimal detection


Mixed-Mode DemodulatorWe turn to digital solution: The information is contained in the pulse density per bit period.

Zero crossingDetector

I+I-

Q+Q-

ShapeKeeping

Zero crossingDetector

Demodulator Output


Digital DemodulatorZero crossing point detection one-shot

Shape keeping one-shot

Homogenizes pulse widths

VDD

VI

+-

+-

VO

VDD

R1

R2

R3

R4C1

C2

VDD

R5

Detects zero-crossings and generates a pulse per each zero-crossing

VDD

YX R

C

Building Blocks DesignBaseband

LNA 90o

PLL

RFFilter

LowNoise

Amplifier

RSSISynthesizer

and VCO

ComplexFilter

GFSKDemodulator


Mixers

Limiter& RSSI

Digital BitStreams


Functions of the baseband signal processing circuit

Bit decision, obtain the bit stream based on the output of the demodulator.Track and compensate the DC offset caused by the LO frequency offset between receiver and transmitter and frequency driftingGenerate the clock and control signal applied in the baseband signal processing circuit.

System Testing


Die Photograph and PCBTSMC digital 0.35um process6.25mm2

2.5mm


Experimental ResultsSensitivity and BER Testing

-82dBm sensitivity for 0.1% BER


Experimental ResultsNoise

15dB Noise Figure


Experimental ResultsLinearity (IIP3)

-10dBm IIP3

Chameleon Project:Bluetooth - Wireless LAN Receiver


Project Objectives

Design a receiver compliant with the Bluetooth and IEEE 802.11b standards

Minimize component number by sharing as much blocks as allowed by the standards

Minimize area and power consumption in the multistandard receiver


Standard Comparison: Radio

Bluetooth Wi-Fi

RF Frequency 2.4GHz 2.4GHz

Sensitivity -70dBm -80dBm

Maximum Signal -20dBm -4dBm

Modulation GFSK CCK

Data rate 1Mb/s 1, 2, 5.5, 11Mb/s

Channel Bandwidth 1MHz 22MHz


MOBILEPANWi-Fi

Cellular

2.5GGSM, TDMA,

CDMA

3GWCDMA

Global

notebook, cell phone, palm

device, pager, car

Mobile

Up to 144k NowUp to 2 Mbps?

2.5G / 3G

RF 2.4 MHz

Released EOY 2002.

50 to 300 feet

notebook, desktop, palm

WLAN(Wireless LAN)

Up to 20 Mbps

802.11g

RF 5 MHz

Up to 512 users.Will have adapter

for 802.11b.

50 to 300 feet


WLAN(Wireless LAN)

Up to 54 Mbps

802.11a

RF 2.4 MHzRF 2.4 MHz

Up to __ users.Will be compatible

with 802.11g

Frequency

Other

32 feet50 to 300 feetRange

notebook, cell phone, palm

device, pager, appliance, car


Types of terminals

PAN(Personal Area

Network)

WLAN(Wireless LAN)

Use

Up to 721 KbpsUp to 11 MbpsSpeed

Bluetooth802.11bType


System Design Issues in the MultistandardReceiver

Receiver architectureDirect Conversion for both standards

What can be shared?RF FrontVGA (partially shared)Frequency SynthesizerProgrammable bandwidth baseband FilterProgrammable sampling rate and resolution ADC (pipeline)

Design for the most stringent specification


System Architecture

VGA

X

X

LPF

LPF

ADC

ADC

Measuresignallevel

Gaincontrol

90o

PFD

%N

CPLPFfref


Conclusions

Monolithic 3V Bluetooth receiver is realized using 0.35um digital processDeveloped independently in a university environmentFeature active complex filter and mixed-mode GFSK demodulator–82dBm sensitivity and –10dBm IIP365mA current consumption from 3V supply45mA expected with inductor with Q=5


The Team who developed and proposed the BT Implementation.

Analog and Mixed-Signal Center, TAMU Department of Electrical Engineering

Texas A&M University 1...Texas A&M University 24 LNA Design Target Robust input matching 50 Ohm...

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