TC1766 da v12 - Infineon

Documentat ion Addendum, V1.2, Apr. 2007

Microcontrol lers

TC176632-Bit Single-Chip Microcontrol ler

Edition 2007-04Published by Infineon Technologies AG 81726 München, Germany© Infineon Technologies AG 2007. All Rights Reserved.

Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.

InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

http://www.infineon.com

Documentat ion Addendum, V1.2, Apr. 2007

Microcontrol lers

TC176632-Bit Single-Chip Microcontrol ler

TrademarksTriCore® is a trademark of Infineon Technologies AG.

TC1766 Documentation Addendum

Revision History: V1.2 2007-04Previous Version: V1.1Page Subjects (major changes since last revision) 7 Figure 1-12 is updated. 8 The register long names for MMU_CON and D11 to D15 are corrected. 10 The desription for CRC generation and error checking is improved; the typo

is corrected for EICR0.REN0, EICR0.REN1, EICR1.REN2 and EICR1.REN3

11 The typo of bit description GEEN1 is corrected. 19 The bit name and access type is corrected for bit 5 of PCP_ES register; the

instruction field definition of Table 10-12 is updated. 20 Figure 10-14 is updated; the typo in the syntax description of the ST.PI

instruction of the PCP is corrected 21 The typo in Figure 11-5 is corrected. 22 The description for Channel Reset Operation is improved. 23 The typo in Transaction Lost Interrupt section is corrected. 24 The typo in Move Engine Interrupt section is corrected. 28 The read and write access modes for address location F000 0804H of

Table 16-7 are corrected; the reserved column for address location F000 0850H to F000 08F4H of Table 16-7 are split.

30 Typo in Slave Select Output Control and the description for Slave Select Register Update section are corrected.

32 A new note is added for SSOC and SSOTC registers; a new footnote is added to SSOTC.LEAD, SSOTC.TRAIL and SSOTC.INACT bit description.

33 A new paragraph is added to Receive FIFO section; the description when LEC=111B is improved; the CAN Bus State Information is updated in Table 20-8.

34, 35, 36 The typo for number of CAN interrupt outputs is corrected. 36 MLI receive clock max. frequency is corrected. 52 The formula for the timer period is corrected.

We Listen to Your CommentsAny information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:[email protected]

mailto:[email protected]

TC1766

Table of Contents

Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 User’s Manual - System Units Part (Volume 1) . . . . . . . . . . . . . . . . . . . . 6Page 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Page 1-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Page 1-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Page 1-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Page 1-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 1-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 2-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 2-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 2-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Page 2-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Page 3-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Page 4-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Page 4-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Page 5-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Page 5-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Page 5-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Page 5-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Page 5-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Page 5-58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Page 5-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page 6-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page 6-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Page 6-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Page 7-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Page 7-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Page 7-49 to 7-51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Page 8-5 to 8-7 and 8-13 to 8-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Page 8-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Page 9-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Page 9-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Page 9-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Page 9-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Page 9-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Documentation Addendum 1 V1.2, 2007-04

TC1766

Table of Contents

Page 9-49 to 9-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Page 9-55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Page 9-57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Page 10-58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Page 10-59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Page 10-73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Page 10-77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Page 10-98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Page 11-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Page 11-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Page 11-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Page 11-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Page 11-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Page 11-80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Page 11-91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Page 12-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Page 14-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Page 16-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Page 16-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Page 16-20 to 16-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Page 16-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Page 16-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28


TC1766

Table of Contents

3 User’s Manual - Peripheral Units Part (Volume 2) . . . . . . . . . . . . . . . . 29Page 17-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Page 18-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Page 18-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Page 18-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Page 18-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Page 18-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 18-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Page 19-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 19-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Page 20-109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Page 20-116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Page 20-117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Page 20-118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Page 21-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Page 21-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Page 21-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Page 21-108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Page 21-116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Page 21-117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Page 22-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Page 22-76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Page 22-89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Page 22-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Page 22-91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Page 22-94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Page 22-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Page 22-97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45


TC1766

Table of Contents

Page 22-99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Page 22-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Page 22-101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Page 22-103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Page 22-104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Page 22-105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Page 22-106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Pages 22-173 and 22-174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Page 22-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Page 22-205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Page 22-209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Page 23-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Page 23-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Page 23-97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Page 24-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Page 24-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Page 24-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52


TC1766

Introduction

1 IntroductionThis document describes corrections, changes, and improvements for the two parts ofthe TC1766 User’s Manual V1.1 2005-08, the System Units book (Volume 1) and thePeripheral Units book (Volume 2). These corrections will be considered with the nextupdate of these User’s Manual documents.The referenced documents to this addendum are located at the Internet page:• www.infineon.com/tc1766• TC1766 System Units User’s Manual (Vol.1), V1.1, Aug. 2005• TC1766 Peripheral Units User’s Manual (Vol.2), V1.1, Aug. 2005


http://www.infineon.com/tc1796

TC1766

User’s Manual - System Units Part (Volume 1)

2 User’s Manual - System Units Part (Volume 1)This section describes corrections for the System Units part of the User‘s Manual.

Page 1-10The second bulleted point under Interrupt System must be corrected to “Flexibleinterrupt-prioritizing scheme with 255 interrupt priority levels.”

Page 1-11The bulleted point under Package must be corrected to “PG-LQFP-176-2 package, 0.5mm pitch.”


TC1766


Page 1-33Figure 1-12 should be replaced with the below figure:

Figure 1-12 TC1766 Pinning for PG-LQFP-176-2 Package

Page 1-44The pad driver class of pin HDRST is “A2” instead of “A1”. The pad driver class of pinNMI and PORST are grouped as “A2”.

1234567891011121314151617181920212223242526272829

394041424344

54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

303132333435363738

45 46 47 48 49 50 51 52 53

979695949392919089

1009998

10110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213

313

413

513

613

713

813

914

014

114

214

314

414

514

614

714

814

915

015

115

215

315

415

515

615

715

815

916

016

116

216

316

416

516

616

716

816

917

017

117

217

317

417

517

6

P0.0

/IN0/

SW

CFG

0/O

UT0

/OU

T56

P0.1

/IN1/

SW

CFG

1/O

UT1

/OU

T57

P0.2

/IN2/

SW

CFG

2/O

UT2

/OU

T58

P0.3

/IN3/

SW

CFG

3/O

UT3

/OU

T59

P0.4

/IN4/

SW

CFG

4/O

UT4

/OU

T60

P0.5

/IN5/

SW

CFG

5/O

UT5

/OU

T61

P0.6

/IN6/

SW

CFG

6/R

EQ2/

OU

T6/O

UT6

2P0

.7/IN

7/S

WC

FG7/

REQ

3/O

UT7

/OU

T63

P0.8

/IN8/

SW

CFG

8/O

UT8

/OU

T64

P0.9

/IN9/

SW

CFG

9/O

UT9

/OU

T65

P0.1

0/IN

10/S

WC

FG10

/OU

T10/

OU

T66

P0.1

1/IN

11/S

WC

FG11

/OU

T11/

OU

T67

P0.1

2/IN

12/S

WC

FG12

/OU

T12/

OU

T68

P0.1

3/IN

13/S

WC

FG13

/OU

T13/

OU

T69

P0.1

4/IN

14/S

WC

FG14

/REQ

4/O

UT1

4/O

UT7

0P0

.15/

IN15

/SW

CFG

15/R

EQ5/

OU

T15/

OU

T71

P1.0/IN16/OUT16/OUT72P1.1/IN17/OUT17/OUT73P1.2/IN18/OUT18/OUT74

P1.3/IN19/OUT19/OUT75

P1.4/IN20/EMG_IN/OUT20/OUT76P1.5/IN21/OUT21/OUT77P1.6/IN22/OUT22/OUT78P1.7/IN23/OUT23/OUT79

P1.8/IN24/IN48/MTSR1B/OUT24/OUT48P1.9/IN25/IN49/MRST1B/OUT25/OUT49P1.10/IN26/IN50/OUT26/OUT50/SLSO17P1.11/IN27/IN51/SCLK1B/OUT27/OUT51

AD0E

MU

X0/

P1.

12AD

0EM

UX

1/P

1.13

AD0E

MU

X2/

P1.

14

TCLK

0A/O

UT3

2/IN

32/P

2.0

SLS

O13

/SLS

O03

/OU

T33/

TREA

DY0

A/IN

33/P

2.1

TVAL

ID0A

/OU

T34/

IN34

/P2.

2TD

ATA

0A/O

UT3

5/IN

35/P

2.3

OU

T36/

RC

LK0A

/IN36

/P2.

4R

REA

DY

0A/O

UT3

7/IN

37/P

2.5

OU

T38/

RVA

LID

0A/IN

38/P

2.6

OU

T39/

RD

ATA

0A/IN

39/P

2.7

P2.8

/SLS

O04

/SLS

O14

/EN

00

P2.9

/SLS

O05

/SLS

O15

/EN

01P2

.10/

MR

ST1

AP2

.11/

SCLK

1A/F

CLP

0BP2

.12/

MTS

R1A

/SO

P0B

P2.1

3/SL

SI1

/SD

I0

P3.0

/RXD

0AP3

.1/T

XD

0A

P3.2/SCLK0P3.3/MRST0

P3.4/MTSR0

P3.5/SLSO00/SLSO10/SLSO00&SLSO10P3.6/SLSO01/SLSO11/SLSO01&SLSO11

P3.7/SLSI0/SLSO02/SLSO12

P3.8/SLSO06/TXD1A

P3.9

/RXD

1AP3

.10/

REQ

0

P3.1

1/R

EQ1

P3.1

2/R

XDC

AN0/

RXD

0BP3

.13/

TXD

CA

N0/

TXD

0B

P3.1

4/R

XDC

AN1/

RXD

1BP3

.15/

TXD

CA

N1/

TXD

1B

OU

T52/

OU

T28/

HW

CFG

0/IN

52/IN

28/P

4.0

OU

T53/

OU

T29/

HW

CFG

1/IN

53/IN

29/P

4.1

OU

T54/

OU

T30/

HW

CFG

2/IN

54/IN

30/P

4.2

P4.3/IN31/IN55/OUT31/OUT55/SYSCLK

OCDSDBG0/OUT40/IN40/P5.0OCDSDBG1/OUT41/IN41/P5.1OCDSDBG2/OUT42/IN42/P5.2

OCDSDBG4/OUT44/IN44/P5.4OCDSDBG3/OUT43/IN43/P5.3

OCDSDBG5/OUT45/IN45/P5.5OCDSDBG6/OUT46/IN46/P5.6OCDSDBG7/OUT47/IN47/P5.7

OCDSDBG8/TDATA1/RDATA0B/P5.8OCDSDBG9/TVALID1/RVALID0B/P5.9

OCDSDBG10/RREADY0B/TREADY1/P5.10OCDSDBG11/TCLK1/RCLK0B/P5.11

OCDSDBG12/TDATA0B/RDATA1/P5.12OCDSDBG13/TVALID0B/RVALID1/P5.13

OCDSDBG14/RREADY1/TREADY0B/P5.14OCDSDBG15/TCLK0B/RCLK1/P5.15

FCLP

0AFC

LN0

SOP

0ASO

N0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN8

AN7

AN9

AN

10A

N11

AN

12A

N13

AN

14A

N15

AN

16A

N17

AN

18A

N19

AN20AN21AN22AN23AN24AN25AN26AN27

AN28AN29AN30AN31AN32AN33AN34AN35

TRSTTCK

TDI

TDOTMS

BRKINBRKOUT

NMI

HDRSTPORST

BYPASSTESTMODE

XTAL1XTAL2

VDD

VDDP

VSS

N.C.

N.C.

TRCLK

TC1766

VDDVDDPVSS

VDDMFVSSMF

VDDAF

VSSAF

VFAREFVFAGND

VD

DM

VSS

M

VAR

EF0

V AG

ND

0

VD

DV D

DP

VSS

VD

D

V DD

P

VSS

VSS

VDD

VDDP

VSS

VDDOSC

VDDOSC3

VSSOSC

V DD

FL3

V DD

P

V SS

V DD

V DD

P

V SS

V DD

V DD

P

V SS

MCP06067_c


TC1766


Page 1-46The footnotes 2 and 4 of Table 1-3 should be deleted.

Page 1-47The following section has to be added after section 1.4.2:

Page 2-13The long register name of register MMU_CON must be changed to “MMUConfiguration Register”.

Page 2-15The bit description of bit CPU_SRCn.TOS is wrong. For TOS = 1, the description mustbe changed from “Reserved” to “Service Provider = PCP”.

Page 2-17In Table 2-4, the register long name for D11, D12, D13, D14 and D15 must be changedto “Data Register 11, Data Register 12, Data Register 13, Data Register 14 and DataRegister 15.

Page 2-23The offset address for register CMP1 must be corrected in Table 2-6 from 2200H into2280H.

1.4.3 Pull-Up/Pull-Down Behavior of the Pins

Table 1-5 List of Pull-up/Pull-down Reset Behavior of the PinsPins PORST = 0 PORST = 1All GPIOs, TDI, TMS, TDO Pull-upHDRST Drive-low Pull-upBYPASS Pull-up High-impedanceTRST, TCK High-impedance Pull-downTRCLK High-impedanceBRKIN, BRKOUT, TESTMODE Pull-upNMI, PORST Pull-down


TC1766



Figure 2-11 PMI Block Diagram

Page 3-18Section 3.2.2.5: Point 3) of the actions should be executed after point 5) and not afterpoint 2).

Page 4-25The first sentence of Section 4.4.3 must be replaced by “Except for different connectionsto serial port lines of ASC0, the bootstrap loader mode 3 is identical to bootstrap loadermode 1.”

MCB06078_c

To/FromLocal Memory Bus

128

Data Switch&

Data Alignment&

Interface Control

PMIControl

Registers

LMB InterfaceSlave Master

CP

UIn

terfa

ce To/FromCPU

Program MemoryInterface (PMI)

PMEM

TagRAM

8 KBICACHE

16 KBSPRAM

PMEM = Program Memory in PMIICACHE = Instruction CacheSPRAM = Scratch-Pad RAMLMB = Local Memory BusCPS = CPU Slave

128

64

64

ParityControl/Check

To SCU(PMI Memory Parity Errors)


TC1766


Page 4-26The first sentence of the note at the top of the page must be extended by “For CRCgeneration and error checking, the BootROM software uses the TC1766 on-chipmemory checker module with an initial value of FFFF FFFFH for the memory checkerresult register before the checksum is generated.”

Page 5-18The bit description of case “1” for EICR0.REN0 must be replaced by “ The detection ofa rising edge of IN0 generates a trigger event (INTF0 becomes set).”





TC1766


Page 5-28The first sentence of the bit description of GEEN1 must be replaced by “Bit GEEN1enables the generation of a trigger event for output channel 1 when the result of thepattern detection changes.”

Page 5-48Figure 5-11 should be replaced with the figure shown as below.The below note must beadded to the end of the last sentence of the page.

Figure 5-11 DMA Request Selection Logic

Note: By default, TIR line is selected for both ASC and SSC modules. For RIR line to beselected, SEL0.DMARS to SEL3.DMARS should be set accordingly. See DMARSregister.

Page 5-58The bit description of ENON on the bottom of the page must be corrected to:“1 Setting of EMSF by hardware is enabled.”

MCA06453

ASC0MUX

SEL0

ASC1MUX

SSC0MUX

SSC1MUX

0

1

SEL1

SEL2

SEL3

SEL0 to SEL3 are bit fields of theDMA Request Select Register

TIR

RIR

TIR

RIR

TIR

RIR

TIR

RIR

SCU

To DMA Controller

To DMA Controller

To DMA Controller

To DMA Controller

0

1

0

1

0

1

ASC0_REQ

ASC1_REQ

SSC0_REQ

SSC1_REQ


TC1766


Page 5-64The sentence “This bit is set with any reset.” in the description of bit PARAV must bechanged into “This bit is set after a power-on reset“.


Figure 6-2 Basic LMB Transactions

Page 6-6In the second paragraph of Section 6.2.3, second bulleted point, the register short namefor LMB Error Data Registers should be replaced with “LEDATL/LEDATH”.

Page 6-7In the bit description of bit LEC, the text “When writing a 0 to LEC” must be replaced by“When writing a 1 to LEC”.

Page 6-19The second sentence of the first paragraph of Section 6.4.3 should be replaced with:“The requesting FPI Bus master releases the FPI Bus for one cycle after the FPI Bustransaction request, in order to allow the FPI Bus slave to indicate if it is ready to handlethe requested FPI Bus transaction.”

Request/Grant

DataCycle

AddressCycle

Bus Cycle 1 2 3 4

Request/Grant

AddressCycle

DataCycle

DataCycle

AddressCycleRequest/Grant

5

MCA06109_c

Transfer 1

Transfer 2

Transfer 3


TC1766



Figure 6-7 Basic FPI Bus Transactions


Figure 6-12 BCU Breakpoint Trigger Combination Logic

Page 7-16In Table 7-7, 32-bit Load Page Buffer Command, the DFLASH address for DB1 AFE155F4H must be replaced with AFE1 55F0H in Cycle 1 and DFLASH address for DB0AFE0 55F0H must be replaced with AFE0 55F4H in Cycle 2.

Request/Grant

DataCycle

AddressCycle

Bus Cycle 1 2 3 4

Request/Grant

AddressCycle

DataCycle

DataCycle

AddressCycleRequest/Grant

5

MCA06109_c

Transfer 1

Transfer 2

Transfer 3

MCA06117_c

Address 1 Trigger

Signal Status Trigger

CONCOM2 CONCOM1 CONCOM0

AND/ORSelection

Address 2 Trigger

Grant Trigger

AND/ORSelection

AND/ORSelection

AddressTrigger

SBCU_DBCNTL

BCUBreakpointTrigger


TC1766


Page 7-41The first paragraph of column “Description” for bit FABUSY should be changed asfollows:“This status flag is a flag for test purposes that should not be used by software drivers.It indicates whether any of the Flash arrays is in busy state. FABUSY is cleared by anyreset operation.”

Page 7-49 to 7-51The following footnote 1) must be added to the following FCON bits and bit fields:WSPFLASH, WSECPF, WSWLHIT, WSDFLASH, and WSECDF1) These bits and bit fields can be changed at any time, also with code fetched from Program Flash. A modified

wait state parameter will be taken into account with the next corresponding access.

Page 8-5 to 8-7 and 8-13 to 8-14The respective address ranges (in bold) for Segment 8 and 10 of Table 8-2 and Table 8-4 must be updated as the following :

Table 8-2 SPB Address Map of Segment 0 to 14Seg-ment

Address Range

Size Description Access TypeRead Write

8 8FE1 4000H - 8FE1 FFFFH

48 Kbyte Reserved LMBBE & SPBBE

LMBBE

8FE2 0000H - 8FF1 FFFFH

1 Mbyte Reserved LMBBE & SPBBE

LMBBE

8FF2 0000H - 8FF5 FFFFH

256 Kbyte

Reserved for TC1766 emulation device memory

8FF6 0000H - 8FFF BFFFH

624 Kbyte

Reserved

8FFF C000H - 8FFF FFFFH

16 Kbyte Boot ROM (BROM) access


TC1766


10 AFE1 4000H - AFE1 FFFFH

48 Kbyte Reserved LMBBE & SPBBE

ignore

AFE2 0000H - AFF1 FFFFH

1 Mbyte Reserved LMBBE & SPBBE

ignore

AFF2 0000H - AFF5 FFFFH

256 Kbyte

Reserved for TC1766 emulation device memory

AFF6 0000H - AFFF BFFFH

624 Kbyte

Reserved

AFFF C000H - AFFF FFFFH


Table 8-4 LMB Address MapSeg-ment

Address Range

Size Description ActionRead Write

81) 8FE1 4000H - 8FE1 FFFFH

48 Kbyte Reserved LMBBET LMBBET

8FE2 0000H - 8FF1 FFFFH

1 Mbyte Reserved LMBBET LMBBET

8FF2 0000H - 8FF5 FFFFH

256 Kbyte Reserved for TC1766 emulation device memory

8FF6 0000H - 8FFF BFFFH

624 Kbyte Reserved

8FFF C000H - 8FFF FFFFH


Table 8-2 SPB Address Map of Segment 0 to 14 (cont’d)

Seg-ment

Address Range

Size Description Access TypeRead Write


TC1766


Page 8-17In Table 8-5, the four “–” of Double-word column and CRAM and PRAM rows must bereplaced by “✔ ”. “CRAM” must be replaced with “CMEM”. Footnote 1 must be added tothe PMI and DMI memory cells as "The module also supports LMB 2-Word and 4-WordBlock read and write accesses”.Footnote 2 must be added to the PCP memory cell as"The module also supports FPI 4-Word and 8-Word Block read and write accesses”.

Page 9-15The following sentence must be added at the end of paragraph “Port 0 is a general-purpose 16-bit ... software later.”: “Note that some of the P0.[7:0] lines are used for configuration purposes, too (see Page9-25).”

Page 9-25Section 9.3.3.3 must be changed as described below:

Depending on the TC1766 device version used in an application, several Port 0 lines(meaning several SWOPT bits) are reserved and cannot be used for user systempurposes during a HDRST reset operation. Table 9-8 defines the reserved Port 0 lines(indicated by 0 or 1) as well as the Port 0 lines that can be used by a user program

102) AFE1 4000H - AFE1 FFFFH

48 Kbyte Reserved LMBBET LMBBET

AFE2 0000H - AFF1 FFFFH

1 Mbyte Reserved LMBBET LMBBET

AFF2 0000H - AFF5 FFFFH

256 Kbyte Reserved for TC1766 emulation device memory

AFF6 0000H - AFFF BFFFH

624 Kbyte Reserved

AFFF C000H - AFFF FFFFH


1) Cached area2) Non-cached area

9.3.3.3 Reserved Port 0 Pins

Table 8-4 LMB Address Map (cont’d)

Seg-ment

Address Range

Size Description ActionRead Write


TC1766


(indicated by “user”) for software configuration selection (or as GPIO pins) depending onthe specific TC1766 device version.

Page 9-32The reset value for P1_IOCR12 should be corrected as 0020 2020H.

Page 9-41P2_IOCR0 should not be linked to footnote 1.

Page 9-42The reset value for P2_IOCR12 should be corrected as 0000 2020H.

Table 9-8 Reserved Port 0 Lines of TC1766 DevicesTC1766 Device Versions SWOPTx Bits (x = 0-15)

P0.[15:8]

P0.[7:6]

P0.5 P0.4 P0.3 P0.[2:0]

TC1766 user user user 1 user 1)

1) The P0.[2:0] bits are only used in alternate boot modes (see Table 4-7). If alternate boot modes are notrequired or used in an application, P0.[2:0] can also be used for user program software configuration selectionpurposes during a hardware reset operation or as GPIO pins.

TC1766ED (Emulation device) XXB2)

2) 00B, 11B : The USB interface of the TC1766ED is not connected to device pins.01B : The USB interface of the TC1766ED is connected to JTAG I/O lines.10B : The USB interface of the TC1766ED is connected to P2.[5:0] lines.

0 or 13)

3) 0: Emulation device functionality is not available.1: Emulation device functionality is fully supported.


TC1766


Page 9-49 to 9-50In Table 9-13, P3.12 and P3.14 Input rows should be updated as below:

In Table 9-13, the text of the associated Reg. I/0 Line TCD0B of P3.13 withP3_IOCR12.PC13 = 1X10B must be changed to TXD0B.

Table 9-13 Port 3 FunctionsPort Pin

I/O Pin Functionality Associated Reg./I/O Line

Port I/O Control Select.Reg./Bit Field Value

P3.12 I General-purpose input P3_IN.P12 P3_IOCR12.PC12

0XXXB

CAN node 0 receive input 0CAN node 1 receive input 1

RXDCAN0

ASC0 input (Asynchronous Mode /Synchronous Mode)

RXD0B

O General-purpose output P3_OUT.P12 1X00B

ASC0 output (Synchronous Mode)1)

RXD0B 1X01B

ASC0 output (Synchronous Mode)

RXD0B 1X10B

Reserved1) – 1X11B

P3.14 I General-purpose input P3_IN.P14 P3_IOCR12.PC14

0XXXB

CAN node 1 receive input 0CAN node 0 receive input 1

RXDCAN1

ASC1 output (Asynchronous Mode/Synchronous Mode)

RXD1B

O General-purpose output P3_OUT.P14 1X00B

ASC1 output (Synchronous Mode)1)

1) The ALT1 and ALT2 for this pin are connected together. There are no dependencies. Either one can bechosen.

RXD1B RXD0B

ASC1 output (Synchronous Mode)

RXD1B RXD0B

Reserved1) – –


TC1766


Page 9-55In Table 9-15, the text of Pin Functionality SCU input of Pin 4.3 with P4_IOCR0.PC3 =1X11B must be replaced with SCU output. In Table 9-16, P4_IOCR0 should not belinked to footnote 1.

Page 9-57Section 9.7.3.3 should be updated as below:

9.7.3.3 Port 4 Input/Output Control Register x (x=4, 8 and 12) Port lines P4.[15:4] are not available. Therefore, PC bit fields; PC[15:4] in registersP4_IOCR4, P4_IOCR8, P4_IOCR12 are not connected.

Page 10-58Bit 5 in the register image of register PCP_ES must be changed into 0,r (instead ofME,rh).

Page 10-59The column “Description ” for bit 5 must be corrected into: “Reserved; read as 0.

Page 10-73The second row (RC0) of Table 10-12 must be replaced by the following row:


TC1766


Page 10-77Figure 10-14 must be replaced by the following figure (block “DATA Transfer” has beenchanged):

Figure 10-14 Counter Operation for BCOPY Instruction

Page 10-98In the syntax description of the ST.PI instruction of the PCP, the register name "Ra"should be replaced by "Rb".

MCA06148

DATA Transfer

(Block sizedetermined by

CNT0 field)

BCOPYInstruction

NextInstruction

CNC = ?

CNT1 := CNT1 - 1 CNT1 := CNT1 - 1

CNT1 = 0 ?

00 10

01

yes

no


TC1766


Page 11-9The wordings “SHADR0n with CHCR0n.SHCT = 01B“on the left of the first waveformfrom the bottom of Figure 11-5 must be replaced with “SHADR0n with ADRCR0n.SHCT= 01B“.

Figure 11-5 Shadow Source Address and Transfer Count Update

MCT06153_c

tc1 = transfer count 1tc2 = transfer count 2sa1 = source address 1sa2 = source address 2

tc1 1tc1-1 tc2 tc2-1 tc2-2

tc1 tc2 tc3

sa1 sa1+1 sa2+1 sa2+2sa2tc1-1sa1+

tc1sa1+

sa2 sa3

1) 3) = writing to CHCR0n and SADR0n2) = start of new DMA transaction with

shadow transfer of source address

0000 0000H

0CHSR0n.TCOUNT

SHADR0n withADRCR0n.SHCT= 01B

SADR0n

CHCR0n.TREL

1) 3)2)


TC1766


Page 11-10Figure 11-6 must be updated as per the corresponding changes on pages 11-35 and 11-50.

Figure 11-6 Channel Request Control

The last sentence of the second last paragraph should be replaced with: “A software request can be generated by setting bit STREQ.SCH0n.”

Page 11-16The paragraphs below “When CHRST.CH0n is set to 1:” must be replaced by thefollowing paragraphs:• Bits TRSR.HTRE0n, TRSR.CH0n, ERRSR.TRL0n, INTSR.ICH0n, INTSR.IPM0n,

WRPSR.WRPD0n, WRPSR.WRPS0n, CHSR0n.LXO, and bit fieldCHSR0n.TCOUNT are reset.

• Source and destination address register will be set to the wrap boundary. SHADR0nwill be cleared.

• All automatic functions are stopped for channel 0n.

MUX

MCA06154c

TRSR

TransferRequestToChannelArbiter

HTRE0n

3

CHCR0n

PRSEL

CH0n_REQ

STREQ

SCH0n

&

TRSR

CH0nSetReset

CHCR0n

RROAT

End ofTransfer

Reset SetReset

MUX

CHCR0n

CHMODE

Suspend Control

&

SUSEN0n

SUSPMRTRSR

0

1End ofTransaction

DCH0n

ECH0n

HTREQ

Suspend Request

&

TransferRequestLostInterruptERRSR

TRL0n

&

Set

CHRSTR

CH0n

CH0n_REQI0CH0n_REQI1CH0n_REQI2

CH0n_REQI3CH0n_REQI4

CH0n_REQI5CH0n_REQI6

CH0n_REQI7

End ofTransaction

≥1

≥1

PatternMatch

Reset

Reset


TC1766


A user program must execute the following steps for resetting a DMA channel:1. If hardware requests are enabled for the DMA channel 0n, disable the DMA channel

0n hardware requests by setting HTREQ.ECH0n = 0.2. Writing a 1 to CHRST.CH0n.3. Waiting (polling) until CHRST.CH0n = 0.A user program should execute the following steps for restarting a DMA channel after it was reset:1. Optionally (re-)configuring the address and other channel registers.2. Restarting the DMA channel 0n by setting HTREQ.ECH0n = 1 for hardware requests

or STREQ.SCH0n = 1 for software requests.The value of CHCR0n.TREL is copied to CHSR0n.TCOUNT when a new DMA transaction is requested and shadow address register contents is not equal 00000000H. Page 11-29In Section 11.1.8.2, the register name EERSR must be replaced by ERRSR in the thirdsentence of the first paragraph, first sentence of the second paragraph and within Figure11-18. The corresponding text must be replaced by :“If such a transaction request lost condition occurs, bit ERRSR.TRL0n is set.” and “Atransaction request lost condition of DMA channel 0n is indicated by status flagERRSR.TRL0n, which can be reset by setting bit CLRE.CTL0n or CHRSTR.CH0n.“Figure 11-18 must be replaced by:

Figure 11-18 Transaction Lost Interrupt

≥1

MCA06166_c

TRL00

TransactionLostIn terrupt 00

ETRL00 TRLINP

EEREERCLREReset

CTL00

ERRSR

TRL07

TransactionLostIn terrupt 07

ETRL07

EERCLRE

CTL07

ERRSR

n = 0-7

Set

CHRSTR

CH00

Reset

CHRSTR

CH07

Set Reset

4

Reset


TC1766


Page 11-30In Section 11.1.8.3, the register name EERSR must be replaced by ERRSR in the firstsentence of the third paragraph and within Figure 11-19. The corresponding text mustbe replaced by :“A source error of Move Engine 0 is indicated by the status flag ERRSR.ME0SER.“Figure 11-19 must be replaced by:

Figure 11-19 Move Engine Interrupts

MCA06167_c

ME0SER

Move Engine 0Source ErrorIn terrupt

EME0SER

≥1

ME0INP

EEREERCLREReset

CME0SER

ERRSR

ME0DER EME0DER

EERCLREReset

CME0DER

ERRSR

Move Engine 0Destination ErrorIn terrupt

Set

Set

4


TC1766


Page 11-35The following paragraphs should be added after the last paragraph(“..for a specific valueof CHDW“) under Section 11.1.9 Pattern Detection:Depending on CHCR0n.PATSEL and on the positive result of the comparison, twoactions follow (if CHCR0n.PATSEL=00, no action will be taken when a pattern match isdetected, so the wrap interrupt can be used):• The activation of the interrupt corresponding to the current active channel 0n using

the Interrupt Pointer defined in CHICR0n.WRPP.• Reset TRSR.HTRE0n and TRSR.CH0n in order to stop the current transaction

(Hardware and Software request enable). The value of CHSR0n.TCOUNT can beread out by the interrupt SW.

The software will have to service the interrupt and to activate again the channel.Page 11-50The description of bit field CH0n must be extended by the following sentence:“CH0n is reset when a pattern match is detected”. The description of bit field HTRE0n must be extended by the following sentence:“HTRE0n is reset when a pattern match is detected”.

Page 11-79The second sentence of the last paragraph should be replaced with:“If DMA channel 0n is active when writing to SADR0n, the source address will not bewritten into SADR0n directly but will be buffered in the shadow register SHADR0n untilthe start of the next DMA transaction.

Page 11-80The second sentence of the last paragraph should be replaced with:“If DMA channel 0n is active when writing to DADR0n, the source address will not bewritten into DADR0n directly but will be buffered in the shadow register SHADR0n untilthe start of the next DMA transaction.


TC1766


Page 11-91Figure 11-29 must be corrected as below:

Figure 11-29 DMA Implementation-specific Registers

DMA InterruptRegisters

Control Register

DMA_CLC DMA_SRC0DMA_SRC1DMA_SRC2DMA_SRC3

MCA06177a

MLI InterruptRegisters

System InterruptRegisters

DMA_SYSSRC0DMA_SYSSRC1DMA_SYSSRC2DMA_SYSSRC3DMA_SYSSRC4

DMA Bus Time-OutRegister

DMA_TOCTRDMA_MLI0SRC0DMA_MLI0SRC1DMA_MLI0SRC2DMA_MLI0SRC3DMA_MLI1SRC0DMA_MLI1SRC1


TC1766


Page 12-26Figure 12-5 must be updated with the following corrected drawing.

Figure 12-5 NMI Trap Handler Routine for Parity Error Handling

Page 14-4The below note must be added to the end of the last sentence of the page.Note: The resetting of the ENDINIT bit takes some time. Accesses to Endinit-protected

registers after the resetting of the ENDINT bit must only be done when ENDINITis really reset. As a solution, WDT_CON0 (the register with the ENDINIT bit)should be read back once before Endinit-protected registers are accessed the firsttime after ENDINIT has been reset.

MCA06449a

V1 := SCU_PETSR

V2.NMIPER = 1?no

yes

V2 := NMISR

V2.NMIEXT set?

Execute ExternalNMI Req. Handler

V2.NMIPLL set?

Execute NMI PLLRequest Handler

V2.NMIWDT set?

Execute WatchdogNMI Req. Handler

yes

yes

Execute Parity ErrorNMI Req. Handler

Entry in TrapHandler Routine

V1 = 0? 1)

V1 := SCU_PETSRyes

no

Exit Trap HandlerRoutine

no

no

yes

no

V2 := NMISR

1) This test is for the case that a parity error occurs after the first read of SCU_PETSR.


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Page 16-15The read and write access modes for address location F000 0804H of Table 16-7 must be changed from “nBE” to “BE”.

Page 16-16The “Reserved” column for address location F000 0850H to F000 08F4H of Table 16-7 must be separated to two different rows of access rights. The read and write accessrights for F000 0850H -F000 0854H are both “nBE” and F000 0858H -F000 08F4H are both“BE”.

Page 16-20 to 16-25The write accesses for all Px_OMR registers (x = 0-5) are corrected from "U,SV" into"U,SV,32".

Page 16-69The long name of register MMU_CON must be changed to “MMU ConfigurationRegister”.

Page 16-79The contents for the short name, description and reset value columns for Table 16-26 ataddress locations F800 05F0H, F800 05F8H, and F800 05FCH must be replaced asshown in Table 16-26.

Table 16-26 Address Map of PMUShort Name Description Address Access Mode Reset

Value1)

1) Which Resets affect the register, see Table 4-2.

Read WriteProgram Memory Unit (PMU)– Reserved2)

2) Do not read from or write to these address locations.

F800 05F0H U, SV E, U, SV

–

– Reserved F800 05F4H BE BE –– Reserved2) F800 05F8H BE E, U,

SV, 32

–

– Reserved2) F800 05FCH U, SV BE –


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User’s Manual - Peripheral Units Part (Volume 2)

3 User’s Manual - Peripheral Units Part (Volume 2)This section describes corrections for the Peripheral Units part of the User‘s Manual.

Page 17-28Figure 17-12 should be updated with the below figure:

Figure 17-12 ASC0/ASC1 Module Implementation and Interconnections

Page 18-15In Figure 18-8, the description at the bottom of the figure, “CON.PH = CON.PO = 1” mustbe replaced by “CON.PH = 0; CON.PO = 1”.

MCB06211c

ASC0Module(Kernel)

Port 3Control

ASC1Module(Kernel)

P3.12 /RXD0BP3.13 /TXD0B

P3.0 /RXD0AP3.1 /TXD0A

P3.14 /RXD1B

P3.15 /TXD1B

P3.9 /RXD1A

P3.8 /TXD1A

RXD_I1

RXD_O

RXD_I0

TXD_O

RXD_I1

RXD_O

RXD_I0

TXD_O

InterruptControl

EIRTBIRTIRRIR

ClockControl

AddressDecoder

InterruptControl

fASC

EIRTBIRTIRRIR

ToDMA

ASC0_RDRASC0_TDR

ToDMA

ASC1_RDRASC1_TDR

A2

A2

A2

A2

A2

A2

A2

A2


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Page 18-16After the first sentence on the top of this page, the following sentence must be added:“With a TB write operation, all timing parameters stored in register SSOTC as well as theSSOC register are latched and remain valid for the consecutive transmission.“In the first line of the paragraph below “Slave Select Output Control”, the text“SSOC.OENn = 0” must be replaced by “SSOC.OENn = 1”.

Page 18-17In the first line below heading “Slave Select Register Update”, the text in brackets “withthe activation of SLSOn” must be replaced by the text “with the TB register writeoperation“.


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Figure 18-11 SSC Error Interrupt Control

MCA05789_c

ErrorInterruptEIR

≥1

CON.PEN

STAT.PE

&

Set

Reset

Set

CON.BEN

STAT.BESetReset

Set&

EFM.SETTEEFM.CLRTE

EFM.SETREEFM.CLRRE

EFM.SETPE

EFM.CLRPE

EFM.SETBEEFM.CLRBE

CON.TEN &STAT.TE

Set

Reset

Set

Transmit Error

Receive Error

CON.REN &STAT.RE

SetReset

Set

Phase Error

Baud Rate Error


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Page 18-19In the first note which is located at the upper part of the page, the text “CON.REN = 1”must be replaced by “CON.AREN = 1”.

Page 18-19The following note must be inserted after the first note of the page:Note: This error can occur after any transfer if the communication is stopped. This is due

to the fact that SSC supports back-to-back transfers for multiple transfers. In orderto handle this, the baud rate detection logic expects a next clock cycle immediatelyfor a new transfer after a finished transfer.

Page 18-23In the STIP bit description, the sentence “This bit determines...” must be replaced by thefollowing sentence:“This bit determines the logic level of the Slave Mode transmit signal when the SSC slaveselect input signals are inactive (PISEL.SLSIS ≠ 000B).”

Page 18-25The bit description of bit EN must be extended by the following sentence: “Note that ENshould only be reset by software while no transfer is in progress (STAT.BSY = 0)”.

Page 18-29The note paragraph at the bottom of the page must be replaced by the following noteparagraph:Note: The SSOC register content is latched by each TB register write operation and

remains latched during the consecutive serial transmission.

Page 18-30In the bit description of register SSOTC a footnote 1) must be added to the bitcombinations 00Β of bit fields LEAD, TRAIL, and INACT:“1) For getting a best case timing with no timing delays (see Figure 18-8), this bit fieldvalue should be set when the SLSOn outputs are disabled (SSOC.OENn bits set to 0).”

Page 18-30The note paragraph after the SSOTC register description table must be replaced by thefollowing note paragraph:Note: The SSOTC register timing parameters are latched by each TB register write

operation and remain latched during a consecutive serial transmission.


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Page 19-20The following sentence should be added at the end of the Section 19.1.2.6 “Note that inthis case no time frame finished interrupt is generated any more.“.

Page 19-42Description of bit field NDBH: for bit combination NDBH = 00000B, the text “No SRH bitshifted“ should be replaced by “No SRH bit shifted; no selection bit is generated, the SRHactive phase is completely skipped.“.

Page 20-49The following paragraph should be added after the last paragraph:"In order to avoid direct reception of a message by a slave message object, as if it wasan independent message object and not a part of a FIFO, the bit RXEN of each slaveobject must be cleared. The setting of the bit RXEN is “don’t care” only if the slave objectis located in a list not assigned to a CAN node."

Page 20-50The first paragraph should be extended by a second sentence:"A transmit FIFO consists of one base message object and one or more slave messageobjects."

Page 20-54Table 20-4: The offset addresses of the four registers must be corrected as follows:MSIMASK = 01C0HPANCTR = 01C4HMCR = 01C8HMITR = 01CCH

Page 20-75In Table 20-6, the two sentences in column “Signification” for LEC value 111B at thebottom of the page must be replaced by the following two sentences:"Whenever the CPU writes the value 111B to LEC, it takes the value 111B. Wheneverthe CPU writes another value to LEC, the written LEC value is ignored."

Page 20-85In the first row of Table 20-8, column “CAN Bus State”, the wording “reserved bits, “ mustbe deleted. In the second row of Table 20-8, column “CAN Bus State”, the wording“reserved bits, “ must be inserted at: “ .....RTR, reserved bits, IDE, ....”.


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Page 20-109The paragraph after Equation (20-2) must be replaced by the following:Equation (20-1)applies to normal divider mode (CAN_FDR.DM = 01B) of the fractional divider.Equation (20-2) applies to fractional divider mode (CAN_FDR.DM = 10B).

Page 20-116The first sentence of the second paragraph must be replaced by: “Each of the 136hardware initiated interrupt sources is controlled by a 4-bit interrupt pointer that directsthe interrupt source to one of the six interrupt outputs INT_Om (m = 0-5).“


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Figure 20-27 Interrupt Compressor

MCA06284_c

4-bitIn terruptPoin ter

In terruptSource

InterruptRequestOutputINT_Om

72Inputs

Interrupt Pointer Control

.........

Interrupt Output Control

.........

16Outputs

......

4

0000

1111

≥1

16RegisterMITR

16

16

CANNode

0

16

16

16

16

16

16

16

16

CANNode

1

INT_O4

INT_O5

73

73

≥1

≥1

..............................

INT_O0

INT_O1

73

73

≥1

≥1

InterruptWiringMatrix

16MessageObject

0

16MessageObject

63


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Page 20-118The first sentence of the page must be replaced by: “Each of the six interrupt outputsINT_Om of the MultiCAN module is controlled by its service request control registers.“

Page 21-2The bullet paragraph “Programmable baud rate: .....” under “Features” must be changedas follows:• Programmable baud rates

– MLI transmitter baud rate: max. fMLI/2 (= 40.0 Mbit/s @ 80 MHz module clock)– MLI receiver baud rate: max. fMLI

Page 21-30The following sentence must be added at the end of section “21.1.5 MLI ReceiverOperation”:“The MLI receiver is able to operate with a maximum receive clock (RCLK) frequency upto the frequency of the module clock fMLI.

Page 21-79In the register table of register RPxBAR the row for bits [3:0] should be deleted. Therange for ADDR bit field must be extended to [31:0].

Page 21-108The following paragraph with the formula must be added after the last paragraph:The receiver baud rate is defined by the following formula.

(21.4)Baud rateRCLKmax = fMLI


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Page 21-116In the register table, P5_IOCR8 and P5_IOCR12 should be updated as below:

Page 21-117In the register table, P5_PDR should be updated as below:

1) For coding of bit field, see Table 21-9. Shaded bits and bit fields are “don’t care” for MLI I/O port control.

rw

Field Bits Type Description

Port Input/Output Control for Port 5.[11:8]Port input/output control for P5.8/RDATA0B/TDATA1Port input/output control for P5.9/RVALID0B/TVALID1Port input/output control for P5.10/RREADY0B/TREADY1Port input/output control for P5.11/RCLK0B/TCLK1

[7:4],[15:12],[23:20],[31:28]

PC8,PC9,PC10,PC11

1)

rw


Port Input/Output Control for Port 5.[15:12]Port input/output control for P5.12/TDATA0B/RDATA1Port input/output control for P5.13/TVALID0B/RVALID1Port input/output control for P5.14/TREADY0B/RREADY1Port input/output control for P5.15/TCLK0B/RCLK1

[7:4],[15:12],[23:20],[31:28]

PC12,PC13,PC14,PC15

1)

1) For coding of bit field, see Table 21-9. Shaded bits and bit fields are “don’t care” for MLI I/O port control.

rw


Pad Driver Mode for P5.15, P5.[13:12] and P5.10Pad Driver Mode for P5.14, P5.11 and P5.[9:8]

[18:16],[22:20]

PDMLI0,PDMLI1 rw


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Page 22-60The first three sentences of the first paragraph on the top must be replaced by threeextended sentences:Old:“Normally, a GTC is enabled by writing GTCCTRk.EOA (Enable-Of-Action) with 0. Notethat bit EOA is hardware protected. Therefore, any bit operation on EOA will result in aread-modify-write access.“New:“A GTC is enabled by writing (ST byte, word, half-word operation) GTCCTRk.EOA(Enable-Of-Action) with 0. Because bit EOA is hardware protected, read-modify-writeoperations (LDMST, ST.X, SWAP) only enable the GTC if bit EOA is modified from 1 to0.“

Page 22-69In the first sentence, the wording "adjacent GTCs" must be replaced by "adjacent LTCs".

Page 22-70Fourth bullet paragraph in section "Free-Running Timer Mode": "GTCkOUT" must bereplaced by "LTCkOUT".

Page 22-71Second bullet from the top: "GTCkOUT" must be replaced by "LTCkOUT".Third bullet paragraph in section "Compare Mode": "GTCkOUT" must be replaced by"LTCkOUT"The last note paragraph must be deleted.

Page 22-74Paragraph above the figure: "GTCs" must be replaced twice by "LTCs".Paragraph below the figure title paragraph: "GTCCTRk.OCM0" must be replaced by"LTCCTRk.OCM0".

Page 22-75The header text “Local Capture or Compare Event” of the second column in Table 22-4must be replaced by “Local Capture, Compare, or TImer Overflow Event”.


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Page 22-76The first three sentences of the first paragraph on the top must be replaced by threeextended sentences:Old:“Normally an LTC is enabled by writing LTCCTRk.EOA (Enable-Of-Action) with 0. Notethat bit EOA is hardware protected. Therefore, any bit operation on EOA will result in aread-modify-write access.“New:“An LTC is enabled by writing (ST byte, word, halfword operation) LTCCTRk.EOA(Enable-Of-Action) with 0 in Capture Mode or Compare Mode. Because bit EOA ishardware prodected, read-modify-write operations (LDMST, ST.X) only enable the LTCif bit EOA is modified from 1 to 0 in Capture Mode or Compare Mode. If switching toTimer Mode, the LTC cell is enabled. If in Timer Mode every write operation into bit 0..7will enable the LTC..“


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Page 22-89The last sentence of the first paragraph should be replaced by “The GPTA moduleprovides a total of 56 input lines and 112 output lines, assigned to seven I/O groupsIOG[6:0] and seven output groups OG[6:0].”Figure 22-59 should be updated with the below figure:

Figure 22-59 Input/Output Line Sharing Unit Overview

MCA06382_c

INT[3:0]

OUT[55:00]

GTCInput

Multiplexer

LTCInput

Multiplexer

IN[55:00]

OUT[111:56]

GPTAModuleKernel

OutputGroups

I/O Groups

OG0

OG1

OG2

OG4

OG3

OG5

OG6

IOG3

IOG2

IOG1

IOG0

IOG5

IOG4

56

56

56

56

32

56 64

GTCG3

GTCG2

GTCG1

GTCG0

GTC Groups

LTCG3

LTCG2

LTCG1

LTCG0

LTC Groups

LTCG7

LTCG6

LTCG5

LTCG4

32

64

OutputMultiplexer

8

8

24

8

PDL[3:0]INT[3:0]

CLK[7:0]

FPC[5:0]

INT[1:0]

4

IOG6


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Page 22-90Figure 22-60 should be updated with the below figure with the example for OG2corrected:

Figure 22-60 Group Definitions For I/O Line Sharing Unit

MCA06383_c

LTC24INLTC25INLTC26INLTC27INLTC28INLTC29INLTC30INLTC31IN

Example for anLTC Group:

LTCG3

LTC24LTC25LTC26LTC27LTC28LTC29LTC30LTC31

LTC24OUTLTC25OUTLTC26OUTLTC27OUTLTC28OUTLTC29OUTLTC30OUTLTC31OUT

GTC08INGTC09INGTC10INGTC11INGTC12INGTC13INGTC14INGTC15IN

GTC08GTC09GTC10GTC11GTC12GTC13GTC14GTC15

GTC08OUTGTC09OUTGTC10OUTGTC11OUTGTC12OUTGTC13OUTGTC14OUTGTC15OUT

Pin IO40Pin IO41Pin IO42Pin IO43Pin IO44Pin IO45Pin IO46Pin IO47

OUT40OUT41OUT42OUT43OUT44OUT45OUT46OUT47

Pin O72Pin O73Pin O74Pin O75Pin O76Pin O77Pin O78Pin O79

OUT72OUT73OUT74OUT75OUT76OUT77OUT78OUT79

Clock Busof

ClockDistribution

Logic

CLK0CLK1CLK2CLK3CLK4CLK5CLK6CLK7

FPC0FPC1FPC2FPC3FPC4FPC5

INT1

Clock Group FPC/INTGroup

INT0INT1

PDL Busof

PDL0/PDL1

PDL0PDL1PDL2PDL3INT0INT1INT2INT3

PDL/INTGroup

Example for anGTC Group:

GTCG1

Example for anI/O Group:

IOG5

Example for anOutput Group:

OG2

SOL0SOL1SOL2SOL3SOL4SOL5INT0 INT2

INT3

INT0INT1

IN40IN41IN42IN43IN44IN45IN46IN47


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Page 22-91The third and fourth paragraphs should be replaced by:“An I/O group combines eight GPTA I/O lines connected to bi-directional device pins withits input and output lines. This results in seven I/O groups, IOG0 to IOG6, supporting56 I/O lines.” “An output group combines eight GPTA output lines connected to device pins as anoutput. This results in seven output groups, OG0 to OG6, supporting 56 output lines.” In Table 22-8, the input and output lines assigned for I/O Groups and Output Groupsshould be replaced by:

Table 22-8 Group to I/O lines/Cell AssignmentGroup/Module Cell/Line Input OutputI/O GroupIOG0 – IN[07:00] OUT[07:00]IOG1 – IN[15:08] OUT[15:08]IOG2 – IN[23:16] OUT[23:16]IOG3 – IN[31:24] OUT[31:24]IOG4 – IN[39:32] OUT[39:32]IOG5 – IN[47:40] OUT[47:40]IOG6 – IN[55:48] OUT[55:48]Output GroupOG0 – – OUT[63:56]OG1 – – OUT[71:64]OG2 – – OUT[79:72]OG3 – – OUT[87:80]OG4 – – OUT[95:88]OG5 – – OUT[103:96]OG6 – – OUT[111:104]


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Page 22-94The first paragraph of Section 22.2.4.2 should be replaced by “The output multiplexershown in Figure 22-59 and Figure 22-61 below connects the 32 GTC output lines andthe 64 LTC output lines with the I/O groups (7 x 8 = 56 input/output lines) and the outputgroups (7 x 8 = 56 output lines).Figure 22-61 should be updated with the below figure:

Figure 22-61 Output Multiplexer

The third sentence onwards for the paragraph below Figure 22-61 should be replacedby “In the same way, I/O groups and output groups are grouped into 14 groups (sevenI/O groups and seven output groups) with 8 lines each. IOG0 and OG0 share the samephysical pins, similarly for IOG1 and OG1, IOG2 and OG2. IOG3 and IOG6 share thesame physical pins for inputs and outputs.

LTC

Gro

ups

GTC

Gro

ups

I/O Groups Output Groups

MCA06384_c

IOG0 IOG1 IOG2 IOG3 IOG4 IOG5

OMG00

OMG02

OMG03

OMG04

OMG05

OMG10

OMG11

OMG12

OMG13

OMG14

OMG15

OMG24

OMG25

OMG20

OMG21

OMG22

OMG01

OG0 OG1 OG2 OG3 OG4 OG5 OG6

OMG0C

OMG18

OMG07

OMG19

OMG09

OMG0A

OMG1A

OMG0B

OMG1B

OMG1C

OMG0D

OMG1D

OMG2D

OutputMultiplexer

OMG06

OMG26

8 8 8 8 8 8 8 8 8 8 8 8 8 8

8

8

OMG27

OMG23

OMG28

OMG17

OMG29

OMG2A

OMG16

OMG2C

OMG08

8

8

8

8

8

8

8

8

8

8

GTCG0GTC[07:00]

GTCG1GTC[15:08]

GTCG2GTC[23:16]

GTCG3GTC[31:24]

LTCG0LTC[07:00]

LTCG1LTC[15:08]

LTCG2LTC[23:16]

LTCG3LTC[31:24]

LTCG5LTC[47:40]

LTCG6LTC[55:48]

LTCG7LTC[63:56]

LTCG4LTC[39:32]

OMG2B

IOG6


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Page 22-96The second sentence of the third bulleted point should be replaced by:“I/O groups IOG0 to IOG6 are assigned to index variable (g = 0 to 6) and output groupsOG0 to OG6 are assigned to index variable (g = 7 to 13).”Figure 22-63 should be updated with the below figure:

Figure 22-63 Output Multiplexer Group (Programmer’s View)

MCA06386_c

010001000

2. LevelMux

OMLn

OMGn

1. LevelMux

OMCRLgOMCRHg(g = 0-13)

To input ofI/O Group g orOutput Group (g-7)

1

MAEN

MRACTL

&Not a reservedOMGn bit combination

8

8

8

3

0 0

GTC Group(OMG0g)

LTC Group(OMG1g)

LTC Group(OMG2g)

3

MUX

MUX

MUX

MUX

MUX


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Page 22-97In Table 22-10, the input and output lines assigned for I/O Groups IOG3 and OutputGroups OG0 to OG7 should be replaced by:

Table 22-8 Output Multiplexer Control Register AssignmentInput/Output Group Controlled by Multiplexer

Control RegisterSelectable Groups via OMGng

IOG3 IN[27:24]/OUT[27:24] OMCRL3 GTGG3,LTCG3, LTCG7 IN[31:28]/OUT[31:28] OMCRH3

IOG6 IN[51:48]/OUT[51:48] OMCRL6 GTGG2,LTCG2, LTCG6 IN[55:52]/OUT[55:52] OMCRH6

OG0 OUT[59:56] OMCRL7 GTGG3,LTCG3, LTCG7 OUT[63:60] OMCRH7








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Figure 22-64 GTC Input Multiplexer

LTCInput

Multiplexer

LTC

Gro

ups

I/O G

roup

s

MCA06387_c

GTC Groups

IOG0

IOG1

IOG2

IOG3

LTCG0LTC[07:00]

LTCG1LTC[15:08]

LTCG2LTC[23:16]

LTCG3LTC[31:24]

LTCG5LTC[47:40]

LTCG6LTC[55:48]

LTCG7LTC[63:56]

LTCG4LTC[39:32]

GTCG0GTC[07:00]

GTCG1GTC[15:08]

GTCG2GTC[23:16]

GTCG3GTC[31:24]

IOG6

IOG5

IOG4

FPC[5:0]INT[1:0]

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8 GIMG40

GIMG41

GIMG42

GIMG43

GIMG31

GIMG32

GIMG33

GIMG30

GIMG20

GIMG21

GIMG22

GIMG23

GIMG10

GIMG11

GIMG12

GIMG00

GIMG02

GIMG03

GIMG01

8 8 8 8


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Page 22-100The second sentence of the first paragraph should be replaced by:“GTC input Multiplexer Group are grouped into seven IOGs (IOG[6:0]) with seven blocksof eight lines each and eight LTC groups (LTCG[7:0]) with 8 cells each.”

Page 22-101The second bulleted point should be replaced by:“Index n is a group number. I/O groups IOG[3:0] have group number 0, I/O groupsIOG[6:4] have group number 1, local timer cell groups LTCG[3:0] have group number 2,Local Timer Cell Groups LTCG[7:4] have group number 3, and the FPC/INT group hasgroup number 4.”The last sentence of the next paragraph should be replaced by:“For example, based on Figure 22-64, each of the eight GTC input multiplexer outputlines to GTC group GTCG2 is connected via five GIMGn2 (n =0-4) with the eight outputsof two I/O group (IOG2 and IOG6), two LTC groups (LTCG2 and LTCG6), and theFPC/INT group.”

Page 22-103In Table 22-11, the text IOG3 of GTCG2 row should be replaced by “IOG6”


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Figure 22-67 LTC Input Multiplexer

Page 22-105The second sentence of the first paragraph should be replaced by:“IOGs and GTCs are grouped into seven IOGs (IOG[6:0]) with seven blocks of eightlines each and four GTC groups (GTCG[3:0]) with 8 cells each.”

I/O G

roup

sG

TC G

roup

s

MCA06390_c

LTC Groups

IOG0

IOG1

IOG2

IOG3

LIMG00

LIMG02

LIMG03

LIMG10

LIMG11

LIMG12

LIMG01

IOG6

IOG4

PDL[3:0]INT[3:0]

LTCG0LTC[07:00]

LTCG1LTC[15:08]

LTCG2LTC[23:16]

LTCG3LTC[31:24]

LTCG5LTC[47:40]

LTCG6LTC[55:48]

LTCG7LTC[63:56]

LTCG4LTC[39:32]

LIMG04

LIMG06

LIMG07

LIMG05

LIMG14

LIMG15

LIMG16

GTCG0GTC[07:00]

GTCG1GTC[15:08]

GTCG2GTC[23:16]

GTCG3GTC[31:24]

CLK[7:0]

LIMG25

LIMG26

LIMG46

LIMG47

LTCInput

Multiplexer

8 8 8 8 8 8 8 8

8

LIMG24

LIMG27

LIMG37

LIMG36

LIMG45

LIMG35

LIMG44

LIMG34

LIMG43

LIMG33

LIMG41

LIMG42

LIMG31

LIMG32

LIMG40

LIMG30

8

8

8

8

8

8

8

8

8

8

8

LIMG21

LIMG22

LIMG23

8IOG5

LIMG20


TC1766


Page 22-106The second bulleted point of the first paragraph should be replaced by:“Index n is a group number. I/O groups IOG[3:0] have group number 0, I/O groupsIOG[6:4] have group number 1, Global Timer Cell Groups GTCG[3:0] have groupnumber 2, clock bus lines CLK[7:0] have group number 3, and the PDL/INT group hasgroup number 4.”The last sentence of the next paragraph should be replaced by:“For example, based on Figure 22-67, each of the eight LTC input multiplexer outputlines to LTC group LTCG2 is connected via five LIMGn2 (n = 0-4) with the eight outputsof two I/O group (IOG2 and IOG6), one GTC group (GTCG2), the clock group, and thePDL/INT group.”

Page 22-108In Table 22-12, the text IOG3 of LTCG2 row should be replaced by “IOG6”

Page 22-125The text "else DCMk.Timer ++" must be included between the last two "endif" lines onthe bottom.

Page 22-132Below the second last line of the page : "GTCk.Cell_Enable = 1", the following line mustbe added: "GTCk.Enable_Of_Action = 0"

Pages 22-173 and 22-174The long name of register LTCCTRk must be corrected as “Local Timer Cell ControlRegister k .....”.

Page 22-178The long name of register LTCCTR63 must be corrected as “Local Timer Cell ControlRegister 63”.

Page 22-184The text for Section Output Multiplexer Control Registers should be replaced by:“Two registers, OMCRL and OMCRH, are assigned to each I/O Group IOG[6:0] andeach Output Group OG[6:0]. OMCRL[6:0]/OMCRH[6:0] are assigned to IOG[6:0] andOMCRL[13:7]/OMCRH[13:7] are assigned to OG[6:0].OMCRL controls the connections of group pins 0 to 3. OMCRH controls the connectionsof group pins 4 to 7.”


TC1766


Page 22-200The first sentence of the first paragraph of Section 22.4.3.1 should be replaced by:“In the TC1766, the seven I/O groups and three output groups of GPTA0 with their inputlines IN[55:0] and output lines OUT[79:0] are assigned to five 8-bit port groups and two4-bit port groups as shown in Figure 22-75.”Figure 22-75 should be updated with the below figure:

Figure 22-75 I/O Port Line Assignment

MCA06398_c

Port Control

OUT[79:0] (from GPTA0)

IN[55:0]

8

8

8

4

4

8

8

P0.[7:0]

P0.[15:8]

P1.[7:0]

P4.[3:0]

P2.[7:0]

P5.[7:0]

P1.[11:8]

[7:0] IOG0[7:0] IOG0[63:56] OG0

[39:32] IOG4[39:32] IOG4

[47:40] IOG5

[47:40] IOG5

[23:16] IOG2[23:16] IOG2[79:72] OG2

[31:24] IOG3[31:24] IOG3[55:48] IOG6[55:48] IOG6

[8:15] IOG1[8:15] IOG1[71:64] OG1


TC1766


Page 22-205The following sentence should be added above Table 22-22, “ Table 22-22 also showsthe assignment of the GPTA module’s four OGx output group lines OGx.y to the outputsignals OUT[111:80].”

Page 22-209The following attention paragraph must be added at the bottom of the page:Attention: If the frequency of the module timer clock fGPTA0 is configured to be

smaller than the control clock fCLC (as programmed in registerGPTA0_FDR) or even disabled (as programmed in registerGPTA0_EDCTR), an action initiated by a write access to a moduleregister could be significantly delayed, because the register writeaccess is clocked by fCLC and the register content is evaluated byhardware using the slower or disabled module timer clock fGPTA0.

Table 22-22 GPTA0 to MSC Interconnection AssignmentMSC0Input Line

AssignedGPTA0 Output Line

MSC0Input Line

AssignedGPTA0 Output Line

ALTIN0.0 OUT80 / OG3.0 ALTIN1.0 OUT96 / OG5.0ALTIN0.1 OUT81 / OG3.1 ALTIN1.1 OUT97 / OG5.1ALTIN0.2 OUT82 / OG3.2 ALTIN1.2 OUT98 / OG5.2ALTIN0.3 OUT83 / OG3.3 ALTIN1.3 OUT99 / OG5.3ALTIN0.4 OUT84 / OG3.4 ALTIN1.4 OUT100 / OG5.4ALTIN0.5 OUT85 / OG3.5 ALTIN1.5 OUT101 / OG5.5ALTIN0.6 OUT86 / OG3.6 ALTIN1.6 OUT102 / OG5.6ALTIN0.7 OUT87 / OG3.7 ALTIN1.7 OUT103 / OG5.7ALTIN0.8 OUT88 / OG4.0 ALTIN1.8 OUT104 / OG6.0ALTIN0.9 OUT89 / OG4.1 ALTIN1.9 OUT105 / OG6.1ALTIN0.10 OUT90 / OG4.2 ALTIN1.10 OUT106 / OG6.2ALTIN0.11 OUT91 / OG4.3 ALTIN1.11 OUT107 / OG6.3ALTIN0.12 OUT92 / OG4.4 ALTIN1.12 OUT108 / OG6.4ALTIN0.13 OUT93 / OG4.5 ALTIN1.13 OUT109 / OG6.5ALTIN0.14 OUT94 / OG4.6 ALTIN1.14 OUT110 / OG6.6ALTIN0.15 OUT95 / OG4.7 ALTIN1.15 OUT111 / OG6.7


TC1766


Page 23-9The formula on the bottom of the page must be corrected into:

(23.1)

Page 23-96Footnote 1 must be deleted from AN24 to AN31 cells.

Page 23-97The below text must be inserted before Figure 23-30.For safety reasons, the measurement of the ADC channels 0-15 (GRPS = 0) is alwaysrelated to the reference input pin (the programmed selection is not taken into account).The measurement of the ADC channels 16-31 (GRPS = 1) is always related to theprogrammed reference (the programmed selection is taken into account).

Page 24-6The two heading paragraphs must be corrected in the following way:Replace “Configuration 3” with “Configuration 2”Replace “Configuration 4” with “Configuration 3”

Page 24-7The text in the leftmost column of Table 24-1 must be corrected in the following way:Replace “(Configuration 2)” with “(Configuration 1)”Replace “(Configuration 3)” with “(Configuration 2)”Replace “(Configuration 4)” with “(Configuration 3)”The last row of Table 24-1 (FAINxN | FAINxP I XXB | 512) must be deleted.

Page 24-8The second formula of equation (24.1) should be corrected into:VFAREFM = VFAGND + (VFAREF -VFAGND)/2

tTPERIOD TRLD 20fADC-----------×=


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