Debug your memory system

with innovative oscilloscope tools

InfiniiScan+

InfiniiSim

Serial Data Package

PrecisionProbe

Agenda

Probing Challenges

• De-embed probing effect for accurate measurement

• PrecisionProbe for maximizing probe performance

DDR memory SI design phases and testing

Trigger and Measure

• Read and Write Data

• Eye Diagram measurement

Analyze • Make measurement and verify against JEDEC spec.

• Run automated measurement to save time.

200 333 400

633 667 800

1066

1333

1600

1866

2133

3200

Da

ta

ra

te

(M

T/s

)

DDR Speed Transition

Key Memory Design Challenges

Faster Data Rate SI verification

- stricter rule in platform design Margin testing

- System requires more system margin

Probe load - Probe load reduces system margin

Compact/Small Board Design Less probing space

- Signal accessibility is limited

Less probing options - Conventional probing limits signal insights

High density board design:

Where to probe?

SI testing is essential for

High speed data rate

DDR3

DDR2

DDR1

DDR4

Agenda

Probing Challenges

• De-embed probing effect for accurate measurement

• PrecisionProbe for maximizing probe performance

DDR memory SI design phases and testing

Trigger and Measure

• Read and Write Data

• Eye Diagram measurement

Analyze • Make measurement and verify against JEDEC spec.

• Run automated measurement to save time.

Probing Challenges

Probing at the wrong location causes reflection, resulting in non-monotonic edges. This will cause error in your tests such slew rate, setup and hold time measurements.

Load on probing affects the signals on your system as well as what you measure.

Probing at transmission lines or surface mount components cause signal

reflection and other SI issues

Midbus probing • Non ideal for SI test

How do I probe my memory signals?

If vias are accessible:

For BGA package, probing at the via close to the balls of the DDR DRAM generally gives you

the best results since the JEDEC standard is defined at the balls

of the DRAM.

If vias are NOT accessible:

For embedded system with tight board spaces and fully

populated DIMM configuration, BGA probes

provide signal access

BGA probe on DIMM configuration

Fully populated DIMM • No vias to probe

BGA probe on embedded board

design

Concern with BGA probing: Does BGA probe affects the SI of my board?

BGA probe and Via probing Comparison – Before

de-embedding

Scope optimized BGA probe

Channel 1: Probing at VIA (under the DRAM) Channel 2: Probing at scope pad point

Skew caused by delay

Skew caused by delay

Channel 1: Probing at VIA Channel 2: Probing at scope pad point on adapter board

Decrease in amplitude

Flex wing BGA probe with adapter board

Good for SI check: High bandwidth probe allows for

Measurement distorted for SI check: Signal performance is affected using the BGA probe for SI check. How do I simulate an ideal probe?

Oscilloscope de-embed tool - InfiniiSim

Physical layout of a board

Memory Controller DRAM

BGA probe

InfiniiSim - General Purpose 9 Blocks Topology Memory

Controller DRAM

BGA probe

S parameter

file

InfiniiMax

probe head

s1p file

Measurement

Simulation

Delay

InfiniiMax probe head

Sub-circuit Modeling of DDR BGA probe

Oscilloscope de-embed tool – After de-embedding

Channel 1: Probing at VIA (DQS strobe) Channel 2: Probing at scope pad point

Channel 1: At VIA (DQS strobe) Channel 2: At scope adapter board

Turn on Bandwidth Limit to 4G on the channel to reduce the ringing effect due to high frequency content.

Signal at BGA probe is identical to signal probing at via. Measurement result is not compromised by the probing effect.

DDR3 BGA Probe Optimum Bandwidth

Nominal BW for BGA probe is between 1.5 and 2 GHz

before probe correction

DDR3 BGA probe is the most common

probe used in DRAM probing

Concerns:

• DDR3/4 data rate is increasing to > 2GB/s

• Probing effect affects SI measurement

DRAM

DDR3 BGA probe

with scope pads for

signal accessibility

DRAM soldered on to

DDR3 BGA probe

and system test

DDR3 BGA Probe Correction Method

1. Apply solder bumps to all of the ground (VSS)

connections on the outer rows of the interposer.

2. Planarize/Level the solder bumps with a large

piece of ceramic.

3. Cut out two pieces of z-axis connection

material, elastomer contact.

4. With a microscope, align the BGA probe

above the thru fixture so that only the signal ball

contacts the transmission line and all of the

ground balls contact ground.

VSS Signal for

correction

VSS

Signal contacts

transmission line on

thru fixture Signal of interest contacts transmission line on thru fixture through elastomer

DDR BGA probe

Solder ball

Elastomer

VSS (ground) contacts ground on thru fixture through elastomer

Thru fixture

PrecisionProbe Fixture Setup

5. Connect the thru fixture to the channel

input of the oscilloscope and feed CAL out

from the oscilloscope to the thru fixture with

a SMA cable.

6. Solder the probe head to the oscilloscope

pads on the BGA probe and connect to one

of the channel inputs.

•Vin is defined as the signal at the BGA

probe point while the signal is being loaded

by the BGA probe.

•Vout is the signal that is output from the

BGA probe.

•Vout/Vin Correction, the signal at the

output of the probe is an accurate

representation of the signal that currently

exists, as it is being probed

Thru fixture with BGA probe ready for calibration

with the scope

Vin

PrecisionProbe Calibration

6. PrecisionProbe Wizard

PrecisionProbe and Cable provide an easy to follow guide with its wizard. The wizard

takes you step by step through the set up of the software and ensures that your

measurements are taken with the highest signal integrity.

Bandwidth control

allows you to

remove unwanted

high frequency

noise by providing

a filter.

Save and Recall the

PrecisionProbe calibration result.

Corrected Probe Response

The BGA probe response corrected to close to 10GHz

Probe Input Impedance

Knowing the impedance profile of the

probe allows you to estimate the loading

of the probe system.

Real Time Eye Diagram Measurement

GDDR5 Write DQ Real Time Eye Diagram

Without de-embedding

With de-embedding

De-embed DQ cleared mask test

Non de-embed DQ violated mask test

Unfold real time eye to find DQ mask violation

Agenda

Probing Challenges

• De-embed probing effect for accurate measurement

• PrecisionProbe for maximizing probe performance

DDR memory SI design phases and testing

Trigger and Measure

• Read and Write Data

• Eye Diagram measurement

Analyze • Make measurement and verify against JEDEC spec.

• Run automated measurement to save time.

SI Measurement with Oscilloscope

•Read and write data parametric testing •Identify cross talk and ISI failures •Track infrequent events •Jitter characterization •Compliance as per JEDEC standard

Memory Design Phases that requires SI testing Prototyping (alpha and beta) •SI characterization to compare results with design simulation and specification •Margin testing – varying temperature and voltage levels

Post Production • Margin testing for checking compatibility issues

SI Validation Tasks (Trigger and Measure)

How do I trigger on a Read/Write Data

DQS

DQ0

Two distinctive read and write burst patterns

Read and Write data

DDR2/3 Read and Write Burst (DQS) with Data (DQ)

DQ Eye diagram

Read and Write eye overlapping

Idle state

Oscilloscope Zone Qualify Trigger – InfiniiScan+

DQ0

DQS

Zone 1

Zone 2

Zone 1 – Must not Intersect to eliminate Idle State Zone 2 – Must Intersect to trigger on Read DQS to get read Data

Read DQS is edge aligned with Read DQ

Eye Diagram Test after Read/Write Separation

Eye Diagram Test • Allows measurement of eye height and width to measure Data eye height and width • User can also define own mask as per device specification

Mask Test Failure

DQ Mask Violation

• Measure the timing relationship between signals (such as Clock and DQS signals)

• Measure signal integrity

• Rise/fall time

• Slew rate

• Amplitude

• Overshoot/Ringing

• Find patterns on DQ signals for ISI related problems.

Find failure edge and perform SI measurement

Unfold Eye and navigate to failure position

How do I trigger on a read/write command?

CAS#

WE#

WCK/WCK#

DQ

GDDR5 Memory Signals

GDDR5 Command Truth Table GDDR5 Memory Signals

READ: CAS# = Low, WE# = High WRITE: CAS# = Low, WE# = Low Load FIFO, Deselect, Refresh, Self Refresh, Power Down: CAS# = X, WE# = X

There’s no distinctive read/write burst patterns

Oscilloscope Zone Qualify Trigger – InfiniiScan+

Trigger on Write command on GDDR5 signals

Trigger Steps: 1. Trigger on falling edge of CAS 2. Zone 1 – Must Not Intersect to trigger on first burst (CAS=Low) 3. Zone 2– Must Intersect to trigger on WE = Low (write command) 4. Zone 3 – Must intersect to trigger on Write data transition and to eliminate Hi state of data caused by other commands – Self refresh, Power Down..etc

CAS#

WE#

WCK/WCK#

DQ

Zone 2

Zone1

Zone 3

Use only 4 channels to do read/write command trigger

Oscilloscope Zone Qualify Trigger – InfiniiScan+

Determine the Write latency of the GDDR5 write command

CAS#

WE#

WCK/WCK#

DQ

Zone 2

Zone1

Zone 3 Write Latency = 4 CK cycles Or 8 WCK cycles

Quickly determine the read/write latencies of the DRAM with Command trigger

Measurement – Eye Diagram

A successful read/write separation enables data valid window measurement on multiple edges

GDDR5 eye diagram measurement to determine data valid window

Trigger Signal Pattern On screen – InfiniiScan +

Concern: There’s only one signal, DQ0 available for probing, I can see the potential issue on screen, can I trigger?

Potential SI problem due to reflection

DQ0

Measurement – Real Time Eye Diagram

Zone 1: Must intersect to trigger on signal with SI issue only

DQ0

Turn on Real-Time eye to ensure data valid window spec is not compromised: Reflection due to imperfect termination found.

Eye Width and Height measurement

Group/Presentation Title

Agilent Restricted

Month ##, 200X

Track Specific Pattern with InfiniiScan Zone Trigger

Page 29

DQ = “010000101010”

Trigger data “010000101010” with InfiniiScan

1 2

3 4

Allows more robust data pattern test: • Measure SI (rise time, overshoot/undershoot amplitude) during rigorous data transitions.

Agenda

Probing Challenges

• De-embed probing effect for accurate measurement

• PrecisionProbe for maximizing probe performance

DDR memory SI design phases and testing

Trigger and Measure

• Read and Write Data

• Eye Diagram measurement

Analyze • Make measurement and verify against JEDEC spec.

• Run automated measurement to save time.

Analyze

Concern with making manual measurements: Tedious and time consuming, repeatability issues

DDR3 Write Pre-amble width - tWPRE JEDEC spec: DDR3 Write Pre-amble width - tWPRE

Make measurement and verify against JEDEC specification

DDR3 Data Setup Time- tDS JEDEC spec: DDR3 Data Setup Time- tDS

Analyze with Automated Compliance Test

Perform Electrical, Clock and Timing tests

Automated tDS test with measurement result indicating pass/fail status as per JEDEC spec

HTML Test Report with measurement details

AC150/AC175 Levels Setup

Automatically load AC level test limits for different speed grade

JEDEC 3E tIS and tIH test limits

Example:

The tIS(base) AC150 specifications are

adjusted from the tIS(base) specification by

adding an additional 100 ps of derating to

accommodate for the lower alternate

threshold of 150 mV

Custom Derating Table for Characterization

Example: tIS (total setup time) = tIS(base) + ΔtIS

Note: ΔtIS is determined from the derating table

DDR Derated Command/Address and Data Tests Custom Derating table support

Editable DeratingAndBaseTable.dat

Automated Threshold Settings for DDR

Characterization

Wizard for voltage threshold settings

“Set” automatically calculate the Vref and VTT voltages

Measurement threshold applies to Single Ended/Differential Input/Output signals

The intuitive GUI in the automated compliance app allows for measurement of non-standard DDR voltage levels. For example, 1.25V.

Multi-Burst Measurement for Statistical Analysis

4 sets of bursts found in one single acquisition

Multi-burst measurement allows measurement of multiple bursts in a single acquisition or multi acquisition for statistical analysis – Min, Max, Mean, Stdev

Margin testing with Compliance Test

Check for compatibility and margin allowance • Use a standard measurement methodology for repetitive testing with variance of temperature and voltage. • Compile test result/report on margin for finding optimal performance.

Compliance test report enables margin reporting

Testing eMMC with User Defined Application

Processor

Baseband + Application

eMMC LPDDR2

ROM RAM

Create your own eMMC Compliance Test with UDA

1. Users Download the FREE development environment

2. User install the DE on their scope or PC and develop their UDA

3. Application is then generated and installed on the scope

4. Application then runs on the oscilloscope with “Run License” and test report is generated

eMMC JEDEC spec as Reference

eMCC spec from JESD84-A441

Sequence of SCPI commands to perform Clock timing tests

Summary

Probing Technologies • DRAM BGA probe used when vias are not

accessible • InfiniiSim and PrecisionProbe for

maximizing probe performance

SI Testing/Characterization with Oscilloscope InfiniiScan+

• Read and Write Data for eye diagram measurement

DDR automated compliance app Run automated measurement to save time. Additional features to perform statistical

analysis and margin testing for characterization purposes

• Multi-burst measurement • Customized Derating table • Automated voltage threshold setting • UDA

Memory Oscilloscope Measurement Tool

DDR Compliance Software Packages

(clock, electrical and timing tests)

DDR Fixtures and Probes

9000/90000 series Oscilloscope

InfiniiScan+

InfiniiSim Serial Data Package

DRAM

PrecisionProbe