Synchronous Rectification for Forward Converters · Parasitic Inductance Limitation 1 2 ( ) P P SR...

Synchronous Rectification for Forward Converters

Steve Mappus

www.fairchildsemi.com

1

Agenda

• Synchronous Rectifier (SR) Characteristics

• Forward Converter Transformer Reset Techniques• Forward Converter Transformer Reset Techniques

• Forward Converter SR Gate Drive• Self-DrivenSelf Driven• Hybrid Self-Driven• Control-Driven

• SR Timing Issues

• Primary-Side Trigger + Linear Predict Control (LPC)• Application Example• Measured Data

www.fairchildsemi.com2

Synchronous Rectification (SR)D1

D2

L

CONP NS

CIN

ResetCircuit

Q1

What is Synchronous Rectification?Rectifier Diode Efficiency y• Replacing secondary side rectifiers (D1, D2)

with MOSFETs (Q2, Q3)Benefits of SR

• Higher Efficiency80%

90%

100%

ency

, ηR

ECT

(%)

y(All Converter Losses Neglected)

• Higher Efficiency• Lower output voltage and higher

current applications benefit most• Parallel MOSFETs for higher current

50%

60%

70%

80%

Rec

tifie

r Effi

cie

VF=0.35VVF=0.65VVF=1V

SR Nomenclature• Q2→control SR• Q3→freewheeling SR

OOO IVP × 1

50%1 2 3 4 5 6 7 8 9 10 11 12

Output Voltage (V)


O

FOFOO

OO

IN

O

VVIVIV

VP +

=×+×

==1

1η

Parallel MOSFETs

Diode Thermal Characteristic• Negative temperature coefficient • Temp increase = VF decreasep VF

• Not easily paralleled

SR Thermal CharacteristicP iti t t ffi i t• Positive temperature coefficient

• Temp increase = RDS(ON) increase• T↑, RDS(ON)↑, ID↓, T↓• Automatic current sharingAutomatic current sharing• MOSFETs easily paralleled

Diode vs MOSFET Thermal I-V CharacteristicsDiode vs. MOSFET Thermal I V Characteristics


n = Number parallel MOSFETs

Rectifier I-V Characteristics

OOO IVP=

×==

1η

Rectifier efficiency

O

FOFOOIN

VVIVIVP +×+× 1

η

Schottky Rectifier (MBR4035PT, 35V, 40A)

• Operates in first quadrant (Q1) only

η=86.84%, (VF=0.5V, VO=3.3V)

SR MOSFET (FDMS8670S 30V 42A)SR MOSFET (FDMS8670S, 30V, 42A)

η=97.06%, (VF=0.1V, VO=3.3V)

• >10% improvement, BUT…

• Considers RDS(ON) conduction loss only!

• Operates in third quadrant (Q3)

I

VF

VFRDS(ON)

I


(a) SR MOSFET (b) Schottky Rectifier

IF IF

SR I-V Characteristics

IDDOhmicRegion

ID(A)

VGS4

Q1

VDS

VGS

G

SVGS1

VGS2

VGS3

D

VDS(V)BVDSS

VGS1

VF(BD)

VGS=0V(Body-Diode)

VDS

VGS

D

G SROhmic

VGS3

VGS2SR Operates in Third Quadrant

• Low currentRDS(Q1)=RDS(Q3)

IDVGS

SOhmic

RegionVGS4 • High current, SR body-diode will conduct if:

• For VGS=0V, negative current flows through SR body-diode

)()( BDFONDSD VRI ≥×Q3


body diode

CCM Buck, Diode Rectification

VGS(Q1)

VDS(Q1)

VIN+VF

VIN-VO

VD1

VDS(Q1)VIN

VF

VLV

VIN-VO

CCM ILO

-VOCCM

)1( DIVP OFD1 −××=DVV

IN

O =IDS(Q1)

ID1

• D1 operates in first quadrant only – operation similar to SR

CCM Buck Operational Waveforms

ID1t0 t1 t2


p q y p• Lower voltage converters can not tolerate losses associated with diode rectification

DCM Buck, Diode Rectification

1DCM and CCM Voltage Gain

k=0.01

0.6

0.8

tage

Gai

n k=0.1

k=0 5k≥1

DVV

IN

O =

0.2

0.4Vol

t k 0.5

DCM Buck Operational WaveformsDCM

0 0.2 0.4 0.6 0.8 1

Duty Cycle

DCM Buck Operational Waveforms

2

411

2

DkV

V

IN

O

×++

=TRLk

O ××

=2where,


• D1 operates in first quadrant only – no negative current flow during DCM• Gain is non-linear during DCM operation

Non-Isolated Synchronous Buck

SR Dominant Losses:• Channel conduction

)1(2 DRIP

• Body-Diode conduction

)1()(2 DRIP ONDSOSR(CH) −××=

FtIVPDedicated Controller or Driver

• Reverse Recovery

sBDOFBDSR FtIVP ×××=)(

)()(: 2301 tttttWhere BD −+−=

Dedicated Controller or Driver• Minimize dead time• Anti cross-conduction protection• Optimized gate drive current


SINRRRRSR FVQP ××=)(• Emulate asynchronous operation• Reduce body-diode conduction

SR Body-Diode Reverse Recovery

CGD

CGS

CDS

R

G

D

VF

IF-dIFdt

tCGSRG

RDRV

S

IF

D

t

VR

t0→t1

CGD

CGS

CDS

RG

RDRV

G

D

IDS

IF(ISD)

tA tB

tRR

(a) Ideal Diode – No Reverse Recovery

-dIF

VR

t1→t2 RDRV

S

IDS

D IDS

VF

F

dt

tIRR

QA QB

t1→t2

QA=IFxtAQB=IFxtB

CGD

CGS

CDS

RG

RDRV

G

(b) SR Body Diode “Ideal” Reverse Recovery Characteristic

VR

t0 t1 t2 t3t2→t3

Softness=tA/tB


S IS(QRR) IS(CDS)IS(CGS)IG(b) SR Body-Diode – Ideal Reverse Recovery Characteristic

SR body-diode has high VF and long tRR!

Parallel SR Schottky Diode

Parasitic Inductance Limitation

21

)(

PP

FBDSR

LLVV

dtdi

+

−=

• Typical example:

A 1 A l d

SyncFET™ with Monolithic Schottky• Minimal parasitic inductance

sA

nHVV

dtdi

µ70

525.02.1

=×−

=

• Assume 15A load current

• Current commutation time can exceed

• Minimal parasitic inductance• Low VF

• Using same example parameters:nsA

sAdt 21570

15=

×=

µ

)(600 measuredAdi= ns

AsAdt 25

60015

=×

=µ


Current commutation time can exceed body-diode conduction time

• Order of magnitude improvement

)(600 measuredsdt µ A600

SyncFET™ Reverse Recovery

FDMS7670 vs FDMS7670S SyncFET™• SyncFET™ QRR improvement of ~10%• Previous generation trench technology would show improvement closer to ~50%


• Previous generation trench technology would show improvement closer to ~50%• FDMS7670S, SyncFET™ VF=0.43V, FDMS7670 VF=0.7V

Forward Converter SR

∝

∆

∝

(a) Forward Converter SR (b) Single-Ended Transformer Hysteresis

Forward Converter with SR• Q2, Q3 gate drive challenges similar to synchronous buck

P i t d i l ti dd dditi l ti i i t• Primary to secondary isolation adds additional timing requirement• Single-ended converter topology requires transformer reset• Optimal SR timing is related to transformer reset method


Transformer Reset Techniques

NP NS

RCD Reset

NP NS

Resonant Reset

Q2

CCL NP NS

Active Clamp Reset

Q1 0

VIN

-VR

Q1 0

VIN

-VR

Q2

Q1

0

VIN

-VR

Reset Winding+ Reset Energy Recycled

Resonant Reset+ Reset Energy Recycled

RCD Reset+ Inexpensive Off-Line Solution

Active Clamp Reset+ High Efficiency (ZVT)

+ Simple Off-Line Solution- 50% Duty Cycle Limit (1:1)- Possible Core Saturation- Transformer Structure- Q1 Hard Switched

+ Fewest Components+ Simple Telecom Solution- Repeatable Design Difficult- High VDS Stress- Not for Off-Line Power

N t S it bl f S lf D i SR

+ >50% Duty cycle Possible- Reset Energy Dissipated- Q1 Hard Switched

+ Higher Frequency Operation+ Lowest Vds Stress+ Off-Line and Telecom+ SR Gate Drive- Q1, Q2 Gate Drive

Hi h C t- Not Suitable for Self-Driven SR- Q1 Hard Switched

- Higher Cost- Limited PWM and/or DriverChoices


Reset Method Impacts Self-Driven SR Gate Drive

SR Gate Drive Methods

1. Self-Driven

2. Hybrid Self-Driven

3. Control-Driven


Self-Driven SR

Self-Driven SR• SR gate drive derived from transformerSR gate drive derived from transformer

(as shown) or output inductor• Advantages

• Simple – no timing issues!Self-Driven RCD Reset Waveforms

• SR gate charge recycled to load• High efficiency with minimal components• Best applied to active clamp forward (D and 1-D)


Self-Driven SR (Continued)

Self-Driven SR• Disadvantages RDS(ON) versus VGS for Disadvantages

• SR gate drive is not regulated• Not compatible with all reset techniques• Difficult to optimize VGS and RDS(ON) when VIN > 2:1

DS(ON) GSFDMS7670AS, SyncFET™

( )

• RDS(ON) can vary by 10% or more• No control of freewheeling SR during start-up or light load

DCM operation


Hybrid Self-Driven SRLO

CO

C

ROQ3VC VS

Q2

CIN

Q1VIN

1 5VDD

FAN3100COUT

SBiasPWM

1

2

3 4

5VDD

GND

IN-IN+

FAN3100COUT

PBiasU1

U2R1

D1 1

2

3 4

5GND

IN-IN+RC1

RC2

C1

C2

R2

D2

Hybrid Self-Driven SR

RCD Forward Converter

Hybrid Self Driven SR• Forward converters with resonant reset signals (ie, RCD or Resonant Reset)• Control SR (Q2) is self-driven• Freewheeling SR (Q3) gate-drive derived from primary-side inverted PWM


• Q1 to Q3, primary to secondary timing is critical• Q2 to Q3 timing issues similar to non-isolated synchronous buck

Hybrid Self-Driven SR TimingLO

CO

CIN

RO

V

Q3

FAN3100CPBias

VC VS

U1

PWM

RC1 RC2

Q2Q1

VIN

1

2

3 4

5VDD

GND

IN-IN+

FAN3100COUT

SBiasPWM

1

2

3 4

5VDD

GND

IN-IN+

FAN3100COUT

PBias

RC1

U2R1

C1

D1

R2

DV

PWM

PWM

RC2C2

D2

VGS(Q2)

V

VGS(Q1)

Freewheeling SR Timing Adjustments• Split primary PWM signal• Delay primary PWM rising edge t0→t2 tRC1

VGS(Q3)

VDS(Q1)

VCVIN

Delay primary PWM rising edge, t0→t2, tRC1

• Delay and invert secondary-side Q3 gate drive• Apply tRC2 so that Q3 turns on just after VS goes

negative

VS

VDS(Q2)


• Adjust t0→t2 > t3→t4 so that Q2 is OFF prior to Q3 ON (no cross-conduction for all line & load)VDS(Q3)

t0 t1t2 t3t4t5

Hybrid Self-Driven SR

Advantages• Improvement over self-driven SR• Reduce body-diode conduction• Regulate freewheeling SR gate drive• Best applied to RCD or resonant reset forward converters

Disadvantages• Non-adaptive to varying component or CCM/DCM mode change

C t l SR t d i t l t d (V ti l t V )• Control SR gate drive not regulated (VGS proportional to VIN)• Timing adjustments dependant upon R and C tolerance and duty cycle, D• Can not be used if primary PWM includes internal gate drive• Can not control freewheeling SR against negative current flow (DCM, pre-biased loads)g g g ( , p )

Full control of both SR MOSFETs only achievable using Control-Driven SR


Full control of both SR MOSFETs only achievable using Control Driven SR

Control-Driven SR

LO

CO RO

1

2

5VDD

GND

IN-IN+

FAN3100COUT

PBias U1Q1a

D2

D1

Q3VPVD

Q2

SBias1 8

VIN

PWM

3 4ININ+

Q1b

SBias1

2

3 6

U2FAN3225C

7

4 5+-

+-

• Both SR MOSFETs are controlled by primary side PWM

2 Switch Forward Desired SR Waveforms2 Switch Forward Converter (Delays Not Shown)

• Both SR MOSFETs are controlled by primary-side PWM• General purpose low-side gate drivers or “smart-drivers” often used• Offers full SR control during start-up, light-load, OCP, pre-biased output• SR gate drive is regulated and independent of transformer reset method


g g p• Q3 timing adjustment similar to previous Hybrid Self-Driven example• RC Delay also needed for Q2 SR

Control-Driven SR Timing DelaysSecondary-Side Control

SR secondary can be driven directly by PWMSecondary to primary power stage propagation delay (solid arrows)y p y p g p p g y ( )

• PWM to primary side gate drive and power transformer

Secondary to primary SR propagation delay (dashed arrows)• Power stage and SR delay times are often not equal


• SR gate drive naturally leads primary MOSFET gate drive• Timing delay normally added in this path

Control-Driven SR Timing DelaysPrimary-Side Control

Primary to secondary power stage propagation delay (solid arrows)• PWM to primary-side gate drive and power transformer• Delay normally added in this path

Primary to secondary SR propagation delay (dashed arrows)• PWM to pulse transformer and SR MOSFET gate driver


• Often need to advance the SR signal (impossible)

Optimal timing adjustment requires primary and secondary sensing

Control-Driven SRPrimary-Side Triggering

LO

CO

Q1a

D2 Q3

VIN

+

FAN6210 LM

VO

+

R1

DB

Q2

CO

Q1b

D2D1

Q3

RDLY DET

XP GND

SIN

1

2

3

4

8

7

6

5

XN SOUT

VDD

LM

R2

R3 R4

DB

DZ

LPC1 SR1

SN

1

2

3

8

7

6

LPC2 GND

SR2

FAN6206

PWM

DZ

Primary SensingA i l d d PWM i t (SIN)

SP VDD4 5

• Any single-ended PWM input (SIN)• Transformer reset voltage (DET)

Secondary Sensing• Q2 drain so rce oltage (LPC1)


• Q2 drain-source voltage (LPC1)• Q3 drain-source voltage (LPC2)

Primary-Side Triggering Light Load (CCM)

FAN6210 Waveforms - Light Load (CCM), XP Triggered by DET

• XP rising edge triggers turn on for each SR• XP rising edge triggers turn-on for each SR• XN rising edge triggers turn-off for each SR• XN triggered by PWM input (SIN) rising and falling edges• XP control SR turn-on triggered by delayed PWM output (SOUT)


gg y y p ( )• XP freewheeling SR turn-on normally triggered by DET (shown)

Primary-Side TriggeringFull Load (CCM)

SIN

SOUT300ns

100ns

Programmable delay 50ns

300ns

Programmable delay

700ns

Programmable delay

700nsXP

XN

50ns

50ns300ns

50ns300ns

50ns300ns

Programmable delay

Gate drive for control SR Gate drive for Freewheeling SR

DET

FAN6210 Waveforms - Heavy Load (CCM), XP Triggered by XN

• XP rising edge triggers turn on for each SR• XP rising edge triggers turn-on for each SR• XN rising edge triggers turn-off for each SR• XN triggered by PWM input (SIN) rising and falling edges• XP control SR turn-on triggered by delayed PWM output (SOUT)


gg y y p ( )• XP freewheeling SR turn-on normally triggered by DET or XN (shown)

• XP can never trigger while XN is HIGH – prevents SR cross-conduction

SR Negative Current IssuesLO

CO

Q1

ROVIN PWM Q2

INEG

CIN

RO

IO

Forward SR• Q2 blocks INEG when Q3 turns off (Q2 off)• INEG charges SR COSS during Q3 off

Synchronous Buck• Q1 drain clamped to DC source• Q2 VDS clamped to DC source through Q1


• BVDSS stress from switching INEG

• SR switching adjustment required (as shown)

body-diode• Negative inductor current ok for VDS

Linear Predict Control (LPC)LO

COQ3

VO

+

R1

R2

PowerStage

(Primary)

Q2

R2

R3 R4

( y)

SP VDD

LPC1 SR1

SN

1

2

3

4

8

7

6

5

LPC2 GND

SR2

FAN6206

FAN6210(XP, XN)( )

VVRatio

V OLPC

O 5.011

2 −<<

• LPC Function is used to turn off Q3 before ILO<0A during DCM operation• During CCM SR gate drive controlled by SP(XP) and SN(XN)• SN signal follows PWM signal and can not turn off Q3 before ILO<0• Both SR V monitored by resistor dividers


• Both SR VDS monitored by resistor dividers• Solves Problem of Negative SR Current

Primary-Side Triggering (DCM)


FAN6206 Waveforms - Light Load (DCM)

Primary-Side Triggering

Advantages• Easily implements correct primary to secondary SR timing for forward converters• No RC timing adjustments required• Compatible with all forward transformer reset techniques including 2 switch forward• Can be used with any single-ended PWM controller

G d f i di bl f h li SR d i f D 10%• Green mode function disables freewheeling SR gate drive for D<10%• Operates in CCM and DCM• Freewheeling SR control prevents negative current flow

Be Aware of• SR Gate drive current limited to 0.7A/1A (source/sink)

• Use FAN3xxx series low-side gate drivers for driving higher gate chargeg g g g g• Internal fixed delays result in longer body-diode conduction times at higher frequency

• For low output voltage converters SyncFET can help


Primary-Side TriggeringApplication Circuit Specifications

INPUTI t V lt 90V V 264VInput Voltage 90VAC<VIN(AC)<264VAC

Line Frequency 47Hz<FLINE<63HzPFC Output 310VDC<VBULK<380VDC

OUTPUTOutput Voltage 12VDC

Output Power 300WOutput Power 300WLoad Current 25ASwitching Frequency 65kHz

Intended Application: PC Power (Computing)


Why 65kHz Operation?

dBuV

90

100Fundamental

(66kHz)

dBuV

90

100Fundamental

(100kHz)

60

70

802nd harmonic

(132kHz)

60

70

80

EN 55022 QP

2nd harmonic(200kHz)

40

50

40

50

EN 55022 QP

EN 55022 AV

10

20

30

10

20

30

150k 200k 300k 500k 1M100k 150k 200k 300k 500k 1M100k

Frequency spectrum with 66kHz operation Frequency spectrum with 100kHz operation


• Lower EMI• Trade Off: EMI filter size versus transformer size

Primary-Side TriggeringApplication Validation Circuit


Measured WaveformsSteady State and LPC Function

Control SR Gate

Freewheeling

Freewheeling SRVDS

XP (SP)

XN (SN)

SR Gate

LPC

S S S i iSP and SN control SR switching

LPC function during DCM operation

Freewheeling SR G

PWMIN (SIN)

300ns

XNXP

SR Gate

XP, XN


SOUT

SIN→SOUT, 300ns fixed turn-on delay SIN→SOUT, 100ns fixed turn-off delay

Measured WaveformsSR Dead-Time, Load Transient

PWMIN (SIN)

XNXPXP, XN

Freewheeling SR Gate

400ns

Control SR Gate

FW SR↓→Control SR↑, 500ns dead-time FW SR↑→Control SR↓, 400ns dead-time


0A→10A load transient 10A→0A load transient

Measured WaveformsStart-Up, OCP, Green Mode

VOUT

SOUT

ZOOM

VOUT=8.8V

OUT

SOUT

Control SR

Freewheeling SR

SR control during start-up FW SR control during start-up

Freewheeling SR

XP, XN

PWMIN(SIN)

D=7.8%

Control SRVDS

Freewheeling SRVDS


10A→64A overload transient Green mode function enabled for D<10%

Measured EfficiencySchottky vs SR

95%

SR Efficiency Comparison(115VAC Input, 12VDC Output, 300W, 12V/25A Output)

90%

Primary-Side Trigger Control-Driven SR (FDP5800)

Schottky Rectifiers (FYP2006DN)

85%

Effic

ienc

y (%

)

80%80%10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

Output Power (%)300W=100%


Summary

• Self-Driven SR• Best for active clamp forward where IO(MIN) > ILO/2 (BCM)• SR gate drive independent from primary controlSR gate drive independent from primary control

• Hybrid Self-Driven SR• Performance improvement over self-driven SRPerformance improvement over self driven SR

• Control Driven SR• SR timing is criticalSR timing is critical• Difficult to implement discretely

• FAN6210+FAN6206• FAN6210+FAN6206 • Simplifies SR timing • Freewheeling SR control during DCM operation


Evaluate all SR solutions under steady state and dynamic test conditions!

Questions?

THANK YOU!


References

1. “FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual y y ( ) ggForward Converter”, Datasheet, Fairchild Semiconductor, March 2010.

2. “FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter”, Datasheet, Fairchild Semiconductor, April 2010.

3 “AN 6206 Primary Side Synchronous Rectifier (SR) Trigger Solution for Dual3. AN-6206 — Primary-Side Synchronous Rectifier (SR) Trigger Solution for Dual-Forward Converter”, Fairchild Semiconductor, April 2010.


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Synchronous Rectification for Forward Converters · Parasitic Inductance Limitation 1 2 ( ) P P SR...

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Transcript of Synchronous Rectification for Forward Converters · Parasitic Inductance Limitation 1 2 ( ) P P SR...