Symbolic Trajectory Evaluation (STE) · • Communication protocols • High level (abstract)...
Transcript of Symbolic Trajectory Evaluation (STE) · • Communication protocols • High level (abstract)...
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Symbolic Trajectory Evaluation (STE):Automatic Refinement and Vacuity Detection
Orna GrumbergTechnion, Israel
Marktoberdort 2007
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Agenda
• Model checking• Symbolic Trajectory Evaluation• Basic Concepts• Automatic Refinement for STE• Vacuity in STE
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System VerificationGiven a (hardware or software) system and a specification,does the system satisfy the specification?
Not decidable!
We restrict the problem to a decidable one:• Finite-state reactive systems• Propositional temporal logics
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Finite state systems
• hardware designs• Communication protocols• High level (abstract) description of
non finite state systems
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Properties in temporal logic
• mutual exclusion: always ¬( cs1 ∧ cs2)
• non starvation: always (request ⇒ eventually grant)
• communication protocols: (¬ get-message) until send-message
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Model of a systemKripke structure / transition system
a,b a
ab,c
c
a,c a,bb
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M=<S, I, R, L>
• S - Set of states. • I ⊆ S - Initial states.• R ⊆ S x S - Total transition relation.• L: S→ 2AP - Labeling function.AP – Set of atomic propositions
Model of systems
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π=s0s1s2... is a path in M from s iffs = s0 and for every i≥0: (si,si+1)∈R
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Propositional temporal logic
AP – a set of atomic propositionsTemporal operators:GpFpXppUqPath quantifiers: A for all path
E there exists a path
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Model Checking
An efficient procedure that receives:A finite-state model describing a systemA temporal logic formula describing a property
It returns yes, if the system has the propertyno + Counterexample, otherwise
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Model Checking
Emerging as an industrial standard tool for hardware design: Intel, IBM, Cadence, Synopsys,…
Recently applied successfully also for software verification: NASA, Microsoft, ETH, CMU, …
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Model checking
A basic operation: Image computation
Given a set of states Q, Image(Q) returns the set of successors of Q
Image(Q) = { s’ | ∃s [ R(s,s’) ∧Q(s)]}
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Model checking AGp on M
• Starting from the initial states of M, iteratively compute the set of successors.
• At each iteration check whether it reached a state which satisfies ¬p.– If so, declare a failure.
• Stop when no new states are found.– Result: the set of reachable states.
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Reachability + checking AG a
a,b a
ab,c
c
a,c a,bb
Reach = New = I = { 1, 2 }
1 2
3 4
56 7
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Return: M |≠ AG a
a,b a
ab,c
c
a,c a,bb
Failure: New ⊄ Sa
1 2
3 4
56 7
8
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Reachability + checking AG (a∨b)
a,b a
ab,c
c
a,c a,bb
Reach = New = I = { 1, 2 }
1 2
3 4
56 7
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Return: Reach, M |= AG (a∨b)
a,b a
ab,c
c
a,c a,bb
Reach = {1, 2, 3, 4, 5, 6} New = emptyset
1 2
3 4
56 7
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Main limitation:
The state explosion problem:Model checking is efficient in time but
suffers from high space requirements:
The number of states in the system model grows exponentially with the number of variablesthe number of components in the system
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Symbolic model checking
A solution to the state explosion problem whichuses Binary Decision Diagrams ( BDDs )to represent the model and sets of states.
• Can handle systems with hundreds of Boolean variables
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Binary decision diagrams (BDDs)
• Data structure for representing Boolean functions
• Often concise in memory• Canonical representation• Most Boolean operations on BDDs can
be done in polynomial time in the BDD size
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BDDs in model checking
• Every set A can be represented by its characteristic function
1 if u∈AfA(u) = 0 if u ∉ A
• If the elements of A are encoded by sequences over {0,1}n then fA is a Booleanfunction and can be represented by a BDD
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Representing a model with BDDs• Assume that states in model M are
encoded by {0,1}n and described by Boolean variables v1...vn
• Reach, New can be represented by BDDsover v1...vn
• R (a set of pairs of states (s,s’) ) can be represented by a BDD over v1...vn v1’...vn’
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Example: representing a model with BDDs
S = { s1, s2, s3 }R = { (s1,s2), (s2,s2), (s3,s1) }
State encoding:s1: v1v2=00 s2: v1v2=01 s3: v1v2=11
For A = {s1, s2} the Boolean formula representing A:
fA(v1,v2) = (¬v1 ∧ ¬v2) ∨ (¬v1 ∧v2) = ¬v1
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fR(v1, v2, v’1, v’2 ) =(¬v1 ∧ ¬v2 ∧ ¬v’1 ∧v’2) ∨(¬v1 ∧ v2 ∧ ¬v’1 ∧v’2) ∨(v1 ∧ v2 ∧ ¬v’1 ∧ ¬v’2 )
fA and fR can be represented by BDDs.
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ab
c
10
c
1 1
bc
1 1
b
ccb
0 11 0
ab
cc
1 1 10
c c c
BDD for f(a,b,c) = (a ∧ b ) ∨ c
Decision tree
ab
c
10
BDD
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SAT-based model checkingAnother solution to the state explosion problem
• Translates the model and the specification to a propositional formula
• Uses efficient tools for solving the satisfiability problem
Since the satisfiability problem is NP-complete, SAT solvers are based on heuristics.
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SAT solvers
• Using heuristics, SAT tools can solve very large problems fast
• They can handle systems with thousands variables
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Bounded model checkingMost commonly used SAT-based model checking
For checking AGp:• Unwind the model for k levels, i.e.,
construct all computation of length k• If a state satisfying ¬p is encountered,
then produce a counter example
The method is suitable for falsification, not verification
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SAT-based model checking
• Can also handle general temporal logicspecifications
• Can be used for verification by using methods such as induction and interpolation.
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Bounded model checking in detail
• Construct a formula fM,k describing all possible computations of M of length k
• Construct a formula fϕ,k expressing that ϕ=EF¬p holds within k computation steps
• Check whether f = fM,k ∧ fϕ,k is satisfiable
If f is satisfiable then M |≠ AGpThe satisfying assignment is a counterexample
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Example – shift registerShift register of 3 bits: <x, y, z>Transition relation:R(x,y,z,x’,y’,z’) = x’=y ∧ y’=z ∧ z’=1
|____|error
Initial condition:I(x,y,z) = x=0 ∨ y=0 ∨ z=0
Specification: AG ( x=0 ∨ y=0 ∨ z=0)
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Propositional formula for k=2
fM = (x0=0 ∨ y0=0 ∨ z0=0) ∧(x1=y0 ∧ y1=z0 ∧ z1=1) ∧(x2=y1 ∧ y2=z1 ∧ z2=1)
fϕ = Vi=0,..2 (xi=1 ∧ yi=1 ∧ zi=1)
Satisfying assignment: 101 011 111This is a counter example!
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A remark
In order to describe a computation of length k by a propositional formula we need k copies of the state variables.
With BDDs we use only two copies of current and next states.
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Abstraction-Refinement
Reconstruct
Refine
Concrete model
Abstract Verify
Abstract model pass
fail
Refined model
A successful approach to deal with the state explosion problem in model checking
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Abstraction-refinement (cont.)
MA - abstract model MC - concrete model• 2-valued abstraction
MA |= ϕ ⇒ Mc |= ϕMA |≠ ϕ ⇒ MC ?
• 3-valued abstractionMA |= ϕ ⇒ Mc |= ϕMA |≠ ϕ ⇒ Mc |≠ ϕMA ? ⇒ Mc ?
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Agenda
• Model checking• Symbolic Trajectory Evaluation• Basic Concepts• Automatic Refinement for STE• Vacuity in STE
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Symbolic Trajectory Evaluation(STE)
A powerful technique for hardware model checking that can handle
• much larger hardware designs • relatively simple specification language
Widely used in industry, e.g., Intel, Freescale
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STE is given
• A circuit M• A specification A ⇒ C, where
– Antecedent A imposes constraints on M– Consequent C imposes requirements on M
A and C are formulas in a restricted temporal logic (called TEL)
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STE• Works on the gate-level representation
of the circuit• Combines symbolic simulation and
abstraction
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Current STE• Automatically constructs an abstract
model for M, based on A (M×A)• Checks whether M×A ² C
Return:– Pass: M ² A ⇒ C– Fail + counterexample– Undecided: refinement is neededThis is a form of 3-valued abstraction
• Manually refines A (and thus also M×A)
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Agenda
• Model checking• Symbolic Trajectory Evaluation• Basic Concepts• Automatic Refinement for STE• Vacuity in STE
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Modeling a circuit
• A Circuit M is described as a graph whose nodes n are inputs, gates, and latches
• We refer to node n at different times t
In fact, we look at an unwinding of the circuit for k times
• k is determined by A ⇒ C
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Modeling a circuit (cont.)
• The value of an input node at time t is nondeterministic: 0 or 1
• The value of a gate node at time t depends on the values of its source nodes at time t
• The value of a latch node at time t depends on the values of its source nodes at time t and t-1
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1
1
Time=0
1
0
00
0
Time=1
Example: a circuit
in1
in2n1 n2
n3
0 0
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Simulation Based Verification
• Assigns values to the inputs of the modelover time (as in the example)
• Compares the output values to the expected ones according to the specification
• Main drawback: the model is verified only for those specific combinations of inputs that were tested
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Symbolic Simulation• Assigns the inputs of the model with
Symbolic Variables over {0,1}
• Checks all possible combinations of inputs at once
• Main drawback: representations of such Boolean expressions (e.g. by BDDs) are exponential in the number of inputs
xy x ∧ y
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STE solution
• Adds an “unknown’’ value X, in addition to 0, 1, and symbolic variables
• Needs also an “over-constrained”value ⊥
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4-valued latticeTo describe values of nodes, STE uses:
0,1, X, and ⊥• (n,t) has value X when the value of n
at time t is unknown• (n,t) has value ⊥ when the value of n
at time t is over-constrained
0
X
⊥1 0 b x 1 b x ⊥ b 0 ⊥ b 1
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Operations on lattice elements
• Meet: a 6 b is the greatest lower bound of a and b
X61=1 X60=0 061=⊥ …
• Join: a 7 b is the least upper bound
0
X
⊥1
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Lattice Semantics
• X is used to obtain abstraction
• ⊥ is used to denote a contradictionbetween a circuit behavior and the constraints imposed by the antecedent A
• Note: the values of concrete circuit node are only 0 and 1.
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Quaternary operations
• X ∨ 1 = 1 X ∨ 0 = X X ∨ X = X• X ∧ 1 = X X ∧ 0 = 0 X ∧ X = X
• ¬X = X
• Any Boolean expression containing ⊥has the value ⊥
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Symbolic execution
• STE combines abstraction with symbolic simulation to represent multiple executions at once
• Given a set of symbolic variables V, the nodes of the circuit are mapped to symbolic expressions over V∪{0,1,X,⊥}
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v2?1:XTime=0Time=1
10
n3n2n1in2in1Time
Example: symbolic abstract execution
in1
in2n1 n2
n3
v1 X v1?1:X X X
X v2 v2?1:X v1?1:X
v1
X
v1?1:X X XX
v2
v1 ∧ v2?1:X
v1∧v2?1:X
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The difference between X and v∈V
• X ∧ ¬X = X• v ∧ ¬v = false
• Different occurrences of X do not necessarily represent the same value (“unknow”)
• All occurrences of v represent the same value
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• Each line is a symbolic state• Trajectory: sequence of states,
compatible with the behavior of the circuit
10
n3n2n1in2in1Timev1 X v1?1:X X X
X v2 v2?1:X v1?1:X v1∧v2?1:X
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Implementation issues
• The value of each node (n,t) is a function from V to {0,1, X, ⊥ }
• BDD representation – Dual railTwo Boolean functions:fn,t
1 : V → { 0,1 }fn,t
0 : V → { 0,1 }
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Dual rail
For a specific assignment to V• fn,t
1(V) ∧ ¬fn,t0(V) represents 1 for (n,t)
( fn,t1 , fn,t
0 ) (n,t)(1,0) 1(0,1) 0(0,0) X(1,1) ⊥
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STE / model checking
• STE holds local view of the system:for each (n,t) separately
• Model checking holds global view:A state – values of all nodes at time t
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Trajectory Evaluation Logic (TEL)
Defined recursively over V, wherep is a Boolean expression over Vn is a nodef, f1, f2 are TEL formulasN is the next-time operator
(n is p) (p → f)
(f1∧f2) (N f)
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Example: TEL formula
f = (in1 is v1) ∧N (in2 is v2) ∧ N2 (v1∧v2 → (n3 is 0))
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Semantics of TEL formulas
TEL formulas are interpreted over• Symbolic execution σ over V, and• assignment φ : V → {0,1}
• [φ,σ ² f ] ∈ {1, 0, X, ⊥ }
Note: (φ,σ) represents an (abstract) execution,i.e., a series of expressions, each over {0,1,X,⊥}
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v1∧v2?1:Xv1?1:Xv2?1:XV2X1XXv1?1:XXV10n3n2n1in2in1Time
The same φ is applied to f and to σf = N (v1∧v2→ (n3 is 1))
Example: TEL semantics
For every φ, [φ,σ ² f ] = 1
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v1∧v2?1:Xv1?1:Xv2?1:XV2X1XXv1?1:XXV10
n3n2n1in2in1Time
f = N (n3 is (v1∧v2?1:0))
Example: TEL semantics
For φ(v1∧v2)=0, [φ,σ ² f ] = X
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TEL Semantics
• For every TEL formula f,[φ,σ ² f] = ⊥ iff ∃i,n: φ(σ) (i)(n) = ⊥
A sequence that contains ⊥ does not satisfy any formula
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TEL semantics (cont.)(σ does not contains ⊥)
Note: φ(p) ∈ {0,1}
• [φ,σ ² (n is p)] = 1 iff φ(σ)(0)(n) = φ(p)
• [φ,σ ² (n is p)] = 0 iffφ(σ)(0)(n) ∈ {0,1} and φ(σ)(0)(n) ≠ φ(p)
• [φ,σ ² (n is p)] = X iff φ(σ)(0)(n) = X
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TEL semantics (cont.)
• [φ,σ ² (f1∧f2) ] = [φ,σ ² f1] ∧ [φ,σ ² f2]
• [φ,σ ² (p → f) ] = φ(¬p) ∨ [φ,σ ² f]
• [φ,σ ² (N f) ] = [ φ,σ1 ² f ]
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TEL semantics (cont.)
[σ ² f ] = 0 iff for some φ, [φ,σ ² f]=0
[σ ² f ] = X iff for all φ, [φ,σ ² f] ≠ 0 andfor some φ, [φ,σ ² f]=X
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TEL semantics (cont.)
[σ ² f ] = 1 iff for all φ, [φ,σ ² f] ∉ {0,X}and for some φ, [φ,σ ² f]=1
[σ ² f ] = ⊥ iff for all φ, [φ,σ ² f]= ⊥
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Back to STE…
Recall that our goal is to check whetherM ² A ⇒ C
where A imposes constraints on M and C imposes requirements
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M×A: Abstraction of M derived by A
The defining trajectory of M and A, denoted M×A, is defined as follows:
• M×A is a symbolic execution of M that satisfies A
• For every symbolic execution σ of M [σ ² A]=1 ↔ σ b M×A
n3,t
σM×A
n4,tn2,tn1,t1 X 0 X
1/⊥ 0/⊥
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M×A (cont.)
• [Seger&Bryant] show that every circuit M and TEL formula f has such M×f
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M×A (cont.)
• M×A is the abstraction of all executions of M that satisfy A and therefore should also satisfy C
• If M×A satisfies C then all executions that satisfy A also satisfy C
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Checking M ² A⇒C with STE
• Compute the defining trajectory M×A of Mand A
• Compute the truth value of [M×A ² C]– [M×A ² C] = 1 → Pass– [M×A ² C] = 0 → Fail– [M×A ² C] = X → Undecided
• The size of M×A (as described with BDDs) is proportional to A, not to M !
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10
n3n2n1in2in1Time
Example: M×AA =(in1 is v1) ∧ N (in2 is v2) C = N (n3 is 1)
in1
in2n1 n2
n3
v1
X
v1 X
v1?1:X XX
v1?1:X X XX v2
v2
X
v2?1:X v1?1:X
v2?1:X
v1∧v2?1:X
v1∧v2?1:X
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Undecided results
A = (in1 is v1) ∧ N (in2 is v2)C = N (n3 is 1)
In M×A the value of (n3,1) is v1∧v2?1:XC requires (n3,1) to be 1
For φ(v1∧v2)=0, [φ, M×A ² C ] = X
When v1∧v2 is 0, STE results in “undecided” for (n3,1) and thus refinement of A is needed
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Agenda
• Model checking• Symbolic Trajectory Evaluation• Basic Concepts• Automatic Refinement for STE• Vacuity in STE
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Our Automatic Refinement Methodology
• Choose for refinement a set Iref of inputsat specific times that do not appear in A
• For each (n,t) ∈ Iref , vn,t is a freshvariable, not in V
• The refined antecedent is:
Anew = A ∧ Λ(n,t)∈Iref Nt(n is vn,t)
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Refinement (cont.)
Anew has the property that:
M ² A ⇒ C ⇔ M ² Anew ⇒ C
Here we refer to the value of A⇒C / Anew⇒Cover the concrete behaviors of M
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Goal:Add a small number of constraints to A,keeping M×A relatively small, whileeliminating as many undecided results aspossible
Remark: Eliminating only some of theundecided results may still reveal “fail”.For “pass”, all of them need to be eliminated
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Choose a refinement goal
We choose one refinement goal (root,tt)• A node that appears in the consequent C• Truth value is X• Has minimal t and depends on minimal
number of inputs
We will examine at once all executions in which (root,tt) is undecided
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Choosing Iref for (root,tt)
Naïve (syntactic) solution:Choose all (n,t) from which (root,tt) is
reachable in the unwound graph of the circuit
Will guarantee elimination of all undecided results for (root,tt)
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XX
XX
X
1
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Better (semantic) solution• Identify those (n,t) that for some assignment are on a path to (root,tt) along which all nodes are X
• Iref is the subset of the above, where n is an input
• Will still guarantee elimination of all undecided results for (root,tt)
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Heuristics for smaller Iref
Choose a subset of Iref based oncircuit topology and functionality, such as:
• Prefer inputs that influence (root,tt) along several paths
• Give priority to control nodes over data nodes
• And more
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Experimental Results for Automatic Refinement
We implemented our automatic refinement within the Intel’s STE tool Forte.
We ran it on two nontrivial different circuits:• Intel’s Content Addressable Memory (CAM)
– 1152 latches, 83 inputs and 5064 gates• IBM’s Calculator design
– 2781 latches, 157 inputs and 56960 gates
We limited the number of added constraints at each refinement iteration to 1
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Some more implementation issues
• Recall that the value of each node (n,t) is a function from V to {0,1, X, ⊥ }
• BDD representation – Dual railTwo Boolean functions:fn,t
1 : V → { 0,1 }fn,t
0 : V → { 0,1
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Dual rail
( fn,t1 , fn,t
0 ) (n,t)(1,0) 1(0,1) 0(0,0) X(1,1) ⊥
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Notation:
• ( fn,t1 , fn,t
0 ) represents (n,t) in MxA
• ( gn,t1 , gn,t
0 ) represents (n,t) in C
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Symbolic counterexample
V(n,t)∈C [ ( gn,t1 ∧ ¬fn,t
1 ∧ fn,t0 ) ∨
( gn,t0 ∧ fn,t
1 ∧ ¬fn,t0 ) ]
Note: C is never ⊥
• Represents all assignments to V in which for some node (n,t), MxA and C do not agree on 0/1
• User needs to correct either the circuit or the specification
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Symbolic incomplete trace
V(n,t)∈C [ ( gn,t1 ∨ gn,t
0 ) ∧( ¬fn,t
1 ∧ ¬fn,t0 ) ]
• Represents all assignments to V in which for some node (n,t), C imposes some requirement (0 or 1) but MxA is X
• Automatic/manual refinement is needed
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Semantic Iref can be computed in a similar manner
XX
XX
X
1
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How do we get ⊥ in STE ?
in1
in2n1
n2in3
n3 n6
A = in1 is 0 ∧ in2 is u ∧ in3 is 0 ∧ n3 is 1
n4
Antecedent failure
n5
0
0
uu
¬u
0 6 1= ⊥⊥
⊥
0
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Antecedent failure is the case in which, for some assignment, MxA contains ⊥
• Can only occur when the antecedent imposes a constraint on internal node
• Reflects contradiction between– Antecedent constraints– Circuit execution
• In our work, such assignments are ignored during verification
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Agenda
• Model checking• Symbolic Trajectory Evaluation• Basic Concepts• Automatic Refinement for STE• Vacuity in STE
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Vacuity in model checking
Example:M |= AG (request → F granted )
holds vacuously if• request is always false or • granted is always true
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Vacuous Results
in1
in2n1
n2in3
n3 n6
A = in1 is 0 ∧ in3 is v ∧ n3 is 1C = N(n6 is 1)
n4
Counterexample for v=0. Spurious?
n5
0
v
X
XX61=1
1v
v v?1:X
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Vacuous Results - Refined
in1
in2n1
n2in3
n3 n6
A = in1 is 0 ∧ in2 is u ∧ in3 is 0 ∧ n3 is 1
n4
The counterexample is spurious!
n5
0
0
uu
¬u
0 6 1= ⊥⊥
⊥
0
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The Vacuity ProblemGiven an STE assertion A ⇒ C, an assignment φ to V
and a circuit M:
• A ⇒ C is vacuous in M under φ if
– there is no concrete execution of M that satisfies φ(A)
OR– C under φ imposes no requirements. For example, if C=(v1->(n is v2)) then for
assignments in which v1=0, C imposes no requirement
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The Vacuity Problem (cont.)
• A ⇒ C fails vacuously in M if – [M×A ² C] = 0AND
– for all assignments φ so that [φ ,M×A ² C] = 0, A ⇒ C is vacuous in M
under φ
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The Vacuity Problem (cont.)
• A ⇒ C passes vacuously in M if – [M×A ² C] = 1AND– for all assignments φ so that
[φ ,M×A ² C] = 1, A ⇒ C is vacuous in M under φ
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Observation
• Vacuity can only occur when A contains constraints on internal nodes (gates, latches)
• Antecedent failure is an explicit vacuity. Our goal is to reveal hidden vacuity.
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Detecting (non-)vacuity
Given a circuit M, an STE assertion A⇒C and an STE result (either fail or pass), our purpose is to find an assignment φ to V and an execution of M that satisfies all the constraints in φ(A)
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Detecting (non-)vacuity
In Addition:• In case of pass, φ should also impose
requirements in C
• In case of fail, the execution should constitute a counterexample
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Detecting (non-)vacuity
We developed two different algorithms for detecting vacuity / non-vacuity:
• An algorithm that uses BMC and runs on the concrete circuit.
• An algorithm that uses STE and automatic refinement.
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Detecting (non-)vacuity using BMC
1. Transform A into an LTL formula2. Encode M and A as a BMC formula3. In case of fail STE result, add the
counterexample as a constraint to the BMC formula
4. In case of pass STE result, add constraints to enforce at least one requirement in C
5. Return “vacuous” if and only if the resulting formula is unsatisfiable
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Detecting (non-)vacuity using BMC
Main drawback: no abstraction is used
We would like to detect vacuity while utilizing STE abstraction
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Detecting (non-)vacuity using STE• Ain ⇒ Aout is a new STE assertion, where
– Ain includes all constraints on inputs in A, and
– Aout includes the constraints on internalnodes in A
• Run STE on Ain ⇒ Aout . Let Φ denote the set of assignments to V for which [M×Ain ² Aout]=1
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Detecting (non-)vacuity using STE(cont.)
1. In case [M×A ² C]=1: If there is an assignment in Φ that imposes a requirement in C, return “pass non vacuously”
2. In case [M×A ² C]=0: If there exists φ∈Φ and φ’ so that [φ’,M×A ² C]=0 and (φ.φ’ is satisfiable) , return “fail non vacuously”
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Detecting (non-)vacuity using STE(cont.)
3. If there is no φ so that [φ, M×Ain ²Aout]=X, return “vacuous”
4. Refine Ain ⇒ Aout and return to step 2
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Summary
What makes STE successful?
The combination of: • Symbolic simulation• Abstraction• Local (dual rail) BDD implementation
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Conclusion and future work
Generalized STE (GSTE) extends STE by providing a specification language which is as expressive as ω-regular languages.
Other directions: • automatic refinement for GSTE (FMCAD’07)• Vacuity definition and detection for GSTE• SAT-based STE (ATVA 2007)• New specification language for GSTE (FMCAD’07)
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ReferencesModel Checking• Model checking
E. Clarke, O. Grumberg, D. Peled, MIT Press, 1999.
Abstraction-refinement in model checking• Counterexample-guided abstraction refinement for symbolic
model checkingE. Clarke, O. Grumberg, S. Jha, Y. Lu, H. Veith, JACM 50(5): 752-794 (2003)
Vacuity in model checking• Efficient detection of vacuity in temporal model checking
I. Beer, S. Ben-David, C. Eisner, Y. Rodeh, Formal Methods in System Design, 18, 2001.
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ReferencesSTE• Formal verification by symbolic evaluation of partially-
ordered trajectoriesC-J. Seger and R. Bryant, Formal Methods in System Design, 6(2), 1995.
FORTE• An industrially effective environment for formal hardware
verificationC-J Seger, R. Jones, J. O’Leary, T. Melham, M. Aagaard, C. Barrett, D. Syme, IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(9), 2005
• FORTEhttp://www.intel.com/software/products/opensource/tools1/verification
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ReferencesRefinement in STE• Automatic refinement and vacuity detection for symbolic
trajectory evaluation– R. Tzoref and O. Grumberg, CAV’06– R. Tzoref, Master thesis, Technion, Haifa, 2006
• SAT-based assistance in abstraction refinement for symbolic trajectory evaluationJ-W. Roorda and K. Claessen, CAV’06
GSTE• Introduction to generalized symbolic trajectory evaluation
J. Yang and C-J. Seger, IEEE transactions on very large scale integrated systems, 11(3), 2003.
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THE END