July 2005

NASA Electronic Parts and Packaging Program

Switching Characteristics of JFET Transistorsat Cryogenic Temperatures

Richard Patterson, NASA Glenn Research CenterAhmad Hammoud, QSS Group, Inc. / NASA GRC

Malik Elbuluk, University of Akron

Scope

Spacecraft on-board electronics are maintained at about room temperature through the use of various thermal control elements for proper operation in space missions where cryogenic temperatures are anticipated. Cryogenic temperatures are typically encountered in planetary exploration and deep space applications, such as Mars and Saturn environments. Electronics that are capable of functioning properly at extreme low temperatures would enhance efficiency of space power systems, improve reliability, simplify design, and decrease development and launch costs. These benefits come about due to the elimination of heating elements and their accessories, and the resulting reduced part count in designing the electrical power system. In this work, the performance of P-channel FET (Field Effect) transistors was evaluated under low temperature and thermal cycling. The investigations were carried out to establish a baseline on functionality and to determine suitability of these devices for use in space applications under cryogenic temperatures. These devices were chosen because they are being considered by the NASA Jet Propulsion Laboratory (JPL) for use in electronic circuits on future space missions.

Test Procedure

The devices investigated in this work comprised of Fairchild Semiconductor FDV304P and NDS352A P-channel FET enhancement mode transistors. These transistors are produced using DMOS technology to minimize on-state resistance [1-2]. Two devices of each type of these transistors were examined for operation between -195 °C and +100 °C. Performance characterization was obtained in terms of their switching characteristics, using a Sony/Tektronix 370A programmable curve tracer, at specific test temperatures. Cold-restart capability, i.e. power switched on while the devices were at a temperature of -195 °C, was also investigated. A temperature rate of change of 10 °C per minute was used, and a soak time of at least 20 minutes was allowed at every test temperature. The effects of thermal cycling under a wide temperature range on the operation of these transistors were also investigated. The devices were exposed to a total of 10 cycles between -195 °C and +100 °C at a temperature rate of 10 °C/minute. Following the thermal cycling, measurements were then performed at the test temperatures of +20, -195, +100, and again at +20 °C. Some of the manufacturer’s specifications for these FET transistors are shown in Table I [1-2].

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Table I. Manufacturer’s specifications of FET transistors [1-2].

Parameter Symbol FDV304P NDS352APOperating Temperature (°C) T(oper) -55 to +150 -55 to +150Drain Current (mA) ID -460 ±900Gate-Source Voltage (V) VGS -8 ±20Power dissipation (W) PD 0.35 0.5Type P-Channel P-ChannelPackage SOT-23 SuperSOT-3Lot Number JX-2233 JX-244

Test Results

Although two devices of each of these FET transistors were evaluated, data pertaining to only one of each type of these devices is presented due to the similarity in the results of the same type devices.

Temperature Effects

The pre-cycling output characteristics of the FDV304P transistors at the selected test temperatures of +20 °C, -100 °C, -195 °C, and +100 °C are shown in Figure 1. These output characteristics are defined as the drain current (ID) versus drain-to-source voltage (VDS) family curves at various gate voltages (VGS). Gate voltages (VGS) utilized in this test were in the range between 0 and -5.0 volts. Two deviations can be noted in the output characteristics with change in temperature. The first is the upward shift of the switching curves, for a given gate voltage, as the temperature is decreased below room temperature. At high temperatures, i.e. +100 °C, this trend reverses as the switching curves exhibit a downward shift as compared to their room temperature counterpart. The second deviation represents the variation in the slope of the switching curves in the linear region, for a given gate voltage, as the test temperature is changed. Such a trend is evident by the leftward shift of the switching characteristics in the linear region as temperature is decreased, and vice versa. This temperature-induced variation in the steepness or the slope of these curves reflects a change in the drain-source on-resistance (RDS(on)) of the device. As can be seen in Figure 1, a decrease in the test temperature results in a reduction in the on-resistance. Similarly, an increase in temperature leads to an increase in value of this property.

The output characteristics of the NDS352A transistor before cycling are shown in Figure 2 at the test temperatures of +20 °C, -100 °C, -195 °C, and +100 °C. Gate voltages (VGS) between 0 and -5.0 volts were also used in this characterization. Similar to its FDV304 counterpart, this transistor exhibited changes in its output characteristics with temperature. These changes, which are reflected by the shift and steepness of the switching family curves, are attributed to the change in the gate threshold voltage and on-resistance with temperature.

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(+20 °C)

(-195 °C)

(-100 °C)

(+100 °C)

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Figure 1. Pre-cycling switching characteristics of FDV304P transistor at various test temperatures.

(+20 °C)

(-195 °C)

(-100 °C)

(+100 °C)

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Figure 2. Pre-cycling switching characteristics of NDS352A transistor at various test temperatures.

Cold Re-Start

Cold-restart capability of the FDV304P and NDS352A P-channel FET transistors was investigated by allowing the devices to soak at -195 °C for at least 20 minutes without the application of electrical bias. Power was then applied to the device under test, and measurements were taken on the output switching characteristics. Both types of transistors were able to successfully cold-start at -195 °C, and the results obtained were the same as those obtained earlier at that temperature.

Effects of Thermal Cycling

The effects of thermal cycling under a wide temperature range on the operation of the FDV304P and NDS352A P-channel FET transistors were investigated by subjecting them to a total of 10 cycles between -195 °C and +100 °C at a temperature rate of 10 °C/minute. Switching characteristics of the transistors were then taken at +20 °C, -195 °, and +100°C. Comparisons of the switching characteristics of the FDV304P and NDS352A transistors at those selected test temperatures before and after the thermal cycling are depicted in Figures 3 and 4, respectively. It can be clearly seen that the post-cycling family of switching curves, for either transistor, is the same as that of pre-cycling for a given test temperature. Therefore, exposure of these transistors to extreme temperature between -195 °C and +100 °C, as well as cycling in this temperature range did not induce any significant change in their switching behaviors. This limited thermal cycling also appeared to have no effect on the structural integrity of these devices as no structural deterioration or packaging damage was observed.

Conclusions

Fairchild Semiconductor FDV304P and NDS352A P-channel FET enhancement mode transistors were evaluated for operation between -195 °C and +100 °C. The effects of thermal cycling under a wide temperature range on the operation of these transistors and cold-restart capability were also investigated. Both devices were able to maintain good operation between -195 °C and +100 °C with minimal changes in their characteristics. The temperature-induced changes included variation in the gate threshold voltage levels and a change in the value of the on-resistance. The changes, however, were transitory in nature as both devices recover to their original characteristics upon removal of the thermal stress. In addition, the limited thermal cycling performed on the transistors had no effect on their performance, and both devices were able to cold start at -195 °C. Further testing under long-term cycling is required to fully establish the reliability of these devices and to determine their suitability for extended use in extreme temperature environments.

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Pre-cycling at 20 °C

Pre-cycling at -195 °C

Pre-cycling at +100 °C

Post-cycling at 20 °C

Post-cycling at -195 °C

Post-cycling at +100 °C

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Figure 3. Comparison of the switching characteristics of the FDV304P transistor at selected test temperatures before and after thermal cycling.

Pre-cycling at 20 °C

Pre-cycling at -195 °C

Pre-cycling at +100 °C

Post-cycling at 20 °C

Post-cycling at -195 °C

Post-cycling at +100 °C

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Figure 4. Comparison of the switching characteristics of the NDS352A transistor at selected test temperatures before and after thermal cycling.

References

[1]. Fairchild Semiconductor Corporation, “FDV304P Digital FET, P-Channel Transistors”, Data Sheet FDV304P Rev. E1, August 1997.

[2]. Fairchild Semiconductor Corporation, “NDS352AP P-Channel Logic Level Enhancement Mode Field Effect Transistor”, NDS352AP Rev. D, February 1997.

Acknowledgements

This work was performed under the NASA Glenn Research Center GESS Contract # NAS3-00145. Funding was provided by the NASA Electronic Parts and Packaging (NEPP) Program.

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