SV300G3 BIOS User Manual UM_V0.7_20180212.pdf · 8 Wiwynn SV300G3 BIOS User Manual 1.3 Menu Bar The...

SV300G3 BIOS

User Manual

Version 0.7

February

Copyright © 2018 Wiwynn. All rights reserved.

2 Wiwynn SV300G3 BIOS User Manual

Copyright

Copyright © 2018 by Wiwynn Corporation. All rights reserved. No

part of this publication may be reproduced, transmitted, transcribed,

stored in a retrieval system, or translated into any language or

computer language, in any form or by any means, electronic,

mechanical, magnetic, optical, chemical, manual or otherwise,

without the prior written permission of Wiwynn Corporation.

Disclaimer

The information in this guide is subject to change without notice.

Wiwynn Corporation makes no representations or warranties, either

expressed or implied, with respect to the contents hereof and

specifically disclaims any warranties of merchantability or fitness for

any particular purpose. Any Wiwynn Corporation software described

in this manual is sold or licensed "as is". Should the programs prove

defective following their purchase, the buyer (and not Wiwynn

Corporation, its distributor, or its dealer) assumes the entire cost of

all necessary servicing, repair, and any incidental or consequential

damages resulting from any defect in the software.

Wiwynn SV300G3 BIOS User Manual 3

Revision History

Date Version Modifications

2017/12/13 0.6 First draft based on STTG3_BIOS_Specification 0.6

2018/02/12 0.7 Revision based on STTG3_BIOS_Specification 0.7


Contents

Preface ................................................................................................... 6

Introduction...................................................................................... 6

About this Manual ............................................................................ 6

1. BIOS Setup .................................................................................... 7

1.1 Entering BIOS Setup ............................................................... 7

1.2 BIOS Hotkeys .......................................................................... 7

1.3 Menu Bar ................................................................................ 8

1.4 Navigation Keys ...................................................................... 9

2. Main .............................................................................................. 10

3. Advanced ..................................................................................... 11

3.1 iSCSI Configuration ............................................................... 12

3.2 Intel(R) Virtual RAID on CPU ................................................. 12

3.3 Trusted Computing ................................................................ 13

3.4 Serial Port Console Redirection ............................................. 14

3.5 SIO Configuration .................................................................. 15

3.6 PCI Subsystem Settings ........................................................ 17

3.7 Network Stack Configuration.................................................. 18

3.8 CSM Configuration ................................................................ 19

3.9 USB Configuration ................................................................. 20

3.10 Wiwynn Options .................................................................... 21

4. Platform Configuration ................................................................ 22

4.1 PCH Configuration................................................................. 22

4.2 Miscellaneous Configuration .................................................. 32

4.3 Server ME Configuration ....................................................... 33

4.4 Runtime Error Logging........................................................... 34

5. Socket Configuration................................................................... 41

5.1 Processor Configuration ........................................................ 41

5.2 Common RefCode Configuration ........................................... 45

5.3 UPI Configuration .................................................................. 46


5.4 Memory Configuration ........................................................... 50

5.5 IIO Configuration ................................................................... 60

5.6 Advanced Power Management Configuration ........................ 83

6. Server Mgmt............................................................................... 111

6.1 System Event Log ............................................................... 112

6.2 BMC network Configuration ................................................. 113

7. Security ...................................................................................... 114

8. Boot ............................................................................................ 115

9. Save & Exit ................................................................................. 116

10. POST Code Table ....................................................................... 117

10.1 PEI Phase ........................................................................... 117

10.2 DXE Phase ......................................................................... 119

10.3 DIMM Error Code POST ...................................................... 122


Preface

Basic Input/Output System (also known as BIOS) is a firmware program

stored on a chip in the system mainboard.

Introduction

BIOS Setup is a text-based utility that allows the user to configure the system

and view current settings and environment information for the platform

devices. The Setup utility controls the platform’s built-in devices, the Boot

Manager and Error Manager.

About this Manual

This manual contains information about the system BIOS and discusses how

to configure the system by changing the settings of the BIOS parameters.

Chapter 1 contains information regarding the BIOS setup, hotkeys, menu bar

and navigation keys.

Chapters 2 to 9 contain detailed description of the BIOS menus, submenus

and functions.

Chapter 10 contains the POST code tables.


1. BIOS Setup

1.1 Entering BIOS Setup

To enter BIOS Setup, press the <Del> or <Esc> key during the

Power-On-Self-Test (POST) to enter the BIOS Setup menu, otherwise,

POST will continue with its test routines.

Note that the BIOS Setup options may vary depending on your hardware

configuration.

1.2 BIOS Hotkeys

The following hotkeys work during POST:

Key Function

Del (Esc) Enter BIOS setup utility

F7 Enter Boot Menu


1.3 Menu Bar

The tabs on the BIOS menu bar at the top of the screen are:

Main: Shows the BIOS version, Processor and System Memory

information. You can set the System Time and System Date here.

Advanced: Sets the Advanced settings for Power, Memory, USB, and

Super IO.

Platform Configuration: Sets the USB, Network, South Bridge chipsets

configurations.

Socket Configuration: Sets the processor, thermal management and

North Bridge chipsets configurations.

System Mgmt: Configures server management features.

Security: Sets the system security features.

Boot: Sets the boot configuration, quiet boot and boot device priority.

Save & Exit: Sets to save or discard the configuration changes made on

other Setup screens.

Use the < Enter > key or to select a field on the menu bar.


1.4 Navigation Keys

Use the following navigation keys to set the BIOS parameters:

Key Function

← → Select screen

↑↓ Select item

Enter Select

+/- Change option

F1 General Help

F8 Previous Values

F9 Optimized Defaults

F10 Save & Reset

Esc Exit

NOTES: Setup options may vary depending on your hardware

configuration. Grayed-out fields are not

user-configurable.

In the descriptive table following each of the menu screenshots, settings

in boldface are the default and suggested settings.


2. Main After entering the BIOS Setup Utility, you will see the Main menu screen.

Main menu displays the BIOS, processor and memory information. You

can also set the system date and time here.


3. Advanced Advanced screen provides an access point to configure several groups of

options. On this screen, the user can select the option group to be

configured. Configuration actions are performed on the selected screen, and

not directly on the Advanced screen.

WARNING: Setting the wrong values in the Advanced menu may cause

the system to malfunction.

Select a submenu item and then press Enter to access the related

submenu screen.


3.1 iSCSI Configuration

3.2 Intel(R) Virtual RAID on CPU

The configuration parameters are dependent on Intel driver.


3.3 Trusted Computing

Parameter Description Option

Security Device

Support

Enables or disables BIOS support for

security device. OS will not show Security

Device. TCG EFI protocol and INT1A

interface will not be available.

Enabled,

Disabled

Current Status

Information

Displays the current status of the Security

Device.


3.4 Serial Port Console Redirection

To manage your host remotely from a serial console, you can redirect the

console to a serial port. Use this option to enable or disable the Console

Redirection function. The default value is [Enabled].


Terminal Type Character formatting used for console

redirection. This setting must match the

remote terminal application.

ANSI: Extended ASCII char set.

VT100: ASCII char set.

VT100+: Extends VT100 to support color,

function keys, etc.

VT-UTF8: Uses UTF8 encoding to map

Unicode chars onto 1 or more bytes.

VT100+,

VT100,

VT-UTF8,

ANSI


3.5 SIO Configuration

This submenu allows you to view the super I/O chip and configure the serial

port settings.


3.5.1 [*Active*] Serial Port


Use This

Device

Enables or disables this

logical device.

Enabled

Disabled

Possible Allows the user to

change the device

resource settings. New

settings will be reflected

on this setup page after

system restarts.

Use Automatic Settings

IO=3F8h; IRQ=4; DMA;

IO=3F8h; IRQ=3,4,5,7,9,10,11,12; DMA;

IO=2F8h; IRQ=3,4,5,7,9,10,11,12; DMA;

IO=3E8h; IRQ=3,4,5,7,9,10,11,12; DMA;

IO=2E8h; IRQ=3,4,5,7,9,10,11,12; DMA


3.6 PCI Subsystem Settings


Above 4G

Decoding

Enables or disables 64-bit capable devices to

be decoded in above 4G address space (only

if system supports 64-bit PCI decoding).

Enabled,

Disabled

SR-IOV

Support

If system has SR-IOV capable PCIe devices,

this option enables or disables Single Root IO

Virtualization Support.

Enabled,

Disabled


3.7 Network Stack Configuration


Network Stack Enables or disables UEFI network stack. Enabled,

Disabled

Ipv4 PXE Support Enables Ipv4 PXE Boot Support. If disabled,

IPV4 PXE boot option will not be created.

Enabled,

Disabled

Ipv6 PXE Support Enables Ipv6 PXE Boot Support. If disabled,

IPV6 PXE boot option will not be created.

Enabled,

Disabled


3.8 CSM Configuration

This function enables or disables the Compatibility Support Module

Configuration (CSM).


CSM

Support

Enable or disable CSM Support. If CSM

Support is enabled, you will see the following

parameters.

Enabled,

Disabled

Network This option controls the execution of UEFI and

Legacy PXE OpROM.

UEFI, Legacy,

Do not launch

Storage This option controls the execution of UEFI and

Legacy Storage OpROM.

UEFI, Legacy,

Do not launch

Video This option controls the execution of UEFI and

Legacy Video OpROM.

Legacy, UEFI

Other PCI

device

This option determines the OpROM execution

policy for devices other than Network, Storage

or Video.

UEFI, Legacy

Do not launch


3.9 USB Configuration


Legacy USB

Support

Select Enabled to enable legacy USB support.

Auto disables legacy support if no USB devices

are connected. Disabled keeps USB devices

available only for EFI applications.

Enabled,

Disabled

Auto

XHCI Hand-off This is a workaround for OSes without XHCI

hand-off support. The XHCI ownership change

should be claimed by XHCI driver.

Enabled,

Disabled


3.10 Wiwynn Options


Onboard LAN

OPROM

Selection

Onboard LAN OPROM selection between

PXE and iSCSI for Legacy mode.

PXE,

iSCSI

Memory ECC

Log Threshold

ECC error event log threshold, defines the

max number of correctable DIMM ECC is

logged in the same boot. Default value is

10, with option Disable, 10, 50, and 100.

10,

Disable,

50, 100


4. Platform Configuration

4.1 PCH Configuration


4.1.1 PCH Devices


PCH state

after G3

Select S0/S5 for ACPI state

after a G3.

Leave power state unchanged,

S0, S5

4.1.2 PCI Express Configuration



PCI-E ASPM

Support

This option enables disables the ASPM

support for all downstream devices.

Per individual port,

Global, L1 Only

PCIe Root

Port Function

Swapping

Enables PCIe root port function

swapping feature to dynamically

assign function 0 to enabled root port.

Enable,

Disable

PCI Express

Root Port

1~20

PCI Express Root Port 1-20 settings.


PCI Express Root Port 1~20


PCI Express Root

Port 1~20

Controls the PCI Express Root Port. Enable,

Disable

PCIE ASPM PCI Express Root port ASPM

Setting.

Disable ASPM,

ASPM L1, ASPM

Auto

PCIe Speed Configures PCIe Speed. Auto,

Gen2, Gen3

PCIE Lane

Topology

Identifies the PCIE Lane topology if it

is x1, x4, SATA Express or M2.

Unknown,

x1, x4, M2

SATA Express


4.1.3 PCH SATA Configuration



SATA Controller Enables or disables SATA controller. Enabled,

Disabled

Configure SATA as Configures SATA port as AHCI or

RAID.

AHCI,

RAID

SATA test mode Enables or disables SATA test mode Enabled,

Disabled

SATA Mode Options

SATA HDD Unlock If enabled, HDD password unlock is

enabled in the OS.

Enabled,

Disabled

SATA LED Locate If enabled, LED/SGPIO hardware is

attached.

Enabled,

Disabled

Support Aggressive

Link Power

Management

Enables or disables Support

Aggressive Link Power (SALP),

Enabled,

Disabled

Hot Plug

0/1/2/3/4/5/6/7

Designates this port as hot pluggable. Enabled,

Disabled

Spin Up device

0/1/2/3/4/5/6/7

If enabled for any port, staggerred spin

up will be performed and only the

drives which have this option enabled

will spin up at boot. Otherwise all

drives will spin up at boot.

Disabled,

Enabled

SATA Topology

0/1/2/3/4/5/6/7

Identifies the SATA topology as default

(Unkown), ISATA, Flex, Direct

Connect or M2.

Unknown, ISATA,

Direct Connect,

Flex, M2


4.1.4 PCH sSATA Configuration



sSATA Enables or disables SATA Controller. Enabled,

Disabled

Configure sSATA

as

This will configure SATA as IDE, RAID

or AHCI.

AHCI,

RAID

SATA test mode Enables or disable SATA controller. Enabled,

Disabled

SATA Mode Options

SATA HDD Unlock If enabled, HDD password unlock is

enabled in the OS.

Enabled,

Disabled

SATA LED Locate If enabled, LED/SGPIO hardware is

attached.

Enabled,

Disabled

Support Aggressive

Link Power

Management

Enables or disables Support

Aggressive Link Power (SALP),

Enabled,

Disabled

Hot Plug

0/1/2/3/4/5/6/7

Designates this port as hot pluggable. Enabled,

Disabled



Spin Up device

0/1/2/3/4/5/6/7

If enabled for any port, staggerred spin

up will be performed and only the

drives witch have this option enabled

will spin up at boot. Otherwise all

drives will spin up at boot.

Disabled,

Enabled

SATA Topology

0/1/2/3/4/5/6/7

Identifies the SATA topology as default

(Unkown), ISATA, Flex, Direct

Connect or M2.

Unknown,

ISATA, Direct

Connect, Flex,

M2


4.2 Miscellaneous Configuration


Active Video Selects the active Video type. Auto,

Onboard Device,

PCIE Device)

NumLock Enables or disables NumLock. Disabled,

Enabled

SR-IOV Support If system has SR-IOV capable PCIe

devices, this option enables or

disables Single Root IO Virtualization

support.

Enabled,

Disabled

SR-IOV

SystemPageSize

Selects SR-IOV SystemPageSize. 4K, 8K, 64K,

256K, 1M, /4M

MR-IOV Support Enables or disables MR-IOV support. Enabled,

Disabled


4.3 Server ME Configuration

Display the Server ME configuration parameters.


4.4 Runtime Error Logging


System Errors Enables or disables system error setup

options.

Enable,

Disable

S/W Error Injection

Support

If enabled, S/W Error Injection is

supported by unlocking MSR 0x790.

Enable,

Disable

System Memory

Poison

Enables or disabled the System Memory

Poison.

Disable,

Enable

System Cloaking If enabled, corrected and UCNA errors

are masked from OS/SW visibility.

Disable,

Enable

CATERR->GPIO->

SMI

Enables or disabled PCH GPIO to trigger

SMI on CATERR.

Enable,

Disable

FatalErrDebugHalt DEBUG loop for McBank fatal error case

ONLY.

WARNING: Enable this knob only in

conjunction with ITP as thread will halt in

Fatal error flow.

Disable,

Enable


4.4.1 eMCA Settings


EMCA Logging

Support

Enables or disables EMCA Logging. Enable,

Disable

LMCE Support Enables or disables Local MCE

firmware support.

Enable,

Disable

Ignore OS

EMCA Opt-in

Enables or disables Ignore OS

EMCA Opt-in and log.

Disable,

Enable

EMCA

CMCI-SMI

Morphing

Enables or disables EMCA CSMI. EMCA gen 2 CSMI,

Disable,

EMCA gen 1 Lite

EMCA

MCE-SMI

Enable

Enables or disables EMCA

Uncorrected SMI for gen1 and

gen2,

EMCA gen 2 –

MSMI,

Disable,

EMCA gen 1 Dual

Mode

Corrected Error

eLog

Enables or disables Corrected Error

eLog.

Enable,

Disable

Memory Error

eLog

Enables or disables Memory Error

eLog

Enable,

Disable

Processor Error

eLog

Enables or disables Processor Error

eLog

Enable,

Disable


4.4.2 Whea Settings


WHEA Support Enables or disables WHEA support. Enable,

Disable

Whea Log

Memory Error

Enables or disables Whea Log Memory

Error.

Enable,

Disable

Whea Log

Processor Error

Enables or disables Whea Log Processor

Error.

Enable,

Disable

Whea Log PCI

Error

Enables or disables Whea Log PCI Error. Enable,

Disable


4.4.3 Memory Error Enabling


Memory Error Enables or disables Memory Error. Enable,

Disable

Memory

Corrected Error

Enables or disables Memory Corrected Error Enable,

Disable

Spare Interrupt Spare Interrupt selection. SMI,

Disable,

Error Pin,

CMCI


4.4.4 IIO Error Enabling


IIO/PCH Global

Error Support

Enables or disables IIO/PCH error support. Enable,

Disable

IIO MCA

Support

Enables or disables IIO MCA support. Enable,

Disable

IIO Error

Registers Clear

Enables or disables clearing of IIO Error

registers.

Enable,

Disable


4.4.5 PCIe Error Enabling



Corrected Error Enables and escalates correctable

errors to error pins.

Enable,

Disable

Uncorrected

Error

Enables and escalates uncorrectable

and recoverable errors to error pins.

Enable,

Disable

Fatal Error

Enable

Enables and escalates fatal errors to

error pins.

Enable,

Disable

PCIE Corrected

Error Threshold

Counter

Enables and disables PCIE corrected

error counter.

Disable,

Enable

PCIE Corrected

Error Threshold

0x001 - 0xffff 1

PCIE AER

Corrected

Errors

Enables and disables PCIE AER

corrected errors.

Enable,

Disable

PCIE AER

Advisory

Nonfatal Error


Advisory Nonfatal Error

Enable,

Disable

PCIE AER

NonFatal Error


Nonfatal Error.

Enable,

Disable

PCIE AER

Fatal Error

Enables and disables PCIE AER Fatal

Error.

Enable,

Disable

SERR

Propagation

Enables and disables SERR

Propagation.

Enable,

Disable

PERR

Propagation

Enables and disables SERR

Propagation.

Enable,

Disable

Signal to OS on

SERR

Enables and disables Signal to OS on

SERR.

Enable,

Disable

Signal to OS on

PERR

Enables and disables Signal to OS on

PERR.

Enable,

Disable


5. Socket Configuration

5.1 Processor Configuration



Hyper-Threading Enables Hyper Threading (Software

Method to enable or disable Logical

Processor threads.

Enable,

Disable,

All

Max CPUID

Value Limit

This should be enabled in order to boot

legacy OSes that cannot support

CPUs with extended CPUID functions.

Disable,

Enable

Execute Disable

Bit

If disabled, forces the XD feature flag to

always return 0.

Enable,

Disable

Enable Intel(R)

TXT

Enables Intel(R) TXT. Disable,

Enable

VMX Enables the Vanderpool Technology,

takes effect after reboot.

Enable,

Disable

Enable SMX Enables Safer Mode Extensions. Disable,

Enable

Hardware

Prefetcher

= MLC Streamer Prefetcher (MSR 1A4h

Bit[0])

Disable,

Enable

Adjacent Cache

Prefetch

= MLC Spatial Prefetcher (MSR 1A4h

Bit[1])

Disable,

Enable



DCU Streamer

prefetcher

DCU streamer prefetcher is an L1 data

cache prefetcher (MSR 1A4h [2]).

Disable,

Enable

DCU IP

Prefetcher

DCU IP prefetcher is an L1 data cache

prefetcher (MSR 1A4h [3]).

Enable,

Disable

DCU Mode MSR 31h Bit[0] - A write of 1 selects the

DCU mode as 16KB 4-way with ECC.

32KB 8Way

Without ECC,

16KB 4Way

With ECC

5.1.1 Per-Socket Configuration


CPU Socket 0/1 Configuration


IOT Cfg Each bit enables IOT/OCLA for a CBo. Disable,

Enable


5.2 Common RefCode Configuration


Isoc Mode Enables or disables Isoc. Auto,

Disable,

Enable

Numa Enables or disables Non uniform Memory

Access (NUMA).

Enable,

Disable


5.3 UPI Configuration

5.3.1 UPI General Configuration



Link Speed

Mode

Selects the UPI link speed as the POR

speed. Options are Fast (default) and

Slow.

Fast,

Slow

Link Frequency

Select

Selects the UPI Link Frequency. Auto, 5.6GB/s,

6.4GB/s, 7.2GB/s,

8.0GB/s, 8.8GB/s,

9.6GB/s, 10.4GB/s

Link L0p

Enable

Enable: Sets the c_l0p_en

Disable: Resets

Auto: Decides based on Si

Compatibility

Auto,

Enable, Disable

Link L1 Enable Enable: Sets the c_l1_en

Disable: Resets


Compatibility

Auto,

Enable, Disable

UPI Failover

Support

Enable: Sets the c_failover_en

Disable: Resets


Compatibility

Auto,

Enable, Disable

UPI Status


5.3.2 UPI Per Socket Configuration

CPU 0/1


CPU 0/1 UPI Port 0/1/2

CPU 0/1 UPI Port DFX 0/1/2


5.4 Memory Configuration



Enforce POR Enable: Enforces Plan Of Record

restrictions for DDR4 frequency and

voltage programming.

Disable: Disables this feature.

Auto: Sets to the MRC default setting;

Auto,

Enable, Disable

PPR Type Selects Post Package Repair Type.

Auto - Sets to the MRC default setting;

current default is Disabled.

Hard PPR, PPR

Disabled,

Auto, Soft PPR,

PPR Error

Injection test

Enables or disables support for

c-script err inj test.

Disable,

Enable

Memory

Frequency

Maximum Memory Frequency

Selections in Mhz. Do not select

Reserved.

Auto,1866, 2133,

2400, 2666

Halt on mem

Training Error

Enables or disables Halt on mem

Training Error.

Enable,

Disable

Multi-Threaded

MRC

Enable: Executes the Memory

Reference Code multi-threaded.

Disable: Disables this feature. Auto:

Sets to MRC default setting; current

default is Enable.

Auto,

Enable, Disable

SPD CRC

Check

Enable Checks the SPD CRC. Auto,

Enable, Disable

LRDIMM

Module Delay

Disable: MRC will not use SPD bytes

90-95 for LRDIMM Module Delay.

Auto: MRC will boundary check the

values and use default values, if SPD

is 0 or out of range.

Auto,

Enable, Disable

MemTest Enables or disables memory test

during normal boot. Auto sets to MRC

default setting; current default is

Enable.

Auto,

Enable, Disable

MemTestLoops Number of memory test loops during

normal boot, set to 0 to run memtest

infinitely

1



Attempt Fast

Boot

Enable: Portions of memory reference

code will be skipped when possible to

increase boot speed on warm boots.


Auto: Sets to the MRC default setting;

Disable,

Enable, Auto

Attempt Fast

Cold Boot

Enable: Portions of memory reference

code will be skipped when possible to

increase boot speed on cold boots.


Auto: Sets to the MRC default setting.

Auto,

Enable, Disable

MemTest On

Fast Boot

Enables or disables memory test

during fast boot. Auto sets to the

MRC default setting; current default is

Disable.

Auto,

Enable, Disable

Data

Scrambling for

DDR4

Enables or disables data scrambling

for DDR4. Auto sets to the MRC

default setting;

Auto,

Enable, Disable

Allow

Correctables

Enables or disables correctable errors

during memory training. Auto sets to

the MRC default setting;

Auto,

Enable, Disable

DIMM Isolation

Enable

Enables or disables DIMM Isolation for

Command/Address Parity and Write

CRC. Auto sets to the MRC default

setting;

Auto,

Enable, Disable

C/A Parity

Enable

Enables or disables DDR4 Command

Address Parity. Auto sets the MRC

default setting; current default is

Enable.

Enable,

Disable, Auto


5.4.1 Memory Topology


5.4.2 Memory Map


IMC

Interleaving

Selects the IMC Interleaving setting. Auto,

Enable, Disable

Channel

Interleaving

Selects the channel interleaving

setting.

Auto,

Enable, Disable

Rank

Interleaving

Selects the rank interleaving setting. Auto,

Enable, Disable

Socket

Interleave

Below 4GB

Splits the 0-4GB address space

between two sockets, so that both

sockets get a chunk of local memory

below 4GB.

Disable,

Enable


5.4.3 Memory RAS Configuration


Static Virtual

Lockstep Mode

Enables or disables Static Virtual

Lockstep mode.

Disable,

Enable

Mirror mode Mirror Mode sets entire 1LM/2LM

memory in system to be mirrored,

consequently reducing the memory

capacity by half. Enabling Mirror mode

will disable XPT Prefetch.

Disable,

Enable

Memory Rank

Sparing

Enables or disables Memory Rank

Sparing.

Disable,

Enable

Correctable

Error Threshold

Correctable Error Threshold (1 -

32767) is used for sparing, tagging,

and leaky bucket.

1000


5.4.4 NGN Configuration


Set TDP DIMM

power limit

Sets the current total dissipated

DIMM power limit.

12W,

10W, 15W, 18W

ARS on Boot Enables or disables Address Range

Scrub during boot time.

Auto,

Enable, Disable

Lock NGN

CSRs

Enables or disables Lock NGN

CSRs.

Auto,

Enable, Disable

Debug lock for

NGN

Enables or disables Debug lock for

NGN.

Auto,

Enable, Disable

NGN CMD

Time

Selects 1N\2N NGN Command

time.

Auto,

Enable, Disable

NGN ECC

Correctable

Enables or disables NGN ECC

Correctable error.

Auto,

Enable, Disable

NGN ECC

Write Check

Enable\Disable NGN ECC Write

Check.

Auto,

Enable, Disable



NGN ECC

Read Check

Enables or disables NGN ECC

Read Check.

Auto,

Enable, Disable

CR QoS

Configuration

Selects CR QoS Configuration

Profiles.

no QoS

optimization,

Option 1, Option 2,

Option 3, Option 4,

Option 5


5.4.5 Memory Dfx Configuration


DIMM

Management

Selects whether BIOS Setup or the

NGN DIMM Management Driver will

control the NVMDIMMs.

Auto,

Enable, Disable

Load NGN DIMM

Management

Drivers

Enables or disables loading of the

NGN DIMM Management Drivers for

NVMDIMMs (install the

gNfitBindingProtocolGuid).

Auto,

Enable, Disable

High Address

Region

High Address Region starting bit

position. Auto = 0 (not enabled). Note

that the actual start of the region is

2**N - 64MB, where N is the selected

bit position.

Auto,

Enable, Disable

Low Mem

Channel Config

Selects the Channel for low memory,

Auto= 0 (BIOS select).

Auto,

Enable, Disable

CR Halt/Warn

Mixed SKU

Enable will raise Fatal error and halt

the system; Disable will log warning

and continue booting to shell/OS.

Auto,

Enable, Disable


5.4.6 BSSA Configuration Menu


BSSA Module

Loader

Enables or disables the loading of

BSSA test module.

Auto,

Enable, Disable

BSSA Rank

Margin Tool

Enables or disables the BSSA Rank

Margin Tool.

Auto,

Enable, Disable

BSSA RMT on

Fast Cold Boot

Enables or disables the BSSA Rank

Margin Tool on a Fast Cold Boot

Auto,

Enable, Disable


5.5 IIO Configuration



PCIe Train by

BIOS

Assume IIO is strapped for Wait-for-BIOS

because straps are unreliable in A-0

Silicon.

Yes,

No

PCIe Hot Plug Enables or disables PCIe Hot Plug

globally.

Enable,

Disable

PCIe ACPI Hot

Plug

Enables or disables PCIe ACPI Hot Plug

globally, or allow per-port control. If

disabled, MSI is generated on HP event. If

enabled, _HPGPE message is generated.

Disable,

Enable

PCIe Surprise

Hot Plug

Enables or disables PCIe Surprise Hot

Plug.

Disable,

Enable

MultiCast Enable Enables MultiCast (for validation use). Disable,

Enable

NoSnoop Read

Config

NoSnoop Read Configuration Disable,

Enable

NoSnoop Write

Config

NoSnoop Write Configuration Enable,

Disable

Max Read Comp

Comb Size

Minimum or maximum size Minimum,

Maximum

Problematic port Selects whether problematic port lock

flows need to be enabled in the system.

Selection allows for P-P or NP-NP lock

flows or neither.

Disable,

Enable

DMI Allocating

Write Flows

Selects DMI Vc0/VCp writes selection as

either allocating or non-allocating. Auto

enables POR setting.

Allocating,

Non-Allocating

PCIe Allocating

Write Flows

Selects Vc0/VCp write selection for all

CPU PCIe ports as either allocating or

non-allocating. Auto enables POR setting.

Allocating,

Non-Allocating

Skip Halt On DMI

Degradation

Enable this option to avoid the system to

be halted on DMI width/link degradation.

Disable,

Enable

Rx Clock WA HSX HSD# 4166557 Disable,

Enable

PME2ACK

Timeout

Controls duration to wait between

PME_TURN_OFF and PME_TO_ACK.

1 ms,

10 ms, 50ms,

Test Mode


MCTP Enables or disables MCTP. Enable,

Disable

Hide PCU Func

6

Hides Power Control Unit Device 30

Function 6.

Disable,

Enable

EN1K Enables 1K granularity for I/O space decode

in each of the virtual P2P bridges

corresponding to root ports and DMI ports.

Disable,

Enable

Dual CV IO

Flow

Allows ucode enable Dual CV feature in the

Cbo.

Enable,

Disable

PCIE Coherent

Read Partial

Configures Coherent Reads for Available

Settings.

PCIRdCur

Setting,

PRd Setting

PCIE Coherent

Read Full

Configures Coherent Reads for Available

Settings.

PCIRdCur

Setting,

PRd Setting

PCI-E

Completion

Timeout

(Global)

Enables or disables the Completion Timeout

(D:x F:0 O:B8h B:4) where x is 0-3.

No,

Yes, Per Port

PCI-E Global

Timeout Value

Programs the Completion Timeout Value

(D:x F:0 O:B8h B:3-0) where x is 0-3.

260ms to

900ms,

50.s to 10ms,

16ms to 55ms,

65ms to 210ms,

1s to 3.5s,

4s to 13s,

17s to 64s

PCI-E ASPM

Support

(Global)

Enables or disables the ASPM support for all

downstream devices.

Disable,

Enable

PCIE Stop &

Scream

Support

Enables or disables PCIE Stop & Scream

Support.

Disable,

Enable

Snoop

Response

Hold Off

Sets Snoop Response Hold Off value, 256

cycles as Default.

9

PCIe Latency

Tolerance

Auto/Disable: Turns off the Latency

Tolerance Report feature of the Pcie Root

Auto,


Reporting port and endpoint. Enable: Turns on the

Latency Tolerance Report feature.

Enable,

Disable

PCIe Extended

Tag Enable

Auto/Enable: BIOS sets 8-bit Tag Field for

PCIe Root Port/EndPoint.

Disable: BIOS sets 5-bit Tag Field for PCIe

Root Port/EndPoint.

Enable,

Disable

PCIe Atomic

Operation

Request

Support

Enables or disables Atomic Operation

feature in PCIe Device Control2 register of

IIO Root Ports and Endpoints.

Disable,

Enable

PCIe Max Read

Request Size

Sets Max Read Request Size in EndPoints. Auto,

Enable,

Disable

Pcie Relaxed

Ordering

Enables or disables PCIe Relaxed Ordering. Enable,

Disable

PCIe PHY test

mode

Enables or disables PCIe PHY test mode. Disable,

Enable

5.5.1 Socketx (x = 0, 1) Configuration



IOU0

(IIO PCIe Br1)

Selects PCIe port Bifurcation for selected

slot(s).

Auto,

x4x4x4x4,

x4x4x8, x8x4x4,

x8x8, x16

IOU1

(IIO PCIe Br2)


slot(s).

Auto,

x4x4x4x4,

x4x4x8, x8x4x4,

x8x8, x16

IOU2

(IIO PCIe Br3)


slot(s).

Auto,

x4x4x4x4,

x4x4x8, x8x4x4,

x8x8, x16

MCP0

(IIO PCIe Br4)


slot(s).

Auto,

x4x4x4x4,

x4x4x8, x8x4x4,

x8x8, x16

MCP1

(IIO PCIe Br5)


slot(s).

Auto,

x4x4x4x4,

x4x4x8, x8x4x4,

x8x8, x16



PCI-E

Completion

Timeout

Enables or disables the Completion

Timeout (D:x F:0 O:B8h B:4) where x is

0-3.

No,

Yes

PCI-E

Completion

Timeout Value

Program the Completion Timeout Value

(D:x F:0 O:B8h B:3-0) where x is 0-3.

260ms to 900ms,

50.s to 10msm

16ms to 55ms,

65ms to 210ms,

1s to 3.5s, 4s to

13s, 17s to 64s

Sck0 RP

Correctable Err

Applies to root ports only. Enables

interrupt on correctable errors,

Disable,

Enable

Sck0 RP

NonFatal

Uncorrectable

Err


interrupt on a non-fatal error.

Disable,

Enable

Sck0 RP Fatal

Uncorrectable

Err


MSI/INTx interrupt on fatal errors,

Disable,

Enable

Ports (0/1A/1B/2A/3A/MCP0/MCP1)



Link Speed Chooses Link Speed for this PCIe port. Auto,

Gen 1 (2.5 GT/s),

Gen 2 (5 GT/s),

Gen 3 (8 GT/s)

Override Max

Link Width

Overrides the max link width that was set

by bifurcation.

Auto,

x1, x2, x4

PCI-E Port

DeEmphasis

De-Emphasizes control (LNKCON2[6]) for

this PCIe port.

-6.0 dB,

-3.5 dB

PCI-E Port

Clocking

Configures port clocking via LNKCON[6].

This refers to this component and the

downstream components.

Common,

Distinct

PCI-E Port

D-state

Sets to D0 for normal operation, D3Hot to

be in low-power state.

D0,

D3Hot

PCI-E ASPM

Support

This option enables or disables the ASPM

(L1) support for the downstream devices.

Disable,

Auto, L1 only

MSI BUS0 DEVx FUN0 OFF 0x5A bit 0, where

X is 0-3

Disable,

Enable

PCI-E Extended

Sync

Enables or disables the Extended Sync

Mode (D:x F:0 O:7Ch B:7) where x is 0-9.

Disable,

Enable

Compliance

Mode

Enables or disables Compliance Mode for

this PCIe port.

Disable,

Enable

EOI Dev 0,2,3 MISCCTRLSTS (Reg 0x188)Bit

26.

Enable,

Disable

Fatal Err Over Enables forced fatal error propagation to

the IIO core error logic for this port.

Disable,

Enable

Non-Fatal Err

Over

Enables forced non-fatal error propagation

to the IIO core error logic for this port.

Disable,

Enable

Corr Err Over Enables forced correctable error

propagation to the IIO core error logic for

this port.

Disable,

Enable

ACPI PME

Interrupt

If enabled, ACPI PME Interrupts are

generated from this port.

Disable,

Enable

L0s Support If disabled, IIO never places its transmitter

in L0s state.

Disable,

Enable



P2P Memory

Write

Controls Peer-to-Peer Memory Write

Decoding.

Enable,

Disable

P2P Memory

Read

Controls Peer-to-Peer Memory Read

Decoding.

Enable,

Disable

PME to ACK Controls timeout usage for IIO waiting on

PME_TO_ACK after a PME_TURN_OFF

message.

Enable,

Disable

Unsupported

Request

Controls the reporting of unsupported

requests that IIO itself detects on requests

from a PCI Express/DMI port.

Disable,

Enable

Alternate TxEq Enables or disables TxEq. Disable,

Enable

SRIS Enables or disables SRIS. Disable,

Enable

Extra Bus

Reserved

Extra bus reserved for bridges behind this

Root Bridge.

0

Reserved

Memory

Reserved memory and prefetchable

memory range for this Root Bridge.

0

Reserved

Memory

Alignment

Reserved memory alignment (0 - 31 bits). 1

Reserved

Prefetchable

Memory

Reserved prefetchable memory range for

this Root Bridge.

0

Reserved

Prefetchable

Memory

Alignment

Prefetchable memory alignment (0 - 31

bits).

1

64 bit Reserved

Prefetchable

Memory

64-bit reserved prefetchable memory

range for this Root Bridge.

0

64 bit Reserved

Prefetchable

Memory

Alignment

64-bit reserved prefetchable memory

alignment (0 - 31 bits).

1

Reserved I/O Reserved I/O (4K/8K/12K/16K/20K) range

for this Root Bridge.

0



ECRC Enables or disables ECRC (Error

Capabilities and Control Register).

Disable,

Enable

IODC

Configuration

Enable/Disable IODC (IO Direct Cache):

Generates snoops instead of memory

lookups, for remote InvItoM (IIO) and/or

WCiLF (cores).

KTI Option,

Auto, Enable for

Remote InvItoM

Hybrid Push,

InvItoM AllocFlow,

Enable for

Remote InvItoM

Hybrid

AllocNonAlloc,

Enable for

Remote InvItoM

and Remote

WViLF


5.5.2 IOAT Configuration


Disable TPH Disables TLP Processing Hint. No,

Yes

Prioritize TPH Prioritizes TPH. Disable,

Enable

Relaxed

Ordering

Enables or disables Relaxed Ordering.

Disable,

Enable


Sck 0/1 IOAT Config



DCA Enables or disables DCA for this specific

socket.

Disable,

Enable

IOAT Function 0/1/2/3/4/5/6/7 Item

DMA Enables or disables DMA for each CB

device.

Disable,

Enable

No Snoop Enables or disables No Snoop for each

CB device.

Disable,

Enable


5.5.3 Intel. VT for Directed I/O (VT-d)


Intel. VT for

Directed I/O

(VT-d)

Enables or disables Intel Virtualization

Technology for Directed I/O (VT-d) by

reporting the I/O device assignment to

VMM through DMAR ACPI Tables.

Enable,

Disable


5.5.4 Intel. VMD Technology

Intel. VMD for Volume Management Device on Socket 0/1


Intel. VMD for Volume

Management Device

Enables or disables Intel Volume

Management Device Technology.

Disable,

Enable


5.5.5 Intel. AIC Retimer/AIC SSD Technology (non-VMD)

Intel. AIC Retimer/AIC SSD on Socket 0/1



Intel. AIC

Retimer/AIC SSD

HW at PStack0

Announces Intel. AIC Retimer/AIC SSD HW at

PStack0(Port1A-1D). Overrides IOU0

bifurcation if required.

Disable,

Enable

Intel. AIC

Retimer/AIC SSD

HW at PStack1




Disable,

Enable

Intel. AIC

Retimer/AIC SSD

HW at PStack2




Disable,

Enable

5.5.6 IIO DFX Configuration


EV DFX Features Exposes IIO DFX devices and other CPU

devices like PMON.

Disable,

Enable

Ltssm Logger Enables or disables Ltssm Logger for PCIE

functionality.

Disable,

Enable

Intel. AIC

Retimer/AIC SSD

HW at PStack2




Disable,

Enable


Socket 0/1 Configuration

Socket 0/1 Dfx PcieBr(0/1/2/3/4/5)D00F0 – Port (0/1A/1C/2A/3A/MCP0/MCP1)



Gen3 Override

mode

Sets specific overrides in Gen3 features. UniPhy,

Manual,

Test Card

DN Tx Preset PCIe Downstream Tx Preset. Auto,

P0 (-6.0/0.0 dB),

P1 (-3.5/0.0 dB),

P2 (-4.5/0.0 dB),

P3 (-2.5/0.0 dB),

P4 ( 0.0/0.0 dB),

P5 ( 0.0/2.0 dB),

P6 ( 0.0/2.5 dB),

P7 (-6.0/3.5 dB),

P8 (-3.5/3.5 dB),

P9 ( 0.0/3.5 dB)

DN Rx Preset

Hint

PCIe Downstream Rx Preset Hint. Auto,

P0 (-6.0 dB),

P1 (-7dB),

P2 (-8 dB),

P3 (-9 dB),

P4 ( -10.0 dB),

P5 ( -11.0 dB),

P6 ( -12.0 dB)

UP Rx Preset PCIe Downstream Rx Preset. Auto,

P0 (-6.0/0.0 dB),,

P1 (-3.5/0.0 dB),

P2 (-4.5/0.0 dB),

P3 (-2.5/0.0 dB),

P4 ( 0.0/0.0 dB),

P5 ( 0.0/2.0 dB),

P6 ( 0.0/2.5 dB),

P7 (-6.0/3.5 dB),

P8 (-3.5/3.5 dB),

P9 ( 0.0/3.5 dB)

Inbound

Configuration

Enables or disables Inbound

configuration.

Disable,

Enable


Socket 0/1 Device Hide Menu



C-Stack

Devhide0/1/2/3/4/

5/6/7

If entire DEVHIDEx is 0, then register will not

be modified. If any byte is non-zero, then the

entire DEVHIDE register will be overridden

with these values (thus overriding any other

HIDE option in setup such as PCIe port hide

questions).

0

P-Stack0

Devhide0/1/2/3/4/

5/6/7






questions).

0

P-Stack1

Devhide0/1/2/3/4/

5/6/7






questions).

0



P-Stack2

Devhide0/1/2/3/4/

5/6/7






questions).

0

MCP0-Stack

Devhide0/1/2/3/4/

5/6/7






questions).

0

MCP1-Stack

Devhide0/1/2/3/4/

5/6/7






questions).

0


5.6 Advanced Power Management Configuration


use SPT

workarounds

If enabled, uses SPT workarounds - B2P cmd

MISC_WORKAROUND_ENABLE.

Enable,

Disable


5.6.1 CPU P State Control



WFR Uncore

GV Rate

Reduction

Auto: Enabled if WFR socket is detected in

system.

Enable: Always enables WFR Uncore GV

Rate Reduction.

Auto,

Disable,

Enable

Uncore Freq

Scaling (UFS)

Enables or disables autonomous uncore

frequency scaling.

Enable,

Disable

SpeedStep

(Pstates)

Enables or disables EIST (P-States). Enable,

Disable

Config TDP Selects the Config TDP level. Nominal,

Level 1,

Level 2

P State Domain Per Logical (ONE): indicates the P-state

domain for each logical proc in the system.

Per Package (ALL): all procs indicate the

same domain in the same package.

ALL,

ONE

EIST PSD

Function

Chooses HW_ALL/SW_ALL/SW_ANY in

_PSD return.

HW_ALL,

SW_ALL,

SW_ANY

SINGLE_PCTL Single PCTL Mode makes all cores in the

processor go to the most recent ratio

request.

Disable,

Enable

Single Power

Domain (SPD)

Single Power Domain aggregates the

request from all cores and the highest

request ratio is applied to all cores on the

processor.

Disable,

Enable

Boot

performance

mode

Selects the performance state that the

BIOS will set before OS hand off.

Max

Performance,

Max Efficient,

Set by Intel Node

Manager

Energy Efficient

Turbo

Disables Energy Efficient Turbo, MSR

0x1FC [19].

Enable,

Disable

Turbo Mode Enables or disables processor Turbo

Mode (requires EMTTM enabled too).

Enable,

Disable

CPU Flex Ratio

Override

Enables or disables CPU Flex Ratio

Programming.

Disable,

Enable


Perf P-Limit


Perf P-Limit

Differential

Parameter used to tune the remote socket

frequency to its lowest below the local

socket frequency.

Also impacts rate at which frequency

drops when feature disengages.

1

Perf P-Limit Clip Maximum floor value for perf P-limit. 31

Perf P-Limit

Threshold

Uncore frequency threshold above which

this socket will trigger the feature and start

trying to raise frequency of other sockets.

15

Perf P Limit Enables or disables Performance P-Limit. Enable,

Disable


5.6.2 Hardware PM State Control


Hardware

P-States

Disable: Hardware chooses a P-state

based on OS Request (Legacy P-States).

Native Mode: Hardware chooses a P-state

based on OS guidance.

Out of Band Mode: Hardware

autonomously chooses a P-state (no OS

guidance).

Native Mode,

Disable,

Out of Band Mode,

Native Mode with

No Legacy Support

Hardware PM

Interrupt

Enables or disables Hardware PM

Interrupt.

Disable,

Enable

EPP Enable If disabled, HW masks EPP in

CPUID[6].10 and uses EPB for EPP.

Enable,

Disable

APS rocketing Enables or disables the rocketing

mechanism in the HWP p-state selection

pcode algorithm. Rocketing enables the

core ratio to jump to max turbo

instantaneously as opposed to a smooth

ramp up.

Disable,

Enable



Scalability Enables or disables the use of scalability

in HWP pcode power efficiency

algorithms. Scalability is the measure of

estimated performance improvement for a

given increase in core frequency.

Disable,

Enable

PPO-Budget Enables or disables core parameter based

per core power budgeting. PPO-Budget

allocates power budget to cores based on

their scalability/EPP.

Disable,

Enable

5.6.3 Overclocking



Extreme Edition Enables or disables Extreme Edition

support.

Enable,

Disable

Overclocking Lock Enables or disables Overclocking. Enable,

Disable

TurboRatioLimit

0/1/2/3/4/5/6/7

User defined Ratio for TurboRatioLimits Msr(0x1AD), (range is 0-80).

0

TurboRatioCores

0/1/2/3/4/5/6/7

User defined core# for TurboRatioLimits Msr(0x1AE) (range is 0-ff).

ff

LOT26 Enable For HEDT *only*, select whether VR power

is turned off to empty DIMM channels.

Enable,

Disable


5.6.4 CPU C State Control


Autonomous Core

C-State

Autonomous Core C-State Control. Disable,

Enable

CPU C6 report Enables or disables CPU C6(ACPI C3)

report to OS.

Auto,

Enable,

Disable

Enhanced Halt

State (C1E)

Core C1E auto promotion Control. Takes

effect after reboot.

Enable,

Disable

OS ACPI Cx Reports CC3/CC6 to OS ACPI C2 or ACPI

C3.

ACPI C2,

ACPI C3


PKGc Interrupt Response Time


C_STATE_LATEN

CY_CONTROL_0

/1/2 VALID

This field qualifies the validity of the value

field in this register.

Disable,

Enable


5.6.5 Package C State Control


Package C State Package C State limit No Limit,

C0/C1 state,

C2 state,

C6 (non Retention)

state,

C6 (Retention) state,

Auto

C2C3TT Default = 0, means [AUTO]. C2 to

C3 Transition Timer, PPDN_INIT =

1:10:1:74 Bit[11:0].

0

PKG C-state Lat.

Neg.

MSR 1FCh Bit[30] =

PCH_NEG_DISABLE

Disable,

Enable

LTR IIO Input MSR 1FCh Bit[29] =

LTR_IIO_DISABLE.

Disable: Ignore IIO LTR input.

Ignore IIO LTR input,

Take IIO LTR input

MDLL Off Enable to shut down MDLL during

SR.

Auto, Enable, Disable


Latency Tolerance Requirement (LTR)


Snoop Latency

Override

Snoop Latency override Control. Disable,

Enable

Force Snoop

Latency Override

Control to ignore PCIe LTR and force the

Snoop Latency value.

Disable,

Enable

Snoop Latency

Multiplier

Override Value is multiplied by this field to

yield a time value.

0

Force Non-Snoop

Latency Override

Control to ignore PCIe LTR, and force the

Non-Snoop Latency value.

0

Non-Snoop

Latency Override

Non-Snoop Latency override Control.

Disable,

Enable

Non-Snoop

Latency Override

Forces PCODe to always use values

provided in SW_LTR_OVRD.

Disable,

Enable

Non-Snoop

Latency Multiplier

Override Value is multiplied by this field to

yield a time value.

0

Non-Snoop

Latency Value

Latency requirement for Non-Snoop

requests.

0


Program Pkg C-state Entry Criteria

CPU(0/1/2/3) SAPMCTL_CFG



IIO0_PKGC_CLK

_GATE_DISABLE

Used by BIOS to disable IIO Pkg C Clock

Gate from playing any role in TurnPLL.

Disable,

Enable

IIO1_PKGC_CLK

_GATE_DISABLE



Disable,

Enable

IIO2_PKGC_CLK

_GATE_DISABLE



Disable,

Enable

UPI01_PKGC_CL

K_GATE_DISABL

Used by BIOS to disable QPI01 Pkg C

Clock Gate from playing any role in

TurnPLL

Disable,

Enable

UPI23_PKGC_CL

K_GATE_DISABL

Used by BIOS to disable QPI02 Pkg C

Clock Gate from playing any role in

TurnPLL.

Disable,

Enable

MC1 PKGC CLK

GATE DISABLE

MC1 PKGC CLK GATE is disabled when in

PKG-C6 state.

Disable,

Enable

MC0 PKGC CLK

GATE DISABLE

MC0 PKGC CLK GATE is disabled when in

PKG-C6 state

Disable,

Enable



UPI01 PLL

Shutdown En

Enables UPI01 PLL Shutdown. Enable,

Disable

UPI23 PLL

Shutdown En

Enables UPI23 PLL Shutdown. Enable,

Disable

PCIe IIO0 PLL

Shutdown En

Enables PCIe PLL Shutdown. Enable,

Disable

PCIe IIO1 PLL

Shutdown En


Disable

PCIe IIO2 PLL

Shutdown En


Disable

MC0 PLLs

Shutdown En

Enables Memory PLLs Shutdown. Enable,

Disable

MC1 PLLs

Shutdown En

Enables Memory PLLs Shutdown.

Enable,

Disable

SetVID Decay

Disable

Used by BIOS to disable SETVID Decay to

enable use of VR12. NOTE: Socket 0

setting will be applied for all sockets.

Disable,

Enable

SAPMCTL_CFG

LOCK

If set, locks various PM registers. Enable,

Disable


5.6.6 CPU Thermal Management


PROCHOT

LOCK

Setting this bit will lock in xxPROCHOT#

response configurations including

ENABLE_BIDIR_PROCHOT,

DIS_PROCHOT_OUT,

VR_THERM_ALERT_DISABLE, and

PROCHOT_LOCK.

Enable,

Disable

PROCHOT

Modes

When a processor thermal sensor trips (either

core), the PROCHOT# will be driven. If

bi-direction is enabled, external agents can drive

PROCHOT# to throttle.

Input-only,

Both Input

and Output,

Output-only, Disable

Thermal

Monitor

Enables or disables the thermal monitor. Enable,

Disable

PROCHOT

RATIO

Controls the CPU response to an inbound

platform assertion of xxPROCHOT# by capping

to the programmed ratio. Default value is Pn.

The min allowed ratio is defined by

PLATFORM_INFO[MIN_OPERATING_RATIO].

0



TCC Activation

Offset

Offset from factory set TCC activation

temperature at which the Thermal Control Circuit

must be activated.

0

CPU T-state Control


Software

Controlled

T-States

Enables or disables the Software Controlled T-States.

Disable,

Enable


5.6.7 CPU – Advanced PM Tuning


SAPM Control MSR 1FCh Bit[22] =

PWR_PERF_TUNING_DISABLE_

SAPM_CTRL.

Enable,

Disable


Energy Perf BIAS


Power

Performance

Tuning

MSR 1FCh Bit[25] =

PWR_PERF_TUNING_CFG_MODE .

Enable – Use

IA32_ENERGY_PERF_BIAS input from

the core; Disable - Use alternate perf BIAS

input from

ENERGY_PERF_BIAS_CONFIG

OS Controls EPB,

BIOS Controls

EPB

PECI PCS EPB Controls whether PECI has control over

EPB

OS Controls EPB,

PECI controls EPB

using PCS

Dynamic

Loadline Switch

Dynamic Loadline Switch control. MSR

0x1FC[Bit24]

Enable,

Disable

Workload

Configuration

This allows optimization for the workload

characterization. Options are UMA and

NUMA.

UMA,

NUMA

Averaging Time

Window P0

This is used to control the effective

window of the average for C0 and P0 time

17



P0

TotalTimeThres

hold Low

The HW switching mechanism DISABLES

the performance setting (0) when the total

P0 time is less than this threshold.

23

P0

TotalTimeThres

hold High

The HW switching mechanism DISABLES

the performance setting (0) when the total

P0 time is greater than this threshold.

3A

5.6.8 Package Current Config


Current Limit

Override

0 - Default, do nothing;

1 - Manual, override Current limitation in 1/8 A

increments.

Disable,

Enable

Lock Indication Lock for CURRENT_LIMIT settings Move this

into the Config Above.

Enable,

Disable


5.6.9 EPB Override Control


UNCORE_PERF_PLI

MIT_OVRD_EN

Uncore Perf PLimit Override. Enable,

Disable

EET_OVERRIDE_

ENABLE

EET override. Disable,

Enable

IO_BW_PLIMIT_OVR

D_EN

IO BW PLimit Override. Disable,

Enable

IOM_APM_OVERRID

E_ENABLE

IOM APM Override. Disable,

Enable

UPI_APM_OVERRID

E_ENABLE

UPI APM Override. Disable,

Enable


5.6.10 SOCKET RAPL Config


FAST_RAPL_NST

RIKE_PL2_DUTY

_CYCLE

FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE

value between25 (10%) - 64 (25%)

64

Package RAPL

Limit MSR Lock

Enables or disables locking of Package RAPL

Limit MSR and a reset will be required to

unlock the register.

Disable,

Enable

Package RAPL

Limit CSR Lock

Enables or disables locking of Package RAPL

Limit CSR and a reset will be required to

unlock the register.

Enable,

Disable

PL1 Limit Enables or disables PL1. If this option is

disabled, BIOS will program the default values

for PL1 Power Limit and PL1 Time Window

Enable,

Disable

PL1 Power Limit PL1 Power Limit in Watts. The value may vary

from 0 to Fused Value. If the value is 0, the

fused value will be programmed. A value

greater than fused TDP value will not be

programmed.

0



PL1 Time Window PL1 value in seconds. The value may vary

from 0 to 56. Indicates the time window over

which TDP value should be maintained. If the

value is 0, the fused value will be

programmed.

1

PL2 Limit Enables or disables PL2. If this option is

disabled, BIOS will program the default values

for PL2 Power Limit and PL2 Time Window.

Enable,

Disable

PL2 Power Limit PL2 Power Limit in Watts. The value may vary

from 0 to Fused Value. If the value is 0, BIOS

programs 125% * TDP

0

PL2 Time Window PL2 value in seconds. The value may vary

from 0 to 56. Indicates the time window over

which TDP value should be maintained. If the

value is 0, the fused value will be

programmed.

1


5.6.11 PMAX Config Configuration


PMAX Config Sign Controls whether PMAX Config offset is a

positive or negative value.

Positive,

Negative

PMAX Config Offset Input decimal correction factor to program.

Valid input values are 0 to 15. Will be

positive or negative based on PMAX

Config Sign value.

0


5.6.12 ACPI Sx State Control


ACPI S3 Controls the ACPI S3 State. Enable,

Disable

ACPI S4 Controls the ACPI S4 State. Enable,

Disable


5.6.13 Memory Power & Thermal Control


MEMHOT

Throttling

Mode

Configures MEMHOT.

Input and Output Modes: Mem Hot

Sense Therm Throt or Mem Hot

Output Therm Throt.

Input-only,

Disable,

Output-only,

Input and Output,

Enabled

MEMHOT

Output

Throttling

Mode Options

Configures MEMHOT,

Output Mode options: Enables or

disables the Throt Output high, mid

and low bit fields.

Enable only temphi,

Disable,

Enable only temphi & mid,

Enable only temphi, mid

and low

.


DRAM RAPL Configuration


Override

BW_LIMIT_TF

Allows custom tuning of BW_LIMIT_TF when

DRAM RAPL is enabled.

0

DRAM RAPL

Extended Range

Selects the DRAM RAPL Extended Range. Enable,

Disable

CMS ENABLE

DRAM PM

CMS ENABLE DRAM PM. Enable,

Disable


Memory Thermal


Throttling Mode Configures the thermal throttling mode. CLTT,

Disable, OLTT,

CLTT with PECI

EN_MEMTRIP If set to Disable, processor will ignore

MEMtrip. If set to Enable, processor will

include MEMtrip in ThermTrip tree.

Disable,

Enable


Memory Power Savings Advanced Options


CKE Throttling Configures CKE Throttling. Auto,

Manual

SREF Feature SREF Feature Auto,

Manual

PKGC SREF EN PKGC SREF EN Enable,

Disable


6. Server Mgmt


BMC Support Enables or disables interfaces to

communicate with BMC.

Enabled,

Disabled

FRB-2 Timer Enables or disables FRB-2 timer (POST

timer).

Enabled,

Disabled

FRB-2 Timer

timeout

Enter a value between 3 to 6 minutes as the

FRB-2 timer expiration value.

6 minutes,

3 minutes,

4 minutes,

5 minutes

FRB-2 Timer Policy

Configures how the system should respond

if the FRB-2 timer expires. Not available if

FRB-2 timer is disabled.

Reset,

Do Nothing,

Power Down


6.1 System Event Log

.Parameter Description Option

When SEL is

Full

Chooses the option for reactions to

a full SEL.

Do Nothing,

Erase at POST

Log EFI Status

Codes

Disables the logging of EFI Status

Codes or logs only error code or

only progress code or both.

Error code,

Disabled,

Both,

Progress code


6.2 BMC network Configuration


Configuration

Address

Configures LAN channel parameters

statically or dynamically (by BIOS or BMC).

Unspecified option will not modify any BMC

network parameters during BIOS phase.

The setting will change to Unspecified after

system resets to prevent conflicting with

BMC network configuration that the user set

by LAN.

Unspecified,

Static,

DHCP


7. Security The BIOS uses passwords to prevent unauthorized tampering with the server

setup. BIOS supports both Administrator and User passwords. To access

this screen from the Main screen, select the Security option.


Administrator

Password

Set Administrator Password


8. Boot


Setup Prompt

Timeout

(Variable)

Number of seconds to wait for setup

activation key. 65535(0xFFFF) means

indefinite waiting.

1

Bootup

NumLock State

Sets the keyboard NumLock state. On,

Off

Quiet Boot Enables or disables the Quiet Boot

option.

Disabled,

Enabled

Boot option

filter

This option controls Legacy/UEFI ROMs

priority.

UEFI,

Legacy

Boot Option

Priorities

Sets the system boot order.


9. Save & Exit The Save & Exit screen allows the user to choose whether to save or discard

the configuration changes made on other Setup screens. It also allows the

user to restore the BIOS Settings to the factory defaults or to save or restore

them to a set of user-defined default values.

Parameter Description

Save Changes and

Reset

Reset the system after saving the changes

Discard Changes and

Reset

Reset system setup without saving any changes

Save Changes Save Changes done so far to any of the setup options

Restore Defaults Restore/Load Default values for all the setup options

Save as User Defaults Save the changes done so far as User Defaults

Restore User Default Restore the User Defaults to all the setup options

Boot Override Select boot device which can override the original boot

order.


10. POST Code Table

10.1 PEI Phase

A. Progress Codes

Normal

Code Description

0x10 PEI Core is started

0x11 Pre-memory CPU initialization is started

0x15 Pre-memory North Bridge initialization is started

0x19 Pre-memory South Bridge initialization is started

0x2B Memory initialization. Serial Presence Detect (SPD) data

reading

0x2C Memory initialization. Memory presence detection

0x2D Memory initialization. Programming memory timing information

0x2E Memory initialization. Configuring memory

0x2F Memory initialization

0x31 Memory Installed

0x37 Post-Memory North Bridge initialization is started

0x3B Post-Memory South Bridge initialization is started

0x4F DXE IPL is started

0x60 DXE Core is started


Recovery

Code Description

0xF0 Recovery condition triggered by firmware (Auto recovery)

0xF1 Recovery condition triggered by user (Forced recovery)

0xF2 Recovery process started

0xF3 Recovery firmware image is found

0xF4 Recovery firmware image is loaded

B. Error Codes

Normal

Code Description

0x50 Memory initialization error. Invalid memory type or

incompatible memory speed

0x51 Memory initialization error. SPD reading has failed

0x52 Memory initialization error. Invalid memory size or memory

modules do not match

0x53 Memory initialization error. No usable memory detected

0x54 Unspecified memory initialization error

0x55 Memory not installed

0x56 Invalid CPU type or Speed

0x57 CPU mismatch

0x58 CPU self-test failed or possible CPU cache error

0x59 CPU micro-code is not found or micro-code update is failed

0x5A Internal CPU error

0x5B Reset PPI is not available


Recovery

Code Description

0xF8 Recovery PPI is not available

0xF9 Recovery capsule is not found

0xFA Invalid recovery capsule

10.2 DXE Phase

A. Progress Codes

Code Description

0x60 DXE Core is started

0x61 NVRAM initialization

0x62 Installation of the South Bridge Runtime Services

0x63 CPU DXE initialization is started

0x68 PCI host bridge initialization

0x69 North Bridge DXE initialization is started

0x6A North Bridge DXE SMM initialization is started

0x70 South Bridge DXE initialization is started

0x71 South Bridge DXE SMM initialization is started

0x72 South Bridge devices initialization

0x78 ACPI module initialization

0x79 CSM initialization

0x90 Boot Device Selection (BDS) phase is started

0x91 Driver connecting is started

0x92 PCI Bus initialization is started

0x93 PCI Bus Hot Plug Controller Initialization

0x94 PCI Bus Enumeration

0x95 PCI Bus Request Resources


Code Description

0x96 PCI Bus Assign Resources

0x97 Console Output devices connect

0x98 Console input devices connect

0x99 Super IO Initialization

0x9A USB initialization is started

0x9B USB Reset

0x9C USB Detect

0x9D USB Enable

0xA0 IDE initialization is started

0xA1 IDE Reset

0xA2 IDE Detect

0xA3 IDE Enable

0xA4 SCSI initialization is started

0xA5 SCSI Reset

0xA6 SCSI Detect

0xA7 SCSI Enable

0xA8 Setup Verifying Password

0xA9 Start of Setup

0xAB Setup Input Wait

0xAD Ready To Boot event

0xAE Legacy Boot event

0xAF Exit Boot Services event

0xB0 Runtime Set Virtual Address MAP Begin

0xB1 Runtime Set Virtual Address MAP End

0xB2 Legacy Option ROM Initialization

0xB3 System Reset

0xB4 USB hot plug

0xB5 PCI bus hot plug

0xB6 Clean-up of NVRAM

0xB7 Configuration Reset (reset of NVRAM settings)


B. Error Codes

Code Description

0xD0 CPU initialization error

0xD1 North Bridge initialization error

0xD2 South Bridge initialization error

0xD3 Some of the Architectural Protocols are not available

0xD4 PCI resource allocation error. Out of Resources

0xD5 No Space for Legacy Option ROM

0xD6 No Console Output Devices are found

0xD7 No Console Input Devices are found

0xD8 Invalid password

0xD9 Error loading Boot Option

0xDA Boot Option is failed

0xDB Flash update is failed

0xDC Reset protocol is not available


10.3 DIMM Error Code POST

For the rule of looping display when DIMM failure happens during the boot

sequence, the BIOS shall initialize and test each DIMM module. If a module

fails during initialization or does not pass the BIOS test, the following POST

codes should flash on the debug card to indicate which DIMM has failed.

The first hex character indicates which CPU interfaces to the DIMM module;

the second hex character indicates the number of the DIMM module. POST

code will also display major code and minor error codes from Intel memory

reference code. The display sequence will be “00”, DIMM location, Major

code and Minor code with 1 second delay for every code displayed. The

BIOS shall repeat the display sequence indefinitely to allow time for a

technician to service the system.

DIMM Error Code

Socket/Channel Code Result

CPU0 (Channel 0 & 1)

A0 CPU 0 Channel 0 DIMM 0 (furthest) Failure

A1 CPU 0 Channel 0 DIMM 1 Failure

A2 CPU 0 Channel 1 DIMM 0 Failure

A3 CPU 0 Channel 1 DIMM 1 (closest) Failure


MRC Warning Codes

Warning Descriptions Major

Code

Minor

Code

WARN_RDIMM_ON

_UDIMM

RDIMM\LRDIMM is plugged into a

UDIMM only board 01h

WARN_UDIMM_ON

_RDIMM

UDIMM is plugged into a

RDIMM\LRDIMM only board 02h

WARN_SODIMM_O

N_RDIMM

SODIMM is plugged into a

RDIMM/LRDIMM only system 03h

WARN_4Gb_FUSE Support for 4Gb devices has been

fused off 04h

WARN_8Gb_FUSE Support for 8Gb devices has been

fused off 05h

WARN_IMC_DISAB

LED

IMC was disabled by MRC 06h

WARN_DIMM_COM

PAT

DIMM is not compatible with the IMC

memory controller. 07h

WARN_DIMM_COM

PAT_MINOR_X16_

COMBO

RESERVED for future use

01h

WARN_DIMM_COM

PAT_MINOR_MAX_

RANKS

Max number of ranks exceeded on the

channel.

02h

WARN_DIMM_COM

PAT_MINOR_QR

QR DIMM is not at Slot0 while SR/DR

DIMMs are present in the channel. 03h

WARN_DIMM_COM

PAT_MINOR_NOT_

SUPPORTED

Incompatible DDR3 DIMM module.

04h

WARN_RANK_NUM The number of ranks on this device is

not supported

05h

WARN_TOO_SLOW This DIMM does not support

DDR3-1067 or higher.

06h

WARN_DIMM_COM

PAT_MINOR_ROW_

ADDR_ORDER

LRDIMM A16 usage is not symmetrical

on channel.

07h

WARN_CHANNEL_

CONFIG_NOT_SUP

PORTED

configuration is not supported. Map out

this channel.

08h



Code

Minor

Code

WARN_CHANNEL_

MIX_ECC_NONEC

C

ECC and non ECC DIMMs were

mixed. ECC is disabled for the entire

system if one DIMM is found that does

not support it.

09h

WARN_DIMM_VOLT

AGE_NOT_SUPPO

RTED

DDR4 voltage not supported 0Ah

WARN_DIMM_COM

PAT_TRP_NOT_SU

PPORTED

RESERVED for future use 0Bh

WARN_DIMM_NON

ECC

0Ch

WARN_DIMM_COM

PAT_3DS_RDIMM_

NOT_SUPPORTED

0Dh

WARN_RANK_COU

NT_MISMATCH

0Eh

WARN_DIMM_SKU

_MISMATCH

0Fh

WARN_LOCKSTEP

_DISABLE

Lockstep Channel mode was

requested but could not be honored 09h

WARN_LOCKSTEP

_DISABLE_MINOR_

RAS_MODE

Unable to enable Lockstep mode

because ECC is disabled. Switch to

independent channel mode.

01h

WARN_LOCKSTEP

_DISABLE_MINOR_

MISMATCHED

Mismatched DIMM pairs found across

channels. Switched to independent

channel mode. mrcHost.RASMode

contains the bitmap of supported RAS

modes for the current DIMM

population.

02h

WARN_LOCKSTEP

_DISABLE_MINOR_

MEMTEST_FAILED

Memory test failed 03h

WARN_USER_DIM

M_DISABLE

DIMM was disabled by MRC. See

minor code below for specific reasons.

0AH



Code

Minor

Code

WARN_USER_DIM

M_DISABLE_QUAD

_AND_3DPC

3-DIMM-Per-Channel and Quad Rank

DIMM were found on the same CPU

socket (unsupported config). Channel

with Quad Rank DIMM is disabled by

MRC.

01h

WARN_USER_DIM

M_DISABLE_MEMT

EST

DIMM was disabled by the MRC as a

result of previous DIMM in the channel

being disabled due to error (the DIMM

itself is not necessarily bad)

02h

WARN_MEMTEST_

DIMM_DISABLE

DIMM was disabled due to MemTest

errors. 0Bh

WARN_MIRROR_DI

SABLE

Mirror mode was requested but could

not be honored. Memtest failure

resulted in a channel being disabled.

Switch to Independent channel mode.

0Ch

WARN_MEM_LIMIT IMC memory decode limit was reached

before all memory could be allocated. 0Dh

WARN_MIRROR_DI

SABLE_MINOR_RA

S_DISABLED

Unable to enable Mirror mode because

ECC is disabled. Switch to


01h

WARN_MIRROR_DI

SABLE_MINOR_MI

SMATCH


channels. Switch to independent

channel mode.

02h

WARN_MIRROR_DI

SABLE_MINOR_ME

MTEST

Mirror mode was disabled due to

memory test failure. 03h

WARN_INTERLEAV

E_FAILURE

Interleave mode failure 0Eh

WARN_SAD_RULE

S_EXCEEDED

Number of SAD rules exceeds 01h

WARN_TAD_RULE

S_EXCEEDED

Number of TAD rules exceeds 02h

WARN_RIR_RULES

_EXCEEDED

Number of RIR rules exceeds 03h

WARN_TAD_OFFS

ET_NEGATIVE

Negative TAD offset 04h



Code

Minor

Code

WARN_TAD_LIMIT_

ERROR

TAD Limit > SAD Limit 05h

WARN_INTERLEAV

E_3WAY

Interleave 3 Way 06h

WARN_A7_MODE_

AND_3WAY_CH_IN

TERLV

RESERVED for future use

07h

WARN_INTERLEAV

E_EXCEEDED

08h

WARN_DIMM_CAP

ACITY_MISMATCH

09h

WARN_DIMM_POP

ULATION_MISMAT

CH

0Ah

WARN_NM_MAX_S

IZE_EXCEEDED

0Bh

WARN_NM_SIZE_B

ELOW_MIN_LIMIT

0Ch

WARN_NM_SIZE_N

OT_POWER_OF_T

WO

0Dh

WARN_MAX_INTE

RLEAVE_SETS_EX

CEEDED

0Eh

WARN_NGN_DIMM

_COMM_FAILED

0Fh

WARN_DIMM_COM

M_FAILED

0Fh

WARN_MINOR_DI

MM_COMM_FAILE

D_TIMEOUT

01h

WARN_MINOR_DI

MM_COMM_FAILE

D_STATUS

02h



Code

Minor

Code

WARN_SPARE_DIS

ABLE

Unable to enable Spare mode because

ECC is disabled. Switch to



channels. Switch to independent

channel mode.

10h

WARN_PTRLSCRB

_DISABLE

Patrol Scrub was disabled 11h

WARN_UNUSED_M

EMORY

Unused memory is populated on

channel 2 in Lockstep or Mirroring

mode.

12h

WARN_UNUSED_M

EMORY_MIRROR


channel 2 in mirror mode 01h

WARN_UNUSED_M

EMORY_LOCKSTE

P


channel 2 in Lockstep mode 02h

WARN_RD_DQ_DQ

S

A Read DQ/DQS failure has occurred

during training. The failing Channel

was disabled

13h

WARN_RD_RCVEN

A tRLCoarse failure has occurred

during DDR training. The failing

Channel was disabled.

14h

WARN_ROUNDTRI

P_EXCEEDED

Round Trip delay of %d exceeds the

limit of %d 01h

WARN_WR_LEVEL A write leveling failure has occurred

during training. 15h

WARN_WR_FLYBY

_CORR

Fault Parts Tracking write Fly-by

correctable error 00h

WARN_WR_FLYBY

_UNCORR

Fault Parts Tracking write Fly-by

uncorrectable error 01h

WARN_WR_FLYBY

_DELAY

RESERVED for future use 02h

WARN_WR_DQ_D

QS

A write DQ/DQS failure has occurred

during training. 16h

WARN_DIMM_POP

_RULE

Improper DIMM population 17h



Code

Minor

Code

WARN_DIMM_POP

_RULE_MINOR_OU

T_OF_ORDER

DIMM is populated out of order and

that it will not be used. If slot 0 is empty

then the channel gets disabled, if slot 1

is empty but slot 0 and slot 2 are

populated then MRC will try to boot

with the DIMM in slot 0 while ignoring

the DIMM in slot 2.

01h

WARN_DIMM_POP

_RULE_MINOR_IN

DEPENDENT_MOD

E

Lockstep/Mirror mode not enabled due

to unused DIMM on Channel 2, and

MRC input RAS_TO_INDP_EN = 1.

Switch to Independent Channel mode.

02h

WARM_DIMM_POP

_RUL_2_AEP_FOU

ND_ON_SAME_CH

03h

WARM_DIMM_POP

_RUL_MINOR_MIX

ED_RANKS_FOUN

D

04h

WARN_DIMM_POP

_RUL_UDIMM_POP

ULATION

20h

WARN_DIMM_POP

_RUL_RDIMM_POP

ULATION

40h

WARN_DIMM_POP

_RUL_LRDIMM_DU

AL_DIE_POPULATI

ON

80h

WARN_DIMM_POP

_RUL_LRDIMM_3D

S_POPULATION

100h

WARN_DIMM_POP

_RUL_RDIMM_3DS

_POPULATION

200h

WARN_CLTT_DISA

BLE

CLTT was requested but could not be

honored 18h



Code

Minor

Code

WARN_CLTT_MINO

R_NO_TEMP_SEN

SOR

A DIMM without Temp Sensor was

found 01h

WARN_CLTT_MINO

R_CIRCUIT_TST_F

AILED

A DIMM failed Temp Sensor circuit test

02h

WARN_THROT_INS

UFFICIENT

Indicates throttling is not sufficient for

this DIMM due to MRC calculation. 19h

WARN_CLTT_DIMM

_UNKNOWN

A DIMM of an unknown category is

found when looking up a pre-defined

category table (DIMM type, rawcard,

heat spreader, planner, etc). Use a

default category (category 11 or 27

depending on DIMM type)

1Ah

WARN_DQS_TEST DQS training failure encountered 1Bh

WARN_MEM_TEST Hardware Memtest failed and the

DIMM is disabled 1Ch

WARN_CLOSED_P

AGE_OVERRIDE

Page override 1Dh

WARN_DIMM_VRE

F_NOT_PRESENT

DIMM Verf controller circuit (DCP) not

detected 1Eh

WARN_EARLY_RID 1Fh

WARN_EARLY_RID

_UNCORR

01h

WARN_EARLY_RID

_CYCLE_FAIL

02h

WARN_LV_STD_DI

MM_MIX

Low voltage DDR3 problem

encountered. 20h

WARN_LV_2QR_DI

MM

2 LV QR detected 21h

WARN_LV_3DPC LV 3 DPC detected 22h

WARN_CMD_ADDR

_PARIT_ERR


WARN_DQ_SWIZZ

LE_DISC

24h



Code

Minor

Code

WARN_DQ_SWIZZ

LE_DISC_UNCORR

01h

WARN_COD_HA_N

OT_ACTIVE

COD Enabled but memory not behind

each HA 25h

WARN_CMD_CLK_

TRAINING

Eye width is too small. Channel is

disabled. 26h

WARN_CMD_PI_G

ROUP_SMALL_EY

E

01h

WARN_INVALID_B

US

27h

WARN_INVALID_FN

V_OPCODE

28h

WARN_MEMORY_T

RAINING

29h

WARN_CTL_CLK_L

OOPBACK_TRAINI

NG

02h

WARN_ODT_TIMIN

G_OVERFLOW

03h

WARN_NO_DDR_M

EMORY

2Ah

WARN_NO_MEMO

RY_MINOR_NO_M

EMORY

01h

WARN_NO_MEMO

RY_MINOR_ALL_C

H_DISABLED

02h

WARN_NO_MEMO

RY_MINOR_ALL_C

H_DISABLED_MIXE

D

03h

WARN_ROUNDTRI

P_ERROR

2Bh



Code

Minor

Code

WARN_RCVNTAP_

CMDDELAY_EXCE

EDED

01h

WARN_MEMORY_

MODEL_ERROR

2Ch

WARN_SNC24_MO

DEL_ERROR

01h

WARN_QUAD_HEM

I_MODEL_ERROR

02h

WARN_SNC24_DIM

M_POPULATION_M

ISMATCH

03h

WARN_SNC24_INC

OMPATIBLE_DDR_

CAPACITY

04h

WARN_SNC24_INC

OMPATIBLE_MCDR

AM_CAPACITY

05h

WARN_MCDRAM_

CONFIG_NOT_SUP

PORTED

06h

WARN_SNC24_TIL

E_POPULATION_MI

SMATCH

07h

WARN_OVERRIDE

_MEMORY_MODE

2Dh

WARN_OVERRIDE

_TO_FLAT_NO_MC

DRAM_MEMORY

01h

WARN_OVERRIDE

_TO_FLAT_NO_DD

R_MEMORY

02h

WARN_OVERRIDE

_TO_HYBRID_CAC

HESIZE_1_2

03h



Code

Minor

Code

WARN_MEM_INIT 2Eh

WARN_SENS_AMP

_TRAINING

2Fh

WARN_SENS_AMP

_CH_FAILIURE

01h

WARN_FPT_CORR

ECTABLE_ERROR

FTP correctable error 30h

WARN_FPT_UNCO

RRECTABLE_ERR

OR

FTP uncorrectable error

31h

WARN_FPT_MINO

R_WR_FLYBY

FTP: failed Write FlyBy 00h

WARN_FPT_MINO

R_RD_DQ_DQS

FTP: failed Read DqDqs 13h

WARN_FPT_MINO

R_RD_RCVEN

Receive Enable training failure 14h

WARN_FPT_MINO

R_WR_LEVEL

FTP failed Write Leveling 15h

WARN_FPT_MINO

R_WR_DQ_DQS

FTP: failed Write DqDqs 16h

WARN_FPT_MINO

R_DQS_TEST

FTP: failed DQS Test 1Bh

WARN_FPT_MINO

R_MEM_TEST

FTP minor correctable memtest 1Ch

WARN_FPT_MINO

R_LRDIMM_TRAINI

NG

FTP minor LRDIMM training

24h

WARN_FPT_MINO

R_VREF_TRAINING

Unable to find the txvref for the eye.

Warning for both correctable and

uncorrectable errors. Channel is

disabled.

25h

WARN_NO_SUFFIC

IENT_SPARERANK

32h

WARN_TWR_LIMIT

_REACHED

01h



Code

Minor

Code

WARN_TWR_LIMIT

_ON_LOCKSTEP_C

H

02h

WARN_MEM_LIMIT 33h

WARN_RT_DIFF_E

XCEED

34h

WARN_PPR_FAILE

D

35h

WARN_REGISTER_

OVERFLOW

36h

WARN_SWIZZLE_D

ISCOVERY_TRAINI

NG

37h

WARN_SWIZZLE_P

ATTERN_MISMATC

H

01h

WARN_WRCRC_DI

SABLE

38h

WARN_TRAIL_ODT

_LIMIT_REACHED

01h

WARN_FNV_BSR 39h

WARN_DT_ERROR 01h

WARN_MEDIA_RE

ADY_ERROR

02h

WARN_ADDDC_DI

SABLE

3Ah

WARN_SDDC_DIS

ABLE

3Bh

WARN_FW_OUT_O

F_DATE

3Ch

WARN_FW_CLK_M

OVEMENT

00h

WARN_MEM_CON

FIG_CHANGED

Timing overrides are enabled but the

DIMM configuration has changed.

Memory overrides will be disabled

40h



Code

Minor

Code

WARN_MEM_OVE

RRIDE_DISABLED

If MEM_OVERRIDE_EN is enabled

but the DIMM configuration has

changed, this warning indicates that

the MRC has disabled memory

overrides.

01h

WARN_MCA_UNC

ORRECTABLE_ER

ROR

MC uncorrectable error caused

machine check 50h

WARN_DM_TEST_

ERROR_CODE

Major DMT error 60h

WARN_DM_TEST_

PARSE_ERROR_MI

NOR_CODE

Parse error

01h

WARN_DM_TEST_

CONFIGURATIONE

RROR_MINOR_CO

DE

Mix DIMM configuration unsupported

on DRAM maintenance test 02h

WARN_DM_TEST_

EXECUTIONERRO

R_MINOR_CODE

Couldn't calculate number loopcounts

for subsequences 03h

WARN_FPGA_NOT

_DETECTED

75h

MRC Fatal Error Codes

Fatal Error

Nomenclature Descriptions

Major

Code

Minor

Code

ERR_NO_MEMORY 0E8h

ERR_NO_MEMORY_

MINOR_NO_MEMOR

Y

1) No memory was detected via SPD

read. No warning log entries available.

2) invalid config that causes no

operable memory. Refer to warning log

entries for details.

01h

ERR_NO_MEMORY_

MINOR_ALL_CH_DIS

ABLED

Memory on all channels of all sockets

are disabled due to hardware memtest

error

02h


Fatal Error


Major

Code

Minor

Code

ERR_NO_MEMORY_

MINOR_ALL_CH_DIS

ABLED _MIXED

No memory installed. All channels are

disabled.

03h

ERR_LT_LOCK Memory locked due to LT “Bricking” 0E9h

ERR_DDR_INIT DDR3 training did complete

successfully

0EAh

ERR_RD_DQ_DQS Error on read DQ/DQS init 01h

ERR_RC_EN Error on Receive Enable 02h

ERR_WR_LEVEL Error on Write Leveling 03h

ERR_WR_DQ_DQS Error on write DQ/DQS 04h

ERR_MEM_TEST Memory test failure 0EBh

ERR_MEM_TEST_MI

NOR_SOFTWARE

Software memtest failure. 01h

ERR_MEM_TEST_MI

NOR_HARDTWARE

Hardware memtest failed. 02h

ERR_MEM_TEST_MI

NOR_LOCKSTEP_M

ODE

Hardware Memtest failure in Lockstep

Channel mode requiring a channel to

be disabled. This is a fatal error which

requires a reset and calling MRC with

a different RAS mode to retry.

03h

ERR_VENDOR_SPE

CIFIC

RESERVED for future use 0ECh

ERR_DIMM_PLL_LO

CK_ERROR

01h

ERR_DIMM_COMPAT UDIMMs and RDIMMs are both

present DIMM vendor-specific errors

0EDh

ERR_MIXED_MEM_T

YPE

Different DIMM types are detected

installed in the system

01h

ERR_INVALID_POP Violation of population rules. 02h

ERR_INVALID_POP_

MINOR_QR_AND_3R

D_SLOT

The 3rd DIMM slot can’t be populated

when QR DIMMs are installed.

03h


Fatal Error


Major

Code

Minor

Code

ERR_INVALID_POP_

MINOR_UDIMM_AND

_ 3RD_SLOT

UDIMMs and SODIMMs are not

supported in the third

DIMM slot

04h

ERR_INVALID_POP_

MINOR_UNSUPPORT

ED_VOLTAGE

Unsupported DIMM Voltage 05h

ERR_DDR3_DDR4_M

IXED

DDR3 and DDR4 DIMMs cannot be

mixed.

06h

ERR_MIXED_SPD_T

YPE

Mixing of 256 byte and 512 byte SPD

devices is not supported

07h

ERR_MISMATCH_DI

MM_TYPE

Memory type mismatch 08h

ERR_MRC_COMPATI

BILITY

Number of HAs found in system

greater than MAX_HA defined in MRC

build

0EEh

ERR_MRC_DIRE_NO

NECC


ERR_MRC_STRUCT

Indicates a CLTT table structure error.

A DIMM is populated in the 3rd slot

when quad rank DIMM is present in the

channel

0EFh

ERR_INVALID_BOOT

_MODE

Boot mode is unknown 01h

ERR_INVALID_SUB_

BOOT_MODE

Sub boot mode is unknown 02h

ERR_INVALID_HOST

_ADDR

03h

ERR_SET_VDD 0F0h

ERR_UNKNOWN_VR

_MODE

Invalid VR mode, unable to set DRAM

VDD

01h

ERR_IOT_MEM_BUF

FER

ERROR: IOT Memory Buffer has not

been allocated memory

0F1h

ERR_RC_INTERNAL 0F2h

ERR_RC_INTERNAL

_HBM

01h


Fatal Error


Major

Code

Minor

Code

ERR_INVALID_REG_

ACCESS

0F3h

ERR_INVALID_WRIT

E_REG_BDF

01h

ERR_INVALID_WRIT

E_REG_OFFSET

02h

ERR_INVALID_READ

_REG_BDF

03h

ERR_INVALID_READ

_REG_OFFSET

04h

ERR_SET_MC_FREQ F3h

ERR_UNSUPPORTE

D_MC_FREQ

01h

ERR_READ_MC_FRE

Q

0F4h

ERR_NOT_ABLE_RE

AD_MC_FREQ

01h

ERR_DIMM_CHANNE

L

70h

ERR_BIST_CHECK 74h

ERR_SMBUS F5h

TSOD_POLLING_EN

ABLED_READ

01h

TSOD_POLLING_EN

ABLED_WRITE

02h

SV300G3 BIOS User Manual UM_V0.7_20180212.pdf · 8 Wiwynn SV300G3 BIOS User Manual 1.3 Menu Bar The...

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