Susceptibility of Integrated Circuits to Electrostatic Discharge

International Journal of Advancements in Research & Technology, Volume 1, Issue 4, September-2012 1 ISSN 2278-7763

Copyright © 2012 SciResPub. IJOART

Susceptibility of Integrated Circuits to Electrostatic Discharge 1Rajashree Narendra,

2M.L. Sudheer,

3D.C. Pande

1Department of TCE, BNMIT, Bangalore, India. 2Department of ECE, UVCE, Bangalore, India. 3EMI/EMC Group, LRDE, Bangalore, India. Email: [email protected]

ABSTRACT

The components that are considered fairly rugged can be damaged by electrostatic discharge (ESD). Bipolar transistors, the ear-liest of the solid state amplifiers, are not immune to ESD, though less susceptible. Devices manufactured using metal oxide sem-iconductor (MOS) technology can be easily damaged due to ESD but some of the newer high speed components can be ruined with as little as 3 volts. The integrated circuits (IC) are susceptible to ESD due to its small size and unavailability of larger area to dissipate the excess energy. The susceptibility of IC’s can be determined by various ESD stress tests. The different ESD stress modes on an input or output pin which is Pin-to-VSS, Pin-to-VDD are used to test an IC. The IC after ESD stresses may undergo damage not only in the input/output circuits or devices, but also in the internal circuits. The effects of ESD on various logic gates belonging to both transistor-transistor logic (TTL) and Complementary MOS (CMOS) logic families have been studied. The comparison between TTL and CMOS logic gates reveal that CMOS devices are more susceptible to ESD than TTL devices. Keywords : Logic gates, ESD stress modes, TTL, CMOS, Susceptibility

1 INTRODUCTION

lectrostatic Discharge (ESD) phenomenon happens due to

the different electrostatic potentials between two or more

objects, and electrical overstress (EOS) takes place due to the

electrical event that is outside the specified range of the device

under test (DUT). Devices are usually damaged by EOS/ESD

[1] via the rapidly generated heat or the rapidly created strong

electrical field. The latent or fatal failures on a silicon chip are

caused by an electrostatic discharge or electrical overstress

event.

Damage to components can, and usually do, occur when

the part is in the ESD path. Many parts in the circuits are very

robust, can handle the discharge and undergo only upsets.

But if a part has a small or thin geometry as part of their phys-

ical structure then the voltage can break down that part of the

semiconductor. Currents during the ESD events become quite

high, but are in the nanosecond to microsecond time frame.

Part of the component is left permanently damaged by this,

which can cause two types of failure modes. Catastrophic is

the easy one, leaving the part completely nonfunctional. The

other can be much more serious. Latent damage may allow the

problem component to work for hours, days or even months

after the initial damage before catastrophic failure. Many

times these parts are referred to as "walking wounded", since

they are working but bad. If these components end up in a life

support role, such as medical or military use, then the conse-

quences can be grim.

There are two ways to reduce IC failures due to ESD. One

is to ensure proper handling and grounding of personnel and

equipment during manufacturing and usage of packaged

chips, i.e., to prevent ESD events from occurring. The other

approach is to connect protection circuits [2-5] (almost always

on-chip) to the pins of a packaged IC which will divert high

currents away from the internal circuitry and clamp high volt-

ages during an ESD stress.

The integrated circuits (IC) are susceptible to ESD due to its

small size and unavailability of larger area to dissipate the

excess energy. The susceptibility of IC’s can be determined

by various ESD stress [6-8]. The different ESD stress modes on

an input or output pin which is Pin-to-VSS, Pin-to-VDD are used

to test an IC. Moreover, ESD current could enter into any pin

and go out of any pin of an IC. To practically verify the whole

chip ESD reliability, two additional ESD test conditions are

considered. These two test conditions are pin-to pin ESD

stress and the VDD to VSS ESD stress.

2 ESD TEST FOR IC

The ESD test is conducted for the logic gates belonging to

the TTL and CMOS logic families. All the logic gates like the

OR, NOR, AND, NAND and XOR for the two logic families

are tested. There are four pin combinations for ESD test on an

IC product which are known as Pin-to-VSS, Pin-to-VDD, Pin-to-

Pin and VDD-to-VSS. The Pin-to-VSS stress, shown in Fig. 1(a), is

to apply the ESD stress on the pin under test (PUT) when the

VSS pins are connected to ground. The Pin-to-VDD stress, which

is shown in Fig. 1(b), is to apply the ESD stress on the PUT

when the VDD pins are connected to ground. The Pin-to-Pin

stress, which is shown in Fig. 1(c), is to apply the ESD stress

on the PUT when the other pins, except VDD/VSS pins, are con-

nected to ground. The VDD-to-VSS stress, which is shown in Fig.

1(d), is to apply the ESD stress on the VDD pins when VSS pins

E



are connected to ground. The ESD stresses can have positive

or negative voltage with respect to the ground as shown in

Fig. 1(e). The IC after ESD stresses may cause damages not

only in the input/output circuits or devices, but also in the

internal circuits. Therefore, each IC product must be designed

with effective on-chip ESD protection circuits to sustain the

requested ESD level.

Fig. 1. The Pin combination for ESD test on an IC product:

(a) Pin-to-VSS; (b) Pin-to-VDD; (c) Pin-to-Pin; and (d) VDD-to-VSS (e) Pin to Pin: positive and negative mode

3 FUNCTIONALITY AND THE EFFECT OF ESD ON

DIFFERENT INTEGRATED CIRCUITS

3.1 Inverter IC

IC CD4069

The CD4069UB as shown in Fig. 2 is a buffer IC consisting

of six inverter circuits and is manufactured using CMOS tech-

nology to achieve wide power supply operating range, low

power consumption, high noise immunity, and symmetric

controlled rise and fall times. A low input gives a high output

and vice versa.

Fig. 2. Pin diagram of CD4069

When a Pin-to-Pin ESD stress of 8kV was applied on the

input pin 1 the output remains at 0 level (low) irrespective of

the input. The initial input is shown in Fig. 3 and the effect

after discharge is shown in Fig. 4. When a Pin-to-Pin ESD

stress of 15kV was applied on the output pin 12, the output

remains at 5V irrespective of the input. In the Hex package the

functionality of that particular gate is only affected.

Fig. 3. Input and Output of the first gate before the discharge

Fig. 4. Input and Output of the first gate after the discharge

IC 7404

This IC Package which is a Hex inverter consists of six TTL

inverters which can be used independent of one another. The

output of the inverter is the complement of its input logic

state. The Pin diagram of IC 7404 is shown in the Fig. 5.

Fig. 5. Pin diagram of 7404

(e)

Input

Output

Input Output



When Pin-to-Pin stress of 4kV was applied on the pin 1,

the first gate is damaged and the output remained at 4V (high)

irrespective of the input. And when discharged on the output

pin, the output remains at 0 (low) irrespective of the input.

The effect is opposite to that observed in a CMOS device.

3.2 Two input AND IC

IC 74LS08

This IC package contains four TTL independent AND gates

each of which performs the logic AND operation, whose pin

details are as shown in Fig. 6. It gives a logic high output

when both the inputs are at high.


After a discharge of 8kV near the IC there are huge tran-

sients in the input and output waveforms and it was also seen

that after the discharge the amplitude of logic high output of

the IC is reduced to half (2.5V) of initial value (5V) as shown

in the Fig. 7. There is no change in the amplitude of the input

waveform after discharge.

Fig. 7 Output of TTL AND gate after the discharge

IC 74HCT08

This IC package contains four CMOS independent AND

gates each of which performs the logic AND operation. It

gives a logic high output when both the inputs are at high.

When discharged at 8kV, as seen in Fig. 8 there are tran-

sients in the input and output waveforms. Also there was

decrease in the amplitude of the output after the discharge,

similar to TTL gate. But in CMOS there is decrease in the am-

plitude of the input waveform as seen in the Figure 8 after

reset which is not observed in TTL IC.

Before reset

After reset

Fig. 8. Output of CMOS AND gate after the discharge

3.3 Two input XOR IC

IC 74LS86

This IC package contains four TTL independent XOR gates

each of which performs the logic AND operation, whose pin

details are as shown in Fig. 9. It gives logic zero output when

both the inputs are same.


After the discharge of 15kV was given to the IC it was ob-

served that there was a DC offset for ground reference, hence

there is a decrease in the amplitude of the output. Also there



are transients in input and output waveforms as shown in the

Fig. 10.

Fig. 10 Output of TTL XOR gate after discharge

IC 74HCT86

This IC package contains four CMOS independent XOR

gates each of which performs the logic XOR operation. It

gives a logic high output when both the inputs are different.

After a discharge of 15kV to the IC, large transients are ob-

served in the input and output waveforms. Also the output

remains at a constant high irrespective of the input given. On

reset the output remains at constant 0V (low) as shown in the

Fig. 11.

Before reset

After reset

Fig. 11. Output of CMOS XOR gate after discharge

3.4 Two input OR IC

IC 74LS32

This IC package contains four TTL independent OR gates

each of which perform the logic OR operation, whose pin de-

tails are as shown in Fig. 12. It gives a logic low output when

both the inputs are at a low.

Fig. 12 Pin diagram of 7432

After a discharge of 8kV near the IC there are huge tran-

sients in the input and output waveforms and it is also seen

that after the discharge the amplitude of logic high output of

the IC is reduced to half of the initial level as shown in the Fig.

13. There is some change in the amplitude of the input wave-

form after the discharge.

Fig. 13. Output of TTL OR gate after the discharge

IC 74HCT32

This IC package contains four CMOS independent OR gates

each of which perform the logic OR operation. It gives a logic

low output when both the inputs are at a low.

After a discharge of 8kV to the IC, large transients are ob-

served in the input and output waveforms. Also the ampli-

tude of the output (5V) is reduced by 4V as shown in the Fig.

14. However the inputs are not affected by the ESD discharge.



Fig. 14. Output of CMOS OR gate after discharge

3.5 Four input NAND IC

This IC package contains two TTL independent NAND

gates each of which performs the logic NAND operation,

whose pin details are as shown in Fig. 15. It gives a logic high

output when any one of the inputs is at 0.

Fig. 15 Pin diagram of SN7420

When Pin-to-Pin ESD stress is done on the input and out-

puts of the IC only that particular gate is affected. When dis-

charged at the input pin, the output remains at 5V for any in-

put and when discharged at output pin the output for any

input remains at 2.5V when measured using a multimeter.

4 CONCLUSION

In the TTL gate when discharged at the input pin, the out-

put remains at 5V for any input and when discharged at out-

put pin the output for any input remains at 2.5V when meas-

ured using a multimeter. The TTL gate is designed with a to-

tem-pole configuration and the constant output voltage is due

to the lower transistor either becoming an open circuit for the

high output or being a short for the low output.

The comparison between TTL and CMOS logic gates reveal

that CMOS is more susceptible to ESD than TTL owing to its

construction. The presence of the dielectric medium in its de-

sign causes what is known as a dielectric breakdown due to

ESD.

REFERENCES

[1] MultiTrace Application Notes, “EOS/ESD Susceptibility Testing”, pp. 1-4.

[2] Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, and Hun-Hsien Chang,

“ESD Protection Design on Analog Pin with Very Low Input Capacitance for

High-Frequency or Current-Mode Applications”, IEEE Journal of solid-state cir-

cuits, Vol. 35, No. 8, august 2000, pp 1194-99.

[3] Charvaka Duvvury, Robert N. Rountree, and Olen Adams, “Internal Chip

ESD Phenomena Beyond the Protection Circuit”, IEEE Transactions On Elec-

tron Devices, Vol 35, No 12, December 1988, pp 2133-39.

[4] Application note TH808x, External ESD protection, www.melexis.com,

390110808001, March 2006, Rev 002, pp1-6.

[5] Wayne Austin, IEC 1000-4-2 ESD Immunity and Transient Current Capability

for the SP72X Series Protection Arrays, Application Note, July 1999, AN 9612.2.

[6] ANSI/ESD STM5.1-2001, For Electrostatic Discharge Sensitivity Testing Hu-

man Body Model (HBM) Component Level, Electrostatic Discharge Associa-

tion, An American National Standard, Approved March 20, 2003.

[7] R.Given, E.Grund, T.Meuse, I.H.Morgan J.Williams, "Study of the Impact of

Non-selected I/O Pins during HBM Test using ZapMaster Mk.2", Thermo

Fisher Scientific, September 2007, www.thermo.com/esd, pp 1-10.

[8] Robert Ashton, ON Semiconductors, “Human Body Model - The hidden

challenges”, Conformity, June 2008, pp 32-39.

http://www.melexis.com/

http://www.thermo.com/esd

Susceptibility of Integrated Circuits to Electrostatic Discharge

Documents

Transcript of Susceptibility of Integrated Circuits to Electrostatic Discharge