Summary Last Lecture - inst.eecs.berkeley.eduee247/fa06/lectures/L23_3_f06.pdf · dac) dac + + -...

EECS 247 Lecture 23: Data Converters © 2006 H.K.

EE247Lecture 23

ADC Converters– Techniques to reduce flash ADC

complexity• Interpolating (continued)• Folding• Multi-Step ADCs

– Two-Step flash– Pipelined ADCs

EECS 247 Lecture 23: Data Converters © 2006 H.K. Page 2

Summary Last Lecture

ADC Converters– Comparator design (continued)

• Comparator architecture examples

– Techniques to reduce flash ADC complexity• Interpolating (to be continued)


Interpolation• Idea

– Reduce number of preamps & instead interpolate between preamp outputs

• Reduced number of preamps– Reduced input capacitance– Reduced area, power dissipation

• Same number of latches (2B-1)

• Important “side-benefit”– Decreased sensitivity to preamp offset

Improved DNL


Preamp Output

Zero crossings (to be detected by latches) at Vin =

Vref1 = 1 ΔVref2 = 2 Δ

0 0.5 1 1.5 2 2.5 3-0.6

-0.4

-0.2

0

0.2

0.4

0.6

Vin /Δ

Pre

amp

Out

put

A2A1

VinA2

A1

Vref1 Vref2

Vref1

Vref2


Differential Preamp OutputDifferential output crossings @ Vin =

Vref1 = 1 ΔVref2 = 2 Δ

Note: Additional crossing ofA1&-A2 (A2&-A1)

A1+A2 cross zero at:

Vref12 = 0.5*(1+2) Δ=1.5Δ

0 0.5 1 1.5 2 2.5 3-0.5

0

0.5

Pre

amp

Out

put

0 0.5 1 1.5 2 2.5 3

A 1+A

2

A2-A2A1-A1

A1+A2

Vin / Δ

-0.5

0

0.5


Interpolation in Flash ADCHalf as many reference voltages and preamps Interpolation factor:x2

Example: For 10bit straight FlashADC need 2B=1024 preamps compared 2B-1=512 for x2 interpolation

Possible to accomplish higher interpolation factor

Interpolation at the output of preamps

Vin

A1

A2

Compare A2& -A1Comparator output is sign of A1+A2


Interpolation in Flash ADCPreamp Output Interpolation

Interpolate between two consecutive output via impedance Z

Choices of Z:1. Resistors (Kimura)2. Capacitors (Kusumoto)3. Current mode (Roovers)

Vin

A1

A2

Z

Z

Z

Vo1

Vo2

Vo1.5 = (Vo

1+Vo2)/2

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC, pp. 438-446, April 1993K. Kusumoto et al, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," JSSC, pp.1200 -1206, December 1993. R. Roovers et al, "A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter," JSSC, pp. 938 - 944, July 1996.

Z

...

...


Higher Order Resistive Interpolation

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,”JSSC April 1993, pp. 438-446

• Resistors produce additional levels

• With 4 resistors per side, the “interpolation factor”M=8(M ratio of latches/preamps)


DNL Improvement• Preamp offset distributed over

M resistively interpolated voltages:

Impact on DNL divided by M

• Latch offset divided by gain of preamp

Use “large” preamp gainNext: Investigate how large preamp gain can be

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,”JSSC April 1993, pp. 438-446


Preamp Input RangeIf linear region of preamp transfer curve do not overlap

Dead-zone in the interpolated transfer curve! Results in error

Linear consecutive preamp input ranges must overlapi.e. range > Δ

Sets upper bound on preamp gain <VDD / Δ

0 0.5 1 1.5 2 2.5 3

A2-A2A1-A1

0 0.5 1 1.5 2 2.5 3-0.5

0

0.5 A1+A2

Pre

amp

Out

put

A 1+A

2

Vin / Δ

Linear region of transfer curve not overlapping

-0.5

0

0.5


Interpolated-Parallel ADC

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp. 438-446

10-bit overall resolution:7-bit flash (127

preamps and 128 resistors) & x8 interpolation


Measured Performance

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp. 438-446

(7+3)

Low inputcapacitance


Interpolation Summary• Consecutive preamp transfer curve need to have overlap

Limits gain of preamp to ~VDD/Δ

• The added impedance at the output of the preamp typically reduces the bandwidth and affects the maximum achievable frequencies

• DNL due to preamp offset reduces by interpolation factor M

• Interpolation reduces # of preamps and thus reduces input C-however, the # of required latches the same as “straight” Flash

Use folding to reduce the # of latches


Folding Converter

• Two ADCs operating in parallel– MSB ADC– Folder + LSB ADC

• Significantly fewer comparators than flash • Fast• Typically, nonidealities in folder limit resolution to ~10Bits

LOGICLSB

ADC

MSBADC

Folding Circuit

VIN

DigitalOutput


Example: Folding Factor of 4

Vin

VFSVFS/2

Vout

00

01

10

11

ToLSB

Quantizer

MSBbits

• Folding factornumber of folds

• Folder maps input to smaller range

• MSB ADC determines which fold input is in

• LSB ADC determines position within fold

• Logic circuit combines LSB and MSB results


Example: Folding Factor of 4

Vin

VFSVFS/2

Vout

00

01

10

11• How are folds generated?

• Note: Sign change every other fold + reference shift

Fold 1 Vout=+ VinFold 2 Vout= - Vin + VFS/2Fold 3 Vout=+ Vin - VFS/2Fold 4 Vout= - Vin + VFS

1 32 4


Generating Foldsvia Source-Couple Pairs

M1 M2

IS

Vref1M3 M4

IS

Vref2 M5 M6

IS

Vref3M7 M8

IS

Vref4

R1 R2

VDD

-Vo+

Vin

Vref1 < Vref2 < Vref3 < Vref4As Vin changes, only one of M1, M3, M5, M7 is on depending on the input level


CMOS Folder Output

CMOS folder transfer curve max. min. portions:

RoundedAccurate at

zero-crossings

In fact, most folding ADCs do not use the folds, but only the zero-crossings!

0 0.5 1 1.5 2 2.5 3 3.5 4-0.5

0

0.5

Fold

er O

utpu

t

0 0.5 1 1.5 2 2.5 3 3.5 4-0.1

-0.05

0

0.05

0.1

Erro

r (Id

eal-R

eal)

Vin /Δ

Ideal Folder

CMOS Folder


Parallel Folders Using Only Zero-Crossings

Vref + 3/4 * Δ

Comparator

Folder 3

Folder 2

Folder 1

Folder 4

LogicVref + 2/4 * Δ

Vref + 1/4 * Δ

Vref + 0/4 * Δ

Vin

LSB bits

(to be combined with MSB bits)

Comparator

Comparator

Comparator


Parallel Folder Outputs

• 4 folders with 4 folds each

• 16 zero crossings• 4 LSB bits

• Higher resolution• More folders

Large complexity• Interpolation

0 1 2 3 4 5

-0.4

-0.2

0

0.2

0.4

Vin /Δ

Fold

er O

utpu

t

F1F2F3F4


Folding & Interpolation

FineFlashADC

ENCODER

Vref + 3/4 * Δ

Folder 3

Folder 2

Folder 1

Folder 4

Vref + 2/4 * Δ

Vref + 1/4 * Δ

Vref + 0/4 * Δ


Folder / Interpolator OutputExample:4 Folders + 4 Resistive Interpolator per Stage

0 1 2 3 5-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

Vin / Δ

Fold

er /

Inte

rpol

ator

Out

put F1

F2I1I2I3

1.5 1.6 1.7 1.8

-0.02

0

0.02

0.04

4

Note: Output of two folders + corresponding interpolator only shown


Folder / Interpolator OutputExample:2 Folders + 8 Resistive Interpolator per Stage

Non-linear distortionInterpolate only between closely spaced folds to avoid nonlinear distortion

1.5 1.6 1.7 1.8 1.9 2 2.1-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0 1 2 3 4 5-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

Fold

er /

Inte

rpol

ator

Out

put F1

F2I1I2I3

Vin / Δ


A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter

Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8



Note: Total of 40 comparators compared to 28-1= 255 for straight flash



Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8


Time Interleaved Converters• Example:

– 4 ADCs operating in parallel at sampling frequency fs

– Each ADC converts on one of the 4 possible clock phases

– Overall sampling frequency= 4fs

– Note T/H has to operate at 4fs!

• Extremely fast:Typically, limited by speed of T/H

• Accuracy limited by mismatch in individual ADCs (timing, offset, gain, …)

T/H

4fsADC

fs

ADC

ADC

ADC

Out

put C

ombi

ner

VIN

Dig

ital O

utpu

tfs+T/4

fs+2T/4

fs+3T/4


Two-Step (2+2) Example

• Using only one ADC: output contains large quantization error

• "Missing voltage" or "residue" ( -εq1)

• Idea: Use second ADC to quantize and add -εq1

0 1 2 300

01

10

11

0 1 2 3-1

-0.5

0

0.5

1

[LS

B]

ADC Input [LSB]

Vin

+Dout = Vin + εq1

2-bit ADC 2-bit ADC

???

ε q1

D out

Vin


Two Stage Example

• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about εq2 ?

Vin “Coarse“

+

Dout= Vin + εq1

2-bit ADC 2-bit ADC

“Fine“+-

2-bit DAC-εq1

-εq1+εq2

-εq1+εq2


Two Step (2+2) Flash ADC

Vin Vin Vin

4-bit Straight Flash ADC Ideal 2-step Flash ADC


Two Stage Example

• Fine ADC is re-used 22 times• Fine ADC's full scale range needs to span only 1 LSB of coarse

quantizer

221

22

2 222 ⋅== refref

q

VVε

00 01 10 11

Vref1/22

−εq1

00

01

10

11

First ADC“Coarse“

Second ADC“Fine“VinVref1

Vref2


Two-Stage (2+2) ADC Transfer Function

Dout

VinVref1

0000000100100011010001010110011110001001101010111100110111101111

CoarseBits(MSB)

FineBits(LSB)


Residue or Multi-Step Type ADCIssues

• Operation:– Coarse ADC determines MSBs– DAC converts the coarse ADC output to analog- Residue is found by

subtracting (Vin-VDAC)– Fine ADC converts the residue and determines the LSBs– Bits are combined in digital domain

• Issue: 1. Fine ADC has to have precision in the order of overall ADC 1/2LSB 2. Speed penalty Need at least 1 clock cycle per extra series stage to resolve

one sample

(optional)coarse ADC

(B1-Bit)Vin

Residue

DAC(B2-Bit)

Fine ADC(K-Bit)

Bit

Com

bine

r

(B1+

B2)

-Bit


Solution to Issue (1)

• Accuracy needed for fine ADC relaxed by introducing inter-stage gain

– Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only!

– Additional advantage- coarse and fine ADC can be identical stages

Vin “Coarse“

+

Dout= Vin + εq1

2-bit ADC 2-bit ADC

“Fine“+-

2-bit DAC-εq1

-εq1+εq2

-εq1+εq2

G=2B1


Solution to Issue (2)

• Conversion time significantly decreased by employing T/H between stages– All stages busy at all times operation concurrent– During one clock cycle coarse & fine ADCs operate concurrently:

• First stage samples/converts/generates residue of input signal sample # n• While 2nd samples/converts residue associated with sample # n-1

Vin “Coarse“

+

Dout= Vin + εq1

2-bit ADC

2-bit ADC

“Fine“+-

2-bit DAC-εq1

-εq1+εq2

T/H+(G=2B1)

T/H


Pipelined A/D Converters

• Ideal operation• Errors and correction

– Redundancy– Digital calibration

• Implementation – Practical circuits– Stage scaling


Pipeline ADCBlock Diagram

• Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!)

• Each stage performs coarse A/D conversion and computes its quantization error, or "residue“

• All stages operate concurrently

Align and Combine Data

Stage 1B1 Bits

Stage 2B2 Bits

Digital output(B1 + B2 + ... + Bk) Bits

Vin

MSB... ...LSB

Stage k Bk Bits

Vres1 Vres2


Pipeline ADCCharacteristics

• Number of components (stages) grows linearly with resolution

• Pipelining– Trading latency for conversion speed– Latency may be an issue in e.g. control systems– Throughput limited by speed of one stage → Fast

• Versatile: 8...16bits, 1...200MS/s

• Many analog circuit non-idealities can be corrected digitally


Pipeline ADC Concurrent Stage Operation

• Stages operate on the input signal like a shift register• New output data every clock cycle, but each stage

introduces at least ½ clock cycle latency

Align and Combine Data

Stage 1B1 Bits

Stage 2B2 Bits

Digital output(B1 + B2 + ... + Bk) Bits

VinStage kBk Bits

φ1φ2

acquireconvert

convertacquire

...

...

CLKφ1

φ2


Pipeline ADCLatency

[Analog Devices, AD 9226 Data Sheet]

Note: One conversion per clock cycle & 7 clock cycle latency


Pipeline ADCData Alignment

• Digital shift register aligns sub-conversion results in time

Stage 2B2 Bits

VinStage kBk Bits

φ1φ2

acquireconvert

convertacquire

...

...

+ +Dout

CLK CLK CLK

Stage 1B1 Bits

CLKφ1

φ2


Cascading More Stages

• LSB of last stage becomes very small • Impractical to generate several Vref• All stages need to have full precision

VinADC

+-DACADC

B3 bitsB2 bitsB1 bits

Vref Vref /2B1 Vref /2(B1+B2) Vref /2(B1+B2+B3)


Pipeline ADC Inter-Stage Gain Elements

• Practical pipelines by adding inter-stage gain use single Vref• Precision requirements decrease down the pipe

– Advantageous for noise, matching (later)

Vin ADCB3 bitsB2 bitsB1 bits

Vref

2B1

+-DACADC

Vref Vref Vref

2B22B3


Complete Pipeline StageVin +

-B-bitDAC

B-bitADC

D

-GVres

Vin0

0

Vref

−εq1

“ResiduePlot“

E.g.:B=2

G=22 =4

Vres

Vref


Pipeline ADCErrors

• We cannot build perfect ADCs, DACs and gain elements

• How can we tolerate/correct errors?• Let's first look at sub-ADC errors• Assumptions:

– Ideal DAC, ideal gain elements, only nonideality due to sub-ADC comparator offset


Pipeline ADC Model

1 q2 2out in,ADC q1

d1 d1 d 2

q( n 1) ( n 1) qnn 2 n 1

d( n 1)dj djj 1 j 1

G GD V 1 1

G G GG

.. . 1GG G

εε

ε ε− −− −

−

= =

⎛ ⎞ ⎛ ⎞= + − + − +⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠⎛ ⎞⎜ ⎟+ − +⎜ ⎟⎝ ⎠∏ ∏

ΣΣ

εq1

- G1

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/Gd1 1/Gd2

Vres1 Vres2 Vres(n-1)

Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn


Pipeline ADC Model

• If the "Analog" and "Digital" gain/loss is precisely matched:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛×= ∏

−

=

1

12log20..

n

jj

B GRD n

∏−

=

+= 1

1

, n

jj

qnADCinout

GVD

ε

jn

jnADC GBB ∑

−

=+=

1

12log


Pipeline ADCObservations

• The aggregate ADC resolution is independent of sub-ADC resolution

• Effective stage resolution Bj=log2(Gj)

• Overall conversion error does not (directly)depend on sub-ADC errors!

• Only error term in Dout contains quantization error associated with the last stage

• So why do we care about sub-ADC errors?Go back to two stage example


Pipeline ADCSub-ADC Errors

∏−

=

+= 1

1

, n

jj

qnADCinout

GVD

ε

1

2, G

VD qADCinout

ε+=

Grows outside ½ LSB bounds

Vin,ADCADCB1 bits

Vref Vref

Vres1

V εq2Vin0

0

Vref

Vres1

ref


Pipeline ADCSub-ADC Errors

Ideal 2-Stage Pipelined ADC 2-Stage Pipelined ADC with Coarse ADC Comp. Offset

Vin VinVinVin


Pipeline ADC1st-Stage Comparator Offset

First stage ADC Levels:(Levels normalized to LSB)Ideal comparator threshold: -1, 0, +1Comparator threshold including offset: -1, 0.3, +1

Problem: Vres1 exceeds 2nd pipeline stage overload range

Missing Code!

Overall ADC Transfer Curve

Vres1

Vres2


Pipeline ADC Three Ways to Deal with Errors

• All involve "sub-ADC redundancy“

• Redundancy in stage that produces errors– Choose gain for 2nd stage < 2B1

– Higher resolution sub-ADC

• Redundancy in succeeding stage(s)


(1) Inter-Stage Gain Following 1st stage < 2B1

• Choose G1 slightly less than 2B1

• Effective stage resolution becomes non-integer B1eff=log2G1

Ref: A. Karanicolas et. al., JSSC 12/1993

VinVref0

0

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


Correction Through Redundancy

“enlarged” residuum still within input range of next stage

Overall ADC Transfer Curve

Vres1

Vres2

If G1=2 instead of 4 Only 1Bit resolution from first stage (3-Bit total) No overall error!


(2) Higher Resolution Sub-ADC

• Keep G1=2B1 (e.g. keep G1=4)

• Add extra decision levels in sub-ADC (e.g. add 1 extra bit to 1st

stage)

• E.g. B1=B1eff+1

Ref: Singer et. al., VSLI1996

Vin

Vref00

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


(3) Over-Range AccommodationThrough Increase in Following Stage Resolution

• No redundancy in stage with errors

• Add extra decision levels in succeeding stage

Ref: Opris et. al., JSSC 12/1998

Vin

Vref00

Vref

Vres1

Vin,ADCADCB1 bits

Vref Vref

εq2

Vres1


Redundancy• The preceding analysis applies to any stage

in an an n-stage pipeline• Can always perceive a multi-stage pipelined

ADC as a single stage + backend ADCVin

B4 bitsB3 bitsB2 bitsB1 bits

VinB2+B3+B4 bitsB1 bits


Redundancy• In literature, sub-ADC redundancy schemes

are often called "digital correction" – a misnomer!

• No error correction takes place• We can tolerate sub-ADC errors as long as:

– The residues stay "within the box", or– Another stage downstream "returns the residue to

within the box" before it reaches last quantizer• Let's calculate tolerable errors for popular

"1.5 bits/stage" topology


1.5 Bits/Stage Example

• Comparators placed strategically to minimize overhead

• G=2

• Beff=log2G=log22=1

• B=log2(2+1)=1.589...

Ref: Lewis et. al., JSSC 3/1992

Vin

Vref00

Vref

Vres1

Vref/8


3-Stage 1.5-bps Pipelined ADC

• All three stagesComparator with

offset

• Overall transfer curve

No missing codesSome DNL error

Ref: S. Lewis et al, “A 10-b 20-MS/s Analog-to-Digital Converter,” J. Solid-State Circ., pp. 351-8, March 1992

Overall Transfer Curve

Vres1

Vres2

Vres3


Inter-Stage Amplifier Offset

• Input referred converter offset – usually no problem• Equivalent sub-ADC offset - accommodated through

adequate redundancy

+

ADC DAC-

D

VresVin G+

Vos +

-Vos

+

Vos


Gain Stage Errors

1, 1

1

2 ( 1) ( 1)22 1

1 2 ( 1)

1 1

1

1 ... 1

out in ADC qd

q q n n qnn n

d d d ndj dj

j j

GD VG

GGG G G

G G

δεδ

ε ε ε− −− −

−

= =

⎛ ⎞+= + −⎜ ⎟+⎝ ⎠⎛ ⎞⎛ ⎞

+ − + + − +⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠∏ ∏

ΣΣ

εq1

- G1+δ

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/(Gd1+δ ) 1/Gd2


Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn

Small amount of gain error can be tolerated


Interstage Gain Error

1 0.5 0 0.5 11

0

1First Stage Residue (Gain Error)

Vin

Vre

s

1 0.5 0 0.5 11

0

1Converter Transfer Function (Gain Error)

Vin

Dou

t1 0.5 0 0.5 1

0.2

0

0.2Transfer Function Error(Gain Error)

Vin

Dou

t(ide

al) -

Dou

t


Gain Errors

• Gain error can be compensated in digital domain – "Digital Calibration"

• Problem: Need to measure/calibrate digital correction coefficient

• Example: Calibrate 1-bit first stage

• Objective: Measure G in digital domain


ADC Model

( )DACinres VVGV −⋅=1

2/)1(0)0(

refDAC

DAC

VDVDV

====

2

VrefG Vin⎛ ⎞⎜ ⎟⋅ −⎝ ⎠

inG V⋅


Calibration – Step 1

Vin= const.+

-1-bitDAC

1-bitADC

D

GVres1

(1)

BackendDback

(1)

MUX

“1“

Vref

( )( )

storeVVV

GD

VVGV

ref

refinback

refinres

→−

⋅=

−⋅=

2/

2/

)1(

)1(1


Calibration – Step 2

Vin= const.+

-1-bitDAC

1-bitADC

D

GVres1

(2)

BackendDback

(2)

MUX

“0“

Vref

( )( ) store

VVGD

VGV

ref

inback

inres

→−⋅=

−⋅=0

0)2(

)2(1


Calibration – Evaluate

( )

( )

GDD

VVGD

VVV

GD

backback

ref

inback

ref

refinback

⋅=−

−−−−−−−−−−−−−−−−−

−⋅=−

−⋅=

21

0

2/

)2()1(

)2(

)1(


Accuracy Bootstrapping

• Highest sensitivity to gain errors in front-end stages

∏∏−

=

−

−−

=

− +⎟⎟⎠

⎞⎜⎜⎝

⎛−++⎟⎟

⎠

⎞⎜⎜⎝

⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛−+= 1

1

)1(

)1(2

1

)1(

2

2

1

2

1

11, 1...11 n

jdj

qn

nd

nn

jdj

nq

dd

q

dqADCinout

GGG

GGG

GGGVD

εεεε

ΣΣ

εq1

- G1

Σ

ΣΣ

εq2

- G2

Σ

ΣΣ

εq(n-1)

- Gn-1

Σ

Vin,ADC

Dout 1/Gd1 1/Gd2


Σ

1/Gd(n-1)

εqnD1 D2 D(n-1)Dn


"Accuracy Bootstrapping"

VinBn bitsStage 3Stage 2Stage 1 Stage k

“Sufficiently Accurate“Direction of Calibration

Ref:

A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Of Solid-State Circuits, pp. 1207-15, Dec. 1993

E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995

L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz," ISSCC 2000, Digest of Tech. Papers., pp. 38-9

→ Calibration in opposite direction...


DAC Errors

• Can be corrected digitally as well• Same calibration concept as gain errors

Vin +-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout+ 1/G

εDAC

-+

Backend


DAC Calibration – Step 1

• εDAC(0) equivalent to offset - ignore

+-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout 1/G

εDAC(0)

BackendVin= const.

MUX

“0“

+


DAC Calibration – Step 2...2B1

• Stepping through DAC codes 1...2B1-1 yields all incremental correction values

+-

B1-bitDAC

D

GVres1

Dback

B1-bitADC +

Dout+ 1/G

εDAC(1...2B1-1)

-

BackendVin= const.

MUX

1...2B1-1

+

Cal. Register


Calibration Hardware

• Digital is "free" and easier to build than precise analog circuits...Ref: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of

monolithic pipelined ADCs," TCAS II, pp. 143-153, March 1995

Summary Last Lecture - inst.eecs.berkeley.eduee247/fa06/lectures/L23_3_f06.pdf · dac) dac + + -...

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