SUBSTRATE NOISE COUPLING IN RFIC - CAS€¦ · SUBSTRATE NOISE COUPLING IN RFICs Helmy, Ahmed,...

SUBSTRATE NOISE COUPLING IN RFICS

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIESConsulting Editor: Mohammed Ismail. Ohio State University

Titles in Series:SUBSTRATE NOISE COUPLING IN RFICs

Helmy, Ahmed, Ismail, MohammedISBN: 978-1-4020-8165-1

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Substrate Noise Coupling in RFICs

by

AHMED HELMYOhio State University, Columbus, OH, USA

and

MOHAMMED ISMAILAnalog VLSI Lab, The Ohio State University, Columbus, OH, USA

Dr. Ahmed HelmyOhio State UniversityDept. Electrical & ComputerEngineering2015 Neil AvenueColumbus OH [email protected]

Dr. Mohammed IsmailAnalog VLSI LabThe Ohio State UniversityDept. Electrical & ComputerEngineering2015 Neil AvenueColumbus OH [email protected]

ISBN: 978-1-4020-8165-1 e-ISBN: 978-1-4020-8166-8

Library of Congress Control Number: 2008922524

c© 2008 Springer Science+Business Media B.V.No part of this work may be reproduced, stored in a retrieval system, or transmittedin any form or by any means, electronic, mechanical, photocopying, microfilming, recordingor otherwise, without written permission from the Publisher, with the exceptionof any material supplied specifically for the purpose of being enteredand executed on a computer system, for exclusive use by the purchaser of the work.

Printed on acid-free paper

9 8 7 6 5 4 3 2 1

springer.com

This book is dedicated to Yasmin, Zeina, Aly,Omar and Mohammed Ismail’s family

Preface

Substrate noise coupling in integrated circuits (ICs) is the process by which inter-ference signals in the form of voltage and current glitches cause parasitic currentsto flow in the silicon substrate to various parts of the IC. The source of such glitchesand parasitic currents could be from the switching noise of high speed digital clockson the same chip. In RF and mixed signal ICs the switching noise is coupled tosensitive analog and RF nodes in the IC causing degradation in performance thatcould severely impact the yield. Thus, overcoming substrate coupling is a key issuein successful “system on chip” first-pass integration where RF and mixed signalblocks, high speed digital I/O interface are integrated with digital signal process-ing algorithms on the same chip. This is particularly true as we move to sub-90nanometer system on chip integration.

In this book a substrate aware design flow is built, calibrated to silicon and usedas part of the design and validation flows to uncover and fix substrate couplingproblems in RF ICs. The flow is used to develop a comprehensive RF substratenoise isolation design guide to be used by RF designers during the floor planning,circuit design and validation phases. This will allow designers to optimize the de-sign, maximize noise isolation and protect sensitive analog/RF blocks from beingdegraded by substrate noise coupling.

Several effects of substrate coupling on circuit performance will be identifiedand remedies will be given based on the proposed design guide. Three case studiesare designed to analyze the substrate coupling problem in RFICs. The case studiesare designed to gradually attack the problem at the device (Case 1), circuit (Case 2)and system levels (Case 3). At the device level a special emphasis is given to thedesign of on chip inductors as an important device in today’s SOC systems and theimpact of substrate noise coupling on the inductor performance is characterized. Anaccurate model is developed for a broadband fit of the inductor scattering parametersto a lumped macro model that is used in the system analysis of case study 3. Thismodel is shown to be scalable and is proven to be accurate when applied to variousfrequency bands and inductor geometries. A special emphasis is put on the DFMeffects that affect the design robustness. A circuit level case study is developed andresults are compared to simulations and silicon measurements to highlight the needfor such a flow before silicon fabrication “taping out” to ensure a yielding part. Incase study 3 a system level problem is studied on a GSM cellular receiver chain.

vii

viii Preface

The results are used as a demonstration vehicle to debug and resolve a system levelsubstrate noise coupling problem that would otherwise have caused the receiver tomalfunction, with adverse implication on yield and profit margin for such a highvolume product.

Chapter 1 introduces the work and highlights the motivation, objective and con-tribution. Chapter 2 discusses the phenomena of substrate coupling. Devices to sub-strate interface, noise injection, reception and propagation are explained in details.The industry standard algorithms used to model the substrate are studied and com-pared. The design methodology used to account for and integrate the substrate modelin the design flow is highlighted. In Chapter 3 the design experiments are discussed,a test chip is described together with the de-embedding technique and measurementprocedure. The design flow is then developed to model the substrate and is cali-brated to the measurement data and simulations vs. measurements are reported as afoundation of a design flow that is used in the next chapters. In Chapter 4 a substrateisolation guide is developed based on two main methodologies. First, circuit andlayout considerations are presented to maximize isolation, namely floor planningtechniques. Supply line distribution and ground rails are also designed to maximizesubstrate isolation. Secondly, isolation structures are introduced and designed. Bias-ing and sizing of such structures are discussed; all are based on the calibrated designenvironment developed in Chapter 3. In Chapter 5 understanding the impact of theseisolation structures and the substrate characteristics is used to develop a design flowfor on chip spiral inductors. Measurements and simulations are compared to validatethe flow and various flavors of on chip inductors are designed to fit the needs of sev-eral RF applications. A scalable inductor macro model is developed that is shownto be usable to a very good accuracy across a wide variety of inductor geometriesand frequency bands. DFM effects are studied and their impacts are highlightedon the inductor performance. Chapter 6 presents three industrial case studies. Thecase studies are designed to gradually show the impact of substrate coupling at adevice, a circuit and then at a system level. Simulation and measurement results areshown with and without applying the isolation techniques and results are compared.Chapter 7 concludes the work and proposes future work.

This book is intended for RF and mixed signal design engineers, system-on-chipdesigners and process engineers as well as graduate students and researchers in thefields of integrated circuits and systems on chip design and optimization.

The work has its roots in the Ph.D. dissertation of the first author, completedat the Analog VLSI Lab, the Department of Electrical and Computer Engineering,The Ohio State University. We would like to thank all those who assisted us duringdifferent phases of this work including our colleagues at the Analog VLSI Lab andat Intel Corporation. We also like to thank the Semiconductor Research Corporationfor partially funding this work. Finally, we would like to thank our families for theirhelp and support.

Columbus, Ohio Ahmed HelmyMohammed Ismail

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Analysis of Substrate Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Process Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Process Cross Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 Connection of Devices to the Substrate . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 Noise Coupling Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5 Substrate Doping Profile Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.6 Substrate Model Extraction in the IC Design Flow . . . . . . . . . . . . . . . 182.7 Doping Profile Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.8 Substrate Model Extraction Kernels . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 Experimental Data to Calibrate the Design Flow . . . . . . . . . . . . . . . . . . . 253.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.2 The Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3 Baseline Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.4 Effect of p-Guard Ring on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.5 Effect of n-Guard Ring on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.6 Effect of Deep n-Well on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.7 Effect of Deep Trench on Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.8 De-embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 Design Guide for Substrate Noise Isolation in RF Applications . . . . . . . 434.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.2 Isolation in Low Resistivity Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . 434.3 Isolation vs. Frequency for Different Isolation Structures . . . . . . . . . . 444.4 Effect of Back Plane Connection on the Noise Isolation

in High Resistivity Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ix

x Contents

4.5 Substrate Contacts: Frontside or Backside? Both . . . . . . . . . . . . . . . . . 484.6 P+ Guard Ring Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.7 P+ and N+ Guard Rings Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.8 Floor Planning Techniques to Minimize Coupling . . . . . . . . . . . . . . . . 564.9 Circuit Techniques to Minimize Coupling . . . . . . . . . . . . . . . . . . . . . . 594.10 Active Guard Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.11 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 On Chip Inductors Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635.2 Integrated Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635.3 Inductor Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655.4 Analytical Exploration of the Design Space . . . . . . . . . . . . . . . . . . . . . 655.5 Inductor Model and Substrate Parasitics . . . . . . . . . . . . . . . . . . . . . . . . 715.6 Calibrating the Field Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.7 Model Fit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755.8 DFM Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6 Case Studies for the Impacts and Remedies of Substrate NoiseCoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.2 System Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.3 Block Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966.4 Device Level Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

A Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

B Measurements Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

List of Figures

1.1 History of Moore’s law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Trend in silicon systems and products . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Substrate noise coupling at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1 Cross section of a general BICMOS process . . . . . . . . . . . . . . . . . . . . . . . 82.2 Contacts in N-well resistors and capacitors . . . . . . . . . . . . . . . . . . . . . . . . 92.3 Poly resistor model showing substrate network . . . . . . . . . . . . . . . . . . . . . 112.4 Device models must be studied to accurately separate devices from

the substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5 Device to substrate capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.6 Cross section of a packaged chip showing bond wire noise . . . . . . . . . . . 152.7 Substrate cut-off frequency fc as a function of resistivity �sub . . . . . . . . . 172.8 Substrate as an undesired noise transfer medium . . . . . . . . . . . . . . . . . . . 192.9 Disretization of substrate doping profiles . . . . . . . . . . . . . . . . . . . . . . . . . . 202.10 Representing a substrate by a mesh of resistors . . . . . . . . . . . . . . . . . . . . . 213.1 The design flow used to characterize substrate noise coupling . . . . . . . . 263.2 The test bench used to simulate the substrate model of the isolation

structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3 Die photograph of the test chip used to measure the isolation of

different substrate structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 Layout and cross section of the structure used to measure and

simulate the baseline isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.5 Measurement vs. simulation for baseline isolation structure . . . . . . . . . . 293.6 Layout and cross section of the structure used to measure and

simulate the p+ guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . 303.7 Careful grounding is needed not to increase substrate noise coupling . . 313.8 p+ guard ring isolation once surrounding the receiver and once

surrounding the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.9 Layout and cross section of the structure used to measure and

simulate the n+ guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . 333.10 Measurement data for n+ guard ring isolation structure . . . . . . . . . . . . . . 333.11 Measurement vs. simulation for n+ guard ring isolation structure . . . . . 343.12 Comparison between isolation techniques . . . . . . . . . . . . . . . . . . . . . . . . . 34

xi

xii List of Figures

3.13 Layout and cross section of the structure used to measure andsimulate the deep n-well guard ring isolation structure . . . . . . . . . . . . . . . 35

3.14 Measurement and simulation data of the deep n-well guard ringisolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.15 Comparison between the isolation of two deep n well guard rings andtwo n well guard rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.16 Layout and cross section of the structure used to measure andsimulate the deep trench isolation structure . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17 Isolation of a p guard ring with a surrounding deep trench ascompared to a regular p guard ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.18 Layout and equivalent circuit of the GSG structure with the DUT . . . . . 393.19 Layout and equivalent circuit of the GSG open structure . . . . . . . . . . . . . 393.20 Layout and equivalent circuit of the GSG short structure . . . . . . . . . . . . . 404.1 Test structure used to simulate the backplane impact on isolation for

resistive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.2 Baseline isolation for resistive coupling vs. backplane inductance . . . . . 464.3 Test structure used to simulate the backplane impact on isolation for

capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4 Baseline isolation for capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . 474.5 Test structure used to simulate the impact of guard rings on isolation . . 494.6 Guard ring Isolation vs. distance D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.7 Guard ring grounding schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.8 Guard ring grounding scheme simulation data LGR = 1 nH . . . . . . . . . . . 514.9 Guard ring Isolation vs. distance “d” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.10 Guard ring isolation vs. distance “d” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.11 Structure used to simulate guard ring isolation vs. distance “w” . . . . . . . 534.12 Guard ring Isolation vs. ring width “w” . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.13 P and N Guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.14 P and N guard ring isolation vs. enclosure distance “d” . . . . . . . . . . . . . . 564.15 Floor planning to minimize substrate noise coupling . . . . . . . . . . . . . . . . 574.16 Placements and biasing of the guard rings and ground lines . . . . . . . . . . 584.17 Layout used to simulate the impact of guard rings on differential noise . 594.18 Differential isolation using p guard ring and dual p and n-well guard

rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.1 Inductor design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.2 Inductor layout showing design parameters and some DFM rules . . . . . 675.3 L contours as a function of OD and W at a given N and S . . . . . . . . . . . . 685.4 Q contours as a function of OD and W at a given N and S . . . . . . . . . . . . 695.5 L, Q contours as a function of OD and W at a different N and S . . . . . . . 705.6 Q vs. f showing different losses mechanisms . . . . . . . . . . . . . . . . . . . . . . . 715.7 Differential inductor macro model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.8 Test bench used to extract model parameters . . . . . . . . . . . . . . . . . . . . . . . 735.9 Q and L simulation vs. measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.10 Q and L simulation vs. measurement zoom in (left), parallel

differential inductor (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

List of Figures xiii

5.11 Q and L macro model fit vs. sp file and percentage error . . . . . . . . . . . . . 765.12a Inductor physical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.12b Inductor macro model and its fitting parameters . . . . . . . . . . . . . . . . . . . . 775.13 Q and L macro model fit vs. sp file and percentage error (left) inductor

parameters (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.14 Macro model fitting parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795.15 Bump relative positions to the on-chip inductor . . . . . . . . . . . . . . . . . . . . 795.16 Impact of bumps on the inductor Q and L (OD = 120 um,

W = 4.7 um, S = 0.6 um, N = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.17 Impact of temperature on the inductor Q and L . . . . . . . . . . . . . . . . . . . . . 815.18 Impact of process variation on inductor performance . . . . . . . . . . . . . . . . 815.19a Inductor with top metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.19b Inductor with n–1 metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.19c Inductor with n–2 metal fill pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.20a Inductor with metal fill patterns for other metal layers . . . . . . . . . . . . . . . 845.20b Inductor with poly and diffusion fill patterns . . . . . . . . . . . . . . . . . . . . . . . 845.21 Inductor with via fill patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845.22 Impact of dummification on Q and L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.1 Block diagram of the RF receiver used in the case study . . . . . . . . . . . . . 886.2 LO phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.3 LO phase noise mixing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906.4 Substrate noise coupling model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916.5 Layout of the VCO, LO and mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926.6 Substrate noise coupling distribution (case of vco perturbation) . . . . . . . 926.7 Substrate noise coupling distribution (case of blocker perturbation) . . . . 936.8 Layout comparison of both versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.9 Adding deep trenches in and around the VCO . . . . . . . . . . . . . . . . . . . . . . 946.10 Noise levels without deep trenches added (left), and with deep

trenches added (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.11 Noise aggressor and victim points using the modified VCO (left),

noise levels (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.12 A die photograph showing the VCO mixer section . . . . . . . . . . . . . . . . . . 966.13 Transmit buffer schematic without substrate network . . . . . . . . . . . . . . . . 976.14 Transmit buffer schematic with substrate network . . . . . . . . . . . . . . . . . . 986.15 Pout and Pgain vs. Pin with and without substrate model vs. silicon

data at 1.9 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.16 S12 measured vs. simulation with and without substrate model at

1.9 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996.17 Transmit buffer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996.18 Cascode stage in the transmit buffer layout . . . . . . . . . . . . . . . . . . . . . . . . 1006.19 Transmit buffer PN unmodified layout (right) modified layout and

measurement (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006.20 Inductor test cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026.21 Inductance vs. freq for the four test cases . . . . . . . . . . . . . . . . . . . . . . . . . . 1026.22 Quality factor vs. freq for the four test cases . . . . . . . . . . . . . . . . . . . . . . . 103

xiv List of Figures

A.1 Low-frequency description of two-port . . . . . . . . . . . . . . . . . . . . . . . . . . . 108A.2 High-frequency description of two-port. Z0 is the characteristic

impedance of the lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108B.1 VNA setup to measure S-parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110B.2 Layout of the measured differential inductors . . . . . . . . . . . . . . . . . . . . . . 110B.3 Layout of the measured differential inductors with all de embedding

structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111B.4 Transmit buffer measurement setup and calibration steps . . . . . . . . . . . . 112

List of Tables

5.1 Set of parameters that should be considered during designing theinductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2 Process information relevant to the inductor design . . . . . . . . . . . . . . . . . 755.3 Process corner definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826.1 Calculations for the receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916.2 Substrate noise coupling level at mixer input relative to the noise source 936.3 Substrate noise coupling level at victim points with and without deep

trenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.4 Substrate noise coupling level at victim points for all three versions . . . 956.5 Inductor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

xv

Chapter 1Introduction

1.1 Motivation and Objectives

The current trend in process technologies is marching towards 45 nm production in2007 and 32 nm production in 2009 [60]. The trend is still obeying Moor’s law [61],which states that the number of transistors on a single chip doubles every 2 years.Figure 1.1 shows the history of Moore’s law. In addition to the number of transistors,the demand on system on chip “SOC” and system in package “SIP” is increasingdrastically to implement low cost, low power and small die size products.

Figure 1.2 shows the trend in silicon products as of 2005 [60]. Examining thisfigure shows that the number of digital content is increasing in the presence ofanalog/RF and low power circuitry to achieve “SOC”. The increased number ofdigital gates is accompanied by the introduction of multi clock domains that canfulfill the signaling requirement. Such environment generates tremendous amountof interference signals that can couple to the analog/RF and other sensitive partsof the SOC, and in the presence of a scaled down supply voltage (to cope with thescaled geometry) the analog/RF become even more sensitive to noise, in addition,the noise margins of the digital gates are also decreased.

Signal isolation, especially between the digital and analog regions of the chip,is an increasing challenge for deep submicron technologies due to the increasedintegration complexity. Noise coupling may occur through the power supply, groundrails and shared silicon substrate. The difficulty of integrating analog and high-speeddigital functions on a chip increases with scaling in both device geometry and sup-ply voltage. Signal isolation is critical for the success of co-integrating high perfor-mance analog circuits and highly complex digital signal processing (DSP) functionson the same die or substrate. Such co-integration is driven by the growth of thepersonal mobile computers and handheld communications market in recent yearsto reduce size, power, and cost and present to the end user a single ship solution.In such an environment, noise disturbances generated by high switching rates ofdigital circuits and the presence of strong interference signals between tightly cou-pled channels can propagate through the common silicon substrate due to the finiteconductivity and permitivity of the substrate material and couple to circuits locatedin different parts of the substrate. Figure 1.3 shows the substrate noise coupling

A. Helmy, M. Ismail, Substrate Noise Coupling in RFICs,C© Springer Science+Business Media B.V. 2008 1

2 1 Introduction

Fig. 1.1 History of Moore’s law [61]

Fig. 1.2 Trend in silicon systems and products [60]

1.1 Motivation and Objectives 3

Fig. 1.3 Substrate noise coupling at a glance

phenomena at a glance. Coupling occurs between a noise transmitter, which in mostcases, is a fast switching digital block, and a noise receiver, which in most cases,is a sensitive analog or RF block. Coupling takes place due to the capacitive andresistive nature of the substrate-devices interface. The disturbances may, in manycases, be significant enough to degrade the performance of the sensitive analog andRF circuits sharing the same substrate with the digital block. Certain types of cir-cuits have traditionally been built on separate substrates in order to minimize noisecoupling between them. For example low-noise amplifiers and switching circuitssuch as dividers and high-power circuits such as buffers and power amplifiers aretraditionally built on separate substrates. Then a SIP or a “system in package” isdesigned to build a single chip “module” to be presented to the end user as a sin-gle package solution for integration on the system board. Such a process althoughbeneficial in many cases adds a huge overhead to project resources as far as design,validation, testing and integration.

Higher levels of integration have several associated advantages and disadvan-tages. Obvious advantages are the reduced package count and die area. This leadsto lowered costs and reduced sizes. The power dissipation can also be reduced asfewer pads and interconnect lines need to be driven, thereby avoiding the associatedcapacitance and parasitic self and mutual inductances. It may be possible to improvethe high frequency response of the circuits or even extend the frequency range ofthe circuits’ performance, as the package interconnect parasitics often degrade thefrequency response at the high frequency end of the application.

A major disadvantage of integration is the increased interaction between circuits.This interaction can appear in two major ways. It can occur due to the significantmutual inductance and capacitance, which exist between any two bond wires andpins in a package. The second method for interaction is through the common sub-strate shared by the circuits.

4 1 Introduction

Integrating high-power switching noise generating circuits and sensitive low-noise circuits on the same silicon substrate while avoiding performance degradationdue to substrate coupling is currently being viewed as a major challenge by circuitand system designers.

In this book the problem of substrate coupling is addressed. The goals of thisbook are as follows. First is to build a calibrated design flow and develop a substratedesign guide that can be adopted in a production worthy design environment that iscapable of designing the substrate isolation structures and debugging the substratecoupling problems and implement fixes to such problems on device, circuit andsystem levels. Second is to design these fixes to take into consideration design formanufacturing effects. Examples of DFM effects are process skew variations, tem-perature variation, and effect of density dummification, wire bonds and C4 bumps.Such effects are being ignored for a while as being second order effects, but astechnology scales these effects have started to surface as critical issues that must beaddressed early in the design cycle. The objective here is to study the impact of sucheffects to ensure high resolution functionality and to eliminate costly reiterations.

The sources of coupling are identified in different technologies as well as invarious devices, both actives and passives. Then the mechanisms of noise recep-tion and propagation through the substrate and the problem of efficient modelingof substrate coupling are discussed. The impact of substrate coupling on circuit be-havior is discussed. Experimental results that verify the design flow will be carriedon silicon. In this book different layout and isolation techniques will be suggestedand verified to minimize substrate noise coupling. The third objective of the bookis to study the impact of the substrate characteristics and isolation techniques onthe design of RF passive devices. Precision passive devices are a new demandingchallenge for current and future on-chip architectures. The request for high qual-ity capacitors, inductors and resistors is mainly driven by advanced mixed-signal,high frequency (RF) and (SOC) applications. In the past, the traditional method ofrealizing passive circuit elements (for example, capacitors, resistors) on ICs wasintegration during front end processing. In this case doped monocrystalline Si sub-strate, polycrystalline Si and Si-oxides or Si-oxynitrides are used [1]. Because oftheir vicinity to the Si substrate, those passive devices fabricated during front endprocessing suffer increased performance degradation especially when used at highfrequencies. Therefore, there is an increasing demand for low loss, low parasitics,but high quality passive devices in the interconnect levels. A part of this book isdedicated to develop an accurate inductor design flow that takes into considerationthe substrate characteristics, isolation techniques and design for manufacturing ef-fects. The focus is put on high quality on-chip inductors as they are critical compo-nents in analog/mixed signal and high frequency (RF) applications. With increasingfrequencies, on-chip inductors will gain even more importance in the future [1–3].Currently they are widely used in RF circuits especially for impedance matching, RFfilters, RF transceivers, voltage controlled oscillators (VCO), power amplifiers andlow noise amplifiers. Several design examples are developed in this book relyingon the inductor design methodology that is also developed and adopted to designthese structures. The impact of substrate is highlighted and isolation techniques are

1.3 Book Organization 5

implemented. The designed inductors are selected to span the different flavors of onchip spiral inductors that fit various RF application needs. The fourth objective is toapply the learning to real life circuits and system level problems and demonstratehow to uncover a substrate noise coupling problem, its impacts and remedies.

1.2 Contributions

The objectives are carefully selected to complement the previous work found in theliterature [62–92] and to provide simulation and measurement based analysis insteadof the rule-of-thumb guidelines now used to deal with substrate noise problems.The focus will be on the RF and high speed serial IO link applications and theirfrequency of operation. The book contributions are summarized as follows:

� A substrate aware design flow is build that uses the substrate model kernel extrac-tor that represents the industry standard. The emphasis is focused on calibratingthe flow to the process technology at hand.

� The flow is calibrated to silicon measurements, based on a test chip that is de-signed and tested for this purpose.

� The emphasis of this work is put on the RF and high speed serial IO links fre-quencies (1∼10 GHz).

� A complete substrate noise isolation design guide is developed based on thecalibrated design flow. The design guide studies various isolation structures inmodern process technologies used for RF and mixed signal ICs, their geometricaland electrical parameters, frequency of operation, floor plan, power and grounddomains design.

� A design flow is developed to design on-chip spiral inductors based on analyticalformulas found in the literature and an industrial tool used as a 3D full wave fieldsolver. The flow is calibrated to silicon measurements and is used to study thesubstrate parameters and their impact on the inductor performance.

� The DFM effects are studied that impact the on-chip inductor performance. Sucheffects that directly impact robustness and yield.

� The two design flows are used in the design phase and is applied to three casestudies on device, circuit and system levels where the noise coupling issue isuncovered and fixed. Simulation and silicon measurements are used to validatethe existence of the problem and to validate the fix implemented.

1.3 Book Organization

In Chapter 2 the phenomena of substrate coupling is studied. Devices to substrateinterface, noise injection, reception and propagation are discussed in details. Theindustry standard algorithms used to model the substrate are studied and compared.The design methodology used to account for and integrate the substrate model inthe design flow is discussed. In Chapter 3 the design experiments are discussed, a

6 1 Introduction

test chip is described together with the de-embedding technique and measurementprocedure. The design flow is then developed to model the substrate and is cali-brated to the measurement data and simulations vs. measurements are reported as afoundation of a design flow that is used in the next chapters. In Chapter 4 a substrateisolation guide is developed based on two main methodologies. First, circuit and lay-out considerations to maximize isolation, namely floor planning techniques, powerline distribution as well as ground rails are designed to maximize substrate isolation.Second is the design of isolation structured that will aid the isolation level. Biasingand sizing of such structures are discussed all are based on the calibrated designenvironment developed in Chapter 3. In Chapter 5 the learning of the impact of theseisolation structures and the substrate characteristics is used to develop a design flowfor on chip spiral inductors. Measurements to simulations are compared to validatethe flow and various flavors of on chip inductors are designed to fit the needs ofseveral RF applications. A scalable inductor macro model is developed that is shownto be usable to a very good accuracy across a wide variety of inductor geometriesand frequency bands. DFM effects are studied and their impacts are highlighted onthe inductor performance. Chapter 6 concludes the book by applying the learningto three industrial case studies. The case studies are designed to gradually show theimpact of substrate coupling on a device, a circuit and then a system. The isolationtechniques developed are applied to the case studies to enhance the performance,simulation and measurement results are shown with and without applying the isola-tion techniques and results are compared.

Chapter 2Analysis of Substrate Noise Coupling

In this chapter the steps needed to prepare the design environment that will be usedin the next chapters to characterize the substrate noise coupling problem are studied.First, the device models of the process are studied to clearly define the devices-substrate interface. Second, the noise injection, reception and transmission mech-anisms are studied to understand the process parameters involved and frequencylimitation that impacts the coupling phenomena, so that approximations and justifi-cations can be engineered. Finally, the field solvers are studied and compared andan industry standard kernel is adopted in our flow.

To set the foundation of analyzing the substrate coupling mechanism a genericcross section of a modern BICMOS process is shown in Fig. 2.1. The process ischaracterized by regions and cross sections [93]. The motivation behind this diagramis to study where and how the devices are connected to the substrate and what shouldbe considered part of the substrate model that is connected to the circuitry and whatshould be left out from the substrate model since it is usually accounted for in thedevice model. Care should be exercised here since failing to make this distinctionmay result in double counting junction caps and substrate parasitics or in somecases missing these parasitics from the model of the entire system completely. Inother words at the interface between the devices and the substrate a clear cut shouldbe made to distinguish between features that are modeled in the front end devicemodels and features that are not and hence should be part of the substrate modelwith no features left out and no features accounted for twice.

In the next section, process regions and cross sections are explained; a BICMOSprocess is used since it has both Bipolar and CMOS devices and acts as a supersetof process technologies.

2.1 Process Regions

Figure 2.1 lists the process different regions as follows:Default: This corresponds to the default p substrate where there is no well im-

plant present. Devices implemented in this region are NMOS devices.N-well: This corresponds to the region where an n-well implant has been made

to create an n-well tub for including p-type PMOS devices.


8 2 Analysis of Substrate Noise Coupling

Fig. 2.1 Cross section of a general BICMOS process

Deep n-well: This region has an n-well implant (similar to the n-well regionabove) but in addition to this implant, there is a buried n-layer underneath the n-wellthus increasing the depth of the n-well in the substrate. Devices implemented in thisregion are PMOS devices that need special substrate isolation.

Triple well: This region corresponds to a p-well tub that has been completelyseparated from the default substrate region by the presence of the buried n-wellstructure that forms the floor of the tub. Devices implemented in this region aretriple well NMOS. In addition to noise isolation, triple well NMOS are usually usedto eliminate body effect or back bias by furnishing a dedicated bulk connection tothis transistor that is separated from the rest of the common substrate and hencecan be connected to a dedicated connection without sharing the common substrateconnection. This is used to bias the device in a drowsy mode, which is used forpower saving during stand-by operations. The overhead of such device is both wafercost and die area.

Sinker: This region corresponds to the n-type buried layer that is contactedthrough an n-sinker. This normally occurs in the bipolar transistors.

Deep trench: This region represents the oxide trench that goes deep into thesubstrate. This is used primarily for substrate noise isolation.

Passives: This region represents the place where passive devices are imple-mented on higher level metal layers. Examples of passive devices are poly resistors,inductors, metal capacitors and routing interconnects. This region can be combinedwith the default region where NMOS transistors are not present.

2.2 Process Cross Sections

Seven distinct cross sections are shown in Fig. 2.1 where the arrows are pointing.1-Default: This corresponds to the section with no active diffusion implants in

the process. This is the section with only the field thick oxide or Shallow TrenchIsolation “STI”.

2-Contact: This cross-section denotes the active diffusions that are bias contacts(substrate and/or well ties or taps) into the substrate mostly from power and groundsupplies (for example P+ ties in the default region is connected to ground pads,

2.2 Process Cross Sections 9

while N+ contacts in the n-well regions will be connected to power supply pads).In some cases these contacts are also present in well resistors and well capacitors(N+ in n-well) where they are not necessarily connected to power and ground padsas shown in Fig. 2.2.

3-Source drain: This cross-section denotes a p-n junction which is formed bya diffusion implant in the substrate (P+ in n-well, N+ in default p-substrate). Thiswould be used for connecting to sources and drains of MOS transistors as well asp-n junction diodes. Note that the source-drain cross section in the substrate shouldnot include the junction parameters for the p-n junction. These are obtained fromthe device models as discussed later in this chapter.

4-channel: This cross-section represents the substrate underneath the gate of theMOS device under active conditions. MOS devices are connected to the substratevia this cross section and its bulk terminal.

5-deep device: This is primarily used to account for devices that include then-well to substrate p-n junction inside the device model. Here the profiles represent-ing the substrate start from below the n-well junction to the bulk substrate.

6-Bipolar: This is used to account for devices that already include the n-buriedlayer to substrate junction inside the device model. Here the profile representing thesubstrate starts from below the n-buried layer junction to the bulk substrate.

7-passives: This cross section lies under passive devices such as inductors andmetal capacitors. In many situations these devices are surrounded by substrate tapsor guard rings to isolate the substrate region under the devices which minimizesnoise coupling to/from these devices.

The combination of a region and a cross section denotes a unique profile in thesubstrate and this in turn ties to devices appropriately. The following discussionfor the different active and passive devices present in today’s technologies clarifiesthe connectivity of different devices into the substrate. First, the regions and crosssections associated with each other are as follows:

Fig. 2.2 Contacts in N-well resistors and capacitors


Region default can only have these cross sections: default, contact, chan-nel, s/d.

Region n-well can only have these cross sections: default, contact, channel, s/d,deep device.

Region deep n-well can only have these cross sections: default, contact, chan-nel, s/d, deep device.

Region sinker can only have these cross sections: bipolar.Region deep trench can only have these cross sections: default.Region triple well can only have these cross sections: default, contact, channel

s/d, deep device.Region passives can only have these cross sections: default, contact.

In addition to that, substrate taps (or ties) are extracted as a one pin device(“TIE”). The single pin of the device is connected to the appropriate supply con-nection. This is achieved by stamping the connectivity to the metal layers on top.

Next will be how each device is modeled and how will this impact the connectionto the substrate. For example, the n-well resistor device can have three terminalswhere the third terminal (“sub”) is connected to p-sub. This means that the devicemodel includes a diode modeling the n-well to substrate junction. In this case, then-well shape associated with this device is taken out from the n-well region shapeoutput in the substrate model because it is accounted for already in the model. Ifthe “sub” terminal of the n-well resistor is a contact in the n-well then the substratemodel should consider the n-well p-sub junction and its capacitance as part of thesubstrate model underneath this device.

2.3 Connection of Devices to the Substrate

This section lists the connection between the different types of devices and the sub-strate. Some devices are considered directly connected to the substrate while othersare indirectly connected as explained below.

2.3.1 Devices Directly Connected to the Substrate Network

MOS Devices: These MOS devices are connected to the substrate through the bulkpin “sub” or “B”. They are connected to the “channel” cross section in the substrate.

Poly Resistors: Since almost all poly resistor models account for the capacitanceto substrate and the substrate network underneath the poly resistors as shown inFig. 2.3, these resistors are connected to the substrate through the bulk pin “B”.These are connected to the “default” or “deep device” cross section if they are polyover sub or poly over n-well respectively. Same argument applies to all passivedevices, inductors, MIM capacitors, etc.

2.3 Connection of Devices to the Substrate 11

Fig. 2.3 Poly resistor model showing substrate network

N-well Resistor: The n-well resistor is connected to the substrate through the bulkpin “sub”. This is connected to the “deep device” cross section (n-well-sub diode ispart of the device model).

Inductors: The inductors are connected to the substrate through the bulk pin“sub”. They are connected to the “default” or contact cross sections, depends onwhether the inductor has a guard ring TIE around it or not.

MIM Capacitors: The Metal to Metal capacitors are connected to the substratethrough the bulk pin “sub”. They are connected to the “default” or deep device crosssection depending if the MIM is over sub or over n-well (n-well-sub diode is part ofthe device model).

Poly Gate Capacitor: This capacitor is connected to the substrate through thebulk node “sub”. It is connected to the “deep device” cross section (n-well-sub diodeis part of the device model).

2.3.2 Devices Indirectly Connected to the SubstrateNetwork

The devices diode, bipolar and the varactor are considered indirectly in the substratenetwork. These devices always have a guard ring (tied to a supply) around them, sothe guard ring is considered as a TIE which is connected to the substrate networkvia the default cross section.

Now that the device models are studied and a decision is made to identifythe devices-substrate interface, substrate is modeled separately as a semiconductormedium and then its model is connected back to the circuit to create a netlist withthe substrate modeled. Figure 2.4 shows a methodology for such separation.


Fig. 2.4 Device models must be studied to accurately separate devices from the substrate [94]

2.4 Noise Coupling Mechanism

Three processes act sequentially to complete the substrate noise coupling phenom-ena. First the noise currents are injected from the devices into the substrate throughthe devices-substrate interface, and then noise propagates through the substratemedium to reach other locations on the same substrate. The nature of such prop-agation depends on the substrate resistivity and isolation structures implementedas well as grounding techniques and frequency of operation. Finally the substratenoise is received at the sensitive circuit node, where it modifies device character-istics. The challenge of modeling the substrate coupling is therefore a three-foldissue. Modeling of the injection mechanisms, substrate medium and the receptionmechanisms is required to accurately analyze substrate coupling. Injection and re-ception mechanisms are modeled within the device models. The modeling of thesubstrate medium is provided separately. In this section, we will discuss substratenoise injection, propagation and reception mechanisms.

2.4.1 Substrate Noise Injection Mechanisms

In mixed signal designs, devices induce currents in the substrate through severalmechanisms. The most dominant are diffusion capacitive coupling, impact ioniza-tion and inductive coupling due to power grid fluctuations at substrate contacts withpower and ground lines. According to [5], there are other less significant mecha-nisms through which currents are injected to the substrate, gate-induced drain leak-age (GIDL) due to the gate induced barrier lowering, photon-induced reverse currentand diode junction leakage current. The effects of these mechanisms are negligiblecompared to the above mentioned ones. They become only significant under certainbias conditions not applicable to the majority of applications, thus we will not focuson such effects in our analysis.

2.4 Noise Coupling Mechanism 13

2.4.1.1 Noise Injection Through Capacitive Coupling

An important mechanism by which noise is injected to the substrate is capacitivecoupling. Devices inject currents into the substrate through the p-n junction deple-tion capacitance of drain and source regions or collector regions to substrate C js .

C js =√

qε

2(ψ + V b)

(√N1N2

N1 + N2

)(2.1)

where Cjs is the capacitance per unit area of the abrupt p-n junction, q is the chargeof an electron, � is the Si dielectric constant, ψ is the junction built in potential, Vbis the magnitude of the reverse bias voltage, N1 and N2 are the doping concentrationof the p and n regions of the junction. The strength of the coupling is dependent onthe device size and the switching frequency. As technology feature size is reduced,the doping concentration of the diffused regions is increased to avoid total pinch-off effect. Higher doping concentration leads to higher depletion capacitance andtherefore lower capacitive impedance from the diffusion regions to the substrateand hence more coupling effects. Note that this capacitance is always included incircuit simulators such as SPICE as model elements “CJ0” and “CJSW” (these arethe source/drain-to-substrate capacitance). Figure 2.5 shows a few types of devices-to-substrate capacitive coupling.

Other than the p-n junction capacitive coupling, passive devices like resistors,capacitors and inductors can also capacitively induce current into the substrate. Re-sistors in modern processes are either poly-type or diffused. Poly resistors have acomparatively smaller parasitic capacitance to the substrate Thus diffusion resistorsinject more noise into the substrate than poly resistors for the same dimensions.

Capacitors can be either metal-to-metal, or poly-to-substrate types. Metal-to-metal capacitors have the largest ratio of the parasitic capacitance to the substratefor a given capacitance. Hence if these devices are used for implementing largeon-chip capacitors, they can act as significant substrate noise-injectors. On-chip in-ductors and interconnects inject noise into the substrate through the parasitic oxide

Fig. 2.5 Device to substrate capacitive coupling


capacitance with the substrate. The substrate parasitic can lead to lowering of the in-ductor quality factor. Thus the substrate loss must be modeled to obtain an accurateprediction of inductor performance as discussed in Chapter 5.

2.4.1.2 Noise Injection Through Impact Ionization

As transistor feature sizes are being reduced, the electric field in the channel in-creases and therefore impact ionization currents are becoming more significant com-pared to other injection mechanisms. When MOS devices are biased in saturationregime, a high electric field in the depleted region of the channel is formed nearthe drain. Due to the high electric field, impact ionization takes place when “hot”carriers dissipate their excess energy via collision generating electron-hole pairs.For a p-type substrate, in case of NMOS transistors, the generated holes are sweptto the substrate generating an effective drain to-substrate current [5]. For PMOStransistors, the impact ionization current is less due to the lower hole mobility. Inaddition, PMOS transistors are physically located inside n-well regions. The welljunctions serve to reduce coupling of currents to the surrounding p-type substratedue to its capacitive impedance. Thus it may be expected that PMOS devices causelower substrate bounce than comparably sized NMOS devices. This is indeed thecase as long as the n-well has a very low impedance ac ground contact. If the wellpotential is allowed to vary with respect to the substrate potential, the well acts asa large injector, with a large reverse biased well to substrate capacitance and cancause significant substrate noise injection. The impact ionization substrate currentdependence on the transistor drain current is given by the following semi-analyticalexpression [6].

Isub = K1(Vds − Vdsat )Id exp

( −K2

Vds − Vdsat

)(2.2)

where Id is the drain current Vds is the drain to source voltage and Vdsat is the drainto source voltage at saturation. K1 and K2 are empirical constants. K2 depends onthe oxide thickness tox and the drain junction depth x j as

K2 � tox1/3x j

1/2 (2.3)

This phenomenon is discussed extensively in [6]. It is derived by considering theexponential dependence of the carrier ionization coefficients on the electrical fieldin the channel. Integrating the substrate current generated per unit length over thelength of the channel results in Eq. (2.2). Recent experimental evidence suggests thathot-electron induced substrate currents are the dominant cause of substrate noisein NMOSFETs up to at least one hundred megahertz [7]. Shorter device channellengths in future technologies are likely to increase the impact ionization currentsdue to increased channel fields and smaller tox and x j .

The nature of current injection due to capacitive coupling and impact ioniza-tion induced currents is different because hot-electrons induced currents are always


injected into the substrate irrespective of the polarity of the injectors. In a switchingCMOS inverter, hot-electrons induced current will be injected into the substrate dur-ing both the 0-1 and 1-0 transitions, while the capacitive component of the currentwill reverse direction during the two edges. As a consequence, hot-electron inducedcurrents will possess large even-harmonics of the fundamental switching frequencyand a DC component. On the other hand, the capacitive currents will possess largeodd-harmonics and no DC component. Thus careful circuit design such as differ-ential circuit techniques can minimize the even-harmonics and decrease the impactionization component. The presence of a DC component in any substrate currentcan be potentially very harmful to circuit operation. In addition to causing a driftin threshold voltages, it can also lead to an increase in minority-carrier injectioninto the substrate due to partial forward-biasing of device-to-substrate junctions.This leads to severe degradation in the circuit performance or in many cases amalfunction.

For small-signal analysis, the effect of the hot-electron induced current can bemodeled as a drain-to-body transconductance gdb [8] given by

gdb = �Isub

�VD= K2 Isub

(Vds − Vdsat )2. (2.4)

The major effect of this parameter on small-signal circuit analysis is that this termappears in parallel with the ro of the device and tends to lower the output impedanceof the transistor in saturation hence lowering its gain in saturation.

2.4.1.3 Noise Injection Due to Power Grid Fluctuations

Due to parasitic effects associated with the package, mainly bond wire inductance,power supply lines become very noisy because of currents drawn by the switch-ing digital circuits. These currents induce large voltage glitches when they switch(Ldi/dt noise) at substrate and well contacts. This represents a significant amount ofnoise injection into the substrate depending on the switching speed and the avail-ability of other noiseless substrate ties. In addition, the power grid noise can be alsocapacitively coupled through metal-to-substrate parasitic capacitance. Figure 2.6shows a cross section of a packaged chip and the coupling between bond wires.

Fig. 2.6 Cross section of a packaged chip showing bond wire noise


2.4.2 Substrate Noise Reception Mechanisms

The reception of noise by most devices on the silicon surface takes place through ca-pacitive sensing. This is true for BJTs, resistors, capacitors and interconnects lines.For MOS transistors, noise couples through drain and source junctions. For deviceslike diffusion resistors and well-to-poly capacitors, the noise is coupled throughthe well junction capacitance. Because junction capacitances are typically small,capacitive coupling effects become significant only at high frequencies. Metal inter-connects and poly resistors are also capacitively linked by oxide capacitance to thesubstrate. Substrate noise can also indirectly affect the circuit performance throughthe package and interconnect parasitics, �I noise across bond wire inductance maycause serious performance issues.

In addition to capacitive pickup through the source and drain depletion junctions,MOS devices also exhibit a more severe form of substrate interaction due to the bodyeffect. The threshold voltage of a MOS transistor is a relatively strong function of thesubstrate potential. For a uniform surface impurity concentration, the dependence ofthe threshold voltage is given by [8].

Vt = Vt0 + γ(√

2φ f + Vsb − √2φ f

)(2.5)

where Vt0 is the threshold voltage at zero source-to-bulk bias � is bulk thresholdparameter and � f is the surface inversion potential. The change in threshold voltagehas a direct effect on the drain current Id through the following equation:

Id = K

2

W

L(Vgs − Vt )2. (2.6)

The dependence is represented as gmb, the bulk-to-source small-signal transcon-ductance gmb

gmb = �Id

�Vbs= gm

γ

2√

2φ f + Vsb(2.7)

where gm is the gate-to-source transconductance at the same operating point. Intypical processes the ratio (gmb/gm) varies from 0.1 to 0.3. The parasitic body-to-source gain is thus lower than the gate-to-source gain by a factor of 14–20 dBonly. The body effect in MOSFETs makes these devices especially vulnerable tosubstrate noise reception. While the capacitive pickup exhibited by most devicesbecomes significant only at high frequencies, the body effect can be an issue at lowfrequencies.


2.4.3 Substrate Noise Transmission Mechanisms

Substrates act as the media for coupling of noise from one device to another. Thus inorder to understand the phenomenon of substrate coupling, it is essential to study thenature of the substrate as a transmission media and the process technology parame-ters that affect that as well as the frequency impact on the behavior of the substrateas the transmission media.

Since the substrate acts as a lossy dielectric, a derivative of Maxwell’s equationsshown below is applicable to the substrate [27]

J = (σ + jωεSi)E (2.8)

where J is the current density in the substrate (A/cm2), E is the electric field(V/cm), σ is the conductivity (S/cm) and εsi is the dielectric permittivity of silicon(�o 8.854e-14 ∗ �r 11.7 F/cm), ω is the frequency in rad/s. The substrate impedanceand the behavior of the substrate as a noise transmission medium are frequency de-pendent. As long as σ >> ωεSi the current in the substrate will be dominated by theresistive nature. At low frequencies, dielectric capacitive behavior of the substrateis insignificant and hence, it can be considered merely as a resistive medium. Thisassumption is valid below a certain cut-off frequency fc given as [9]

fc = 1/(2�sub�si) (2.9)

where �sub is the resistivity of the substrate. Figure 2.7 shows a plot between thesubstrate resistively � = 1/ and the frequency at which = ωεSi called thecutoff frequency fc.. For �sub = 10 �-cm, the substrate can be considered as aresistive medium below 15 GHz. Thus for most of the cases in this book the substrate

Fig. 2.7 Substrate cut-off frequency fc as a function of resistivity �sub


medium is treated as a resistive medium except in some specific conditions that willbe highlighted where they fit.

The above model considers current flow only due to drift (field induced) currents.This model would be sufficient for low-level majority-carrier conduction. Minority-carriers, once injected into the substrate, can exist for long periods of time (carrierlifetime) and cause significant local variations in conductivity. However a large in-jection of minority-carriers into the substrate usually indicates a fault condition,as this occurs when a device-to-substrate junction is turned on. Hence to modelsubstrate cross-talk we only consider the drift-induced substrate currents.

2.5 Substrate Doping Profile Tradeoffs

Conductivity is the parameter that determines the nature of the noise transmissionmedia in the substrate. The conductivity depends on the carrier concentration“p” and the hole mobility “�p” and hence is a function of the doping profiles inthe substrate. Substrate coupling depends on the type of the substrate whether it islightly-doped or heavily-doped. Intuitively, the higher the resistivity of the substratethe lower the noise coupling will be. Tradeoff between noise coupling, latch upeffects and wafer cost is what dictate the wafer doping profile of different processtechnologies based on the target application. The modern process technologies arecategorized into three main types. First, the memory and RF processes with a highresistivity substrate (all TSMC and UMC processes [10, 11]). Second the digitalCMOS processes with a low resistivity substrate and a high resistivity epitaxiallayer (option for all TSMC and UMC, STMicro, IBM [10–13]). Third, the bipo-lar processes with high resistivity substrate and epitaxial layer and low resistivityburied layers (IBM, STMicro [12, 13]). High resistivity substrates are used for RFapplication since noise isolation is critical as well as to minimize eddy currents inthe substrate and hence enhance the quality factor of all the passive devices builton it that are critical for RF applications. Many CMOS fabrication processes todayuse a lightly doped epitaxial layer grown on top of a heavily doped bulk substrate.The lightly doped epitaxial layer provides a tightly controlled level of doping fordevice performance, while the low resistivity of the heavily doped bulk helps toprevent latchup. The buried layers are usually low resistivity p-layers at the topof the substrate that prevents inversion of the bulk regions outside the transistorchannel areas.

2.6 Substrate Model Extraction in the IC Design Flow

In the circuit design flow, the substrate model is in the form of a sub-circuit RCnetwork that represents the substrate. The resulting substrate model is consideredan additional subsystem to be electrically linked to the original design that assumesno substrate coupling. The substrate is represented by a linear multi-port network

2.7 Doping Profile Considerations 19

Fig. 2.8 Substrate as an undesired noise transfer medium

Fig. 2.8 and the role of the substrate model is to extract the admittance/impedancematrix elements representing the electrical behavior of the substrate. The substratemodel acts as a transfer function between the noise sources and the sensitive cir-cuits. The electrical behavior of the substrate transfer function is determined by theprocess parameters, layout and substrate impedance to ground. For high-resolutionanalog circuits, the substrate transfer function is designed to strongly attenuatenoise injected by digital circuits. This can be achieved by careful layout designsuch as the placement of carefully designed guard rings as will be discussed inChapter 4.

2.7 Doping Profile Considerations

In order to model the effect of substrate coupling, doping information is required tocalculate the resistivity of the silicon at different points. Doping profiles for a certainprocess can be obtained either by physical measurements on fabricated wafers orthrough accurate computer device simulators. For every process technology, thereis more than one doping profile at different regions of the fabricated devices. Inorder to simplify the substrate-modeling problem, the doping profile at each deviceregion is approximated by a stack of uniformly doped layers of silicon [14]. Thedoping concentration of each layer is the mean of the non-uniform doping profilewithin that layer. This process is called profile discretization as shown in Fig. 2.9.As the number of layers increases, a more accurate substrate model can be obtained,however there is always the trade-off between the accuracy and performance of themodeling tool. Depending on the process, modeling engineers could find a suitablerefinement level at which the accuracy is acceptable within a reasonable time frame.


Fig. 2.9 Disretization of substrate doping profiles [94]

The discretizations of doping profiles and resistivity setting are determined basedon calibrating the modeling tool to Si measurements as pre-processing steps uponwhich a process specific technology file is produced in our model strategy.

2.8 Substrate Model Extraction Kernels

Different techniques had been be employed in the literature to solve the equationsgoverning the physical problem of the substrate coupling, and then to represent itas an equivalent matrix of admittances (or impedances) connecting the terminals(ports). The most common approaches use the Finite Difference techniques andthe Boundary Element Method (Green’s function is evaluated). With the discretiza-tion of doping profiles mentioned before, the substrate can be treated as a stack ofuniformly-doped layers. In these layers, a simplified form of Maxell’s equations,that ignores the influence of the magnetic fields, can be formulated as [15]:

ε.�

�t(∇.E) + 1

ρsub∇.E = 0 (2.10)

where E is the electric field intensity vector, and �sub and �si are the sheet resistivity andthe dielectric constant of the silicon respectively. Equation (2.10) can be discretizedon the substrate volume either in differential form using the Finite Difference (FD)techniques or in integral form using the Boundary Element Methods (BEM). In gen-eral, the discretization process leads to a large matrix representing the coupling inthe substrate, which can be reduced to a simple equivalent macro-model connecting

2.8 Substrate Model Extraction Kernels 21

the substrate sub-system ports. Before matrix reduction, the Finite Difference methodproduces a large sparse matrix regardless of the number of the substrate ports. Integralapproaches, such as using the Boundary Element Methods, produce a matrix size thatis proportional to the number of ports. Although the matrix size is much smaller inBEM, the matrix is very dense and must be inverted, a rather computationally intensiveprocess [16, 95]. Hence there is a compromise between accuracy and complexity inthe two famous techniques found in the literature. The industry standard tool used inthe book uses the finite difference method.

2.8.1 Finite Difference Method

Extraction of the substrate macromodel requires the solution of the Laplace equationin the substrate. Solution of partial differential equations by the use of numericaltechniques has been studied extensively and has been presented by several authors[17, 18]. These techniques usually involve approximating the differential equationsof the system by difference equations. The resulting matrix is then solved using amethod, which is appropriate for the matrix size involved. One of these methodsis the finite difference technique. The Finite Difference approach is widely used inmodeling the substrate behavior [19, 20]. In this approach, the silicon substrate ismodeled as a three-dimensional resistor mesh. Layers of the doping profiles, com-bined with the device layout geometrical structures, constitute a matrix of cubiodsas shown in Fig. 2.10.

Every cuboid is modeled as a resistor in parallel with a capacitor [21]. The valuesof the resistors in the mesh are determined from the process information (layer sheetresistivity or doping density) and the geometry defined by the layout. As indicatedearlier, the capacitance can be neglected except for the well-to-substrate junctioncapacitance. The resulting resistance mesh interconnects the substrate ports and

Fig. 2.10 Representing a substrate by a mesh of resistors [95]


models the electrical behavior of the substrate. The 3D mesh network connectingthe ports of the substrate can then be reduced and translated into a SPICE sub-circuit consisting of resistors mesh. The sub-circuit could be used to simulate thesubstrate coupling using a typical circuit simulator such as SPICE3. Being a purelynumerical technique, the accuracy of the obtained solution is highly dependent onthe resolution of the discretization [22]. Because of its accuracy at high resolutions,the FD method is useful for high accuracy with complex substrate profiles, whereanalytical methods can be rather complicated [23,95] this is why this method is usedin the industry standard tool extracting the substrate model.

2.8.2 Boundary Element Method

The Boundary Element Method of extracting the substrate resistances is an analyt-ical method that starts with discretizing each port on the substrate into a collectionof panels [24]. This method is based on using Green’s function of the substrate.The Green’s function for a medium is defined as the potential at any point in themedium with suitable boundary conditions due to a unit current injected at any pointwithin the medium [24]. The Green function can be analytically determined for thesubstrate as in [25]. Using Green’s function of the substrate, the impedance matrixrepresenting the substrate behavior is analytically evaluated. The impedance matrixis then inverted to obtain the substrate admittance matrix [22, 26]. The substrateresistance between the ports is then obtained as the reciprocal of the sum of thecorresponding admittance matrix elements. A major advantage of the BEM is thatit is not as sensitive to discretization as the Finite Difference technique. As men-tioned earlier, the resulting matrix of BEM methods is much smaller; however, thecomputational advantage of having a dramatically smaller matrix is limited by thefact that the impedance matrix to be inverted is fully dense (unlike the sparse matrixgenerated by FD method). If heuristics are further employed, the resulting matrixmay be sparsified.

2.8.3 Comparison Between the Two Techniques

Two techniques have been presented in the literature for computing the substratemacro-models. The first technique is purely numerical while the second utilizes acombination of numerical and analytical methods. The primary advantage of thesecond technique is the speed of computation, which was found to be significantlysuperior to the numerical technique for small structures. The computation time inthe numerical scheme is small for a small number of grid points, but becomes largeas the number of points is increased. For achieving good accuracy, the memoryrequirement of the numerical technique is seen to be very large. An advantage ofthe purely numerical technique is its versatility. The technique can be used to modellateral variations in resistivity without any overheads, unlike the analytical method.

2.8 Substrate Model Extraction Kernels 23

The power of the analytically based technique lies in the fact that meshing needs tobe done only in the region of the contacts, not in the bulk unlike the FD method thatis applied to the 3-D substrate. Hence BEM reduces the problem from a 3-D problemto a 2-D problem. In the analytical technique the number of mesh points rises rapidlywith the number of contacts. Another disadvantage of the numerical technique isthat for optimization, if a single contact is varied, then the entire problem has to berecomputed. This is not a problem with the BEM [95].

2.8.4 Approximations in the Model Extraction Algorithm

Trade-offs between accuracy and simulation time are inevitable, as low computationtimes are usually achieved by ignoring some of the second order effects in the simu-lation. In the modeling technique a lumped equivalent macromodel representing thesubstrate is extracted by solving the differential equations representing the medium.The lumped macromodel relates the voltage and the current vectors at the substratecontacts. Several approximations must be made in order to extract the macromodelin a reasonable amount of time. The approximations involved, their validity and thepoint at which the approximations fail are discussed below.

2.8.4.1 The Electrostatic Assumptions

The first approximation involved is that of considering the substrate as a resistiveonly media with no capacitance and inductance effects as discussed in Section 2.4.3.This approximation is accurate at low to moderate frequencies but it fails at fre-quencies above ∼15 GHz in typical silicon substrates of approximately 10 �-cm.Another side of this approximation is to ignore any radiation and wave phenomenain the substrate; this is valid in integrated circuit substrates because the dimensionsof the substrates are typically much smaller than the smallest electrical wavelengths,thus distributed effects are not observed in the substrates. Above these frequenciescomplete solution of Maxwell’s equations is necessary. Another deviation from theelectrostatic model will occur when the vertical dimensions of the substrates becomecomparable to the skin depth in the medium. The skin-effect makes the resistancebetween two contacts on the surface frequency-dependent. The computational sim-plification achieved from the electrostatic assumption is enormous. Solution of theMaxwell equations in the substrate involves the solution of two inhomogeneouswave equations [27]. In the electrostatic approximation the scalar potential in thesubstrate satisfies the Laplace equation, and very efficient numerical techniques forparasitic extraction can be developed. The key inference is that the low frequencyformulas suffice for first-order impedance estimates at most frequencies of interest.

2.8.4.2 The Linearity Assumption

The conductivity of the silicon substrate is dependent on the electric field in the sub-strate. Thus the current-field relationship is nonlinear in silicon. This effect becomes


significant at high-fields or at high current densities. The injection of minority-carriers can also make the conductivity time, location and field dependent. Theminority-carrier leakage is avoided by reverse-biasing the devices-substrate junc-tions. The conductivity of the silicon layers is assumed to be a constant, indepen-dent of the field. It is also assumed to be isotropic. Several nonlinear effects areconsidered in device simulators. These tools, however, are completely unsuitablefor parasitic extraction due to the large computation times involved in even one ortwo devices problems.

2.8.4.3 The Equipotential Assumption

The devices-to-substrate junctions are treated as equipotential contacts with the sur-face. A more accurate model of the junction would consider the devices-to-substratejunction as a depleted semiconductor region (a dielectric). This model is difficult toimplement in a fast substrate noise simulator, since the extent of the depletion regiondepends on the voltage across the junction. The magnitude of the error from thisapproximation is reduced considerably due to the small dimensions of the devicescompared to the substrate. Thus, while the instantaneous variations of the voltageacross the reverse-biased junction may change the value of the depletion capacitanceconsiderably, the change in the value of the substrate model impedance values isexpected to be small. The nonlinear behavior of the junction capacitors is includedin circuit simulators such as SPICE.

2.9 Conclusion

In this chapter the device models are studied to accurately identify the devices-substrate interface. The injection, reception and transmission mechanisms in thesubstrate are studied together with the solvers that are used for extracting the sub-strate model.

Chapter 3Experimental Data to Calibrate the Design Flow

3.1 Introduction

In the previous chapter the ingredients of a design flow that models the substratenoise coupling phenomena are studied. The design flow put together is summarizedin Fig. 3.1. It starts by defining the devices-substrate interface and integrating thisin the runsets (rule files) used for layout vs. schematic check and layout parasiticextraction. The rule files decides based on the substrate-devices interface what toinclude in the substrate model and what to leave behind as part of device models.The layout data is used to identify the geometries, interconnectivity and locationof the devices and the substrate isolation structures that are designed. The processstack information and doping profile are another input to the solver. The abovementioned inputs are fed to the substrate model extraction kernel. A commerciallyavailable tool [58] that represents the industry standard is used as the extractionkernel. Figure 3.2 shows the test bench used to simulate the isolation structures withthe substrate RC model as part of this test bench. The test bench has two signal portsfor the two port single ended scattering parameters simulation that is performed onthe substrate model. The substrate model is extracted based on the layout structuresthat are presented in the next section. To calibrate this design environment a testchip is designed and measured to compare silicon measurements to the simulationresults and ensure that the design environment used is accurately predicting siliconbehavior. Once this calibration is done the use of the design environment and sub-strate model extraction and simulations will be extended to other isolation structuresto come up with a design guide for substrate noise isolation using circuit techniques,floor planning and substrate isolation structures [96,97]. Then the environment willbe used to assess the impact of substrate noise on device, circuit and system levels.Remedies are then given based on the design guide. Next, they are validated toensure that the impact of substrate noise coupling on the circuit performance isminimized.


26 3 Experimental Data to Calibrate the Design Flow

Fig. 3.1 The design flow used to characterize substrate noise coupling

Fig. 3.2 The test bench used to simulate the substrate model of the isolation structures

3.2 The Test Chip

A test chip is designed taped out and measured to assess the impact of differentsubstrate isolation techniques on the substrate noise coupling. The substrate isola-tion (or crosstalk) characterization is performed on a high resistive substrate of aBICMOS process wafers with a substrate resistivity of 10 �-cm. The test chip usedfor this characterization contained various substrate crosstalk reduction structures.

3.2 The Test Chip 27

The purpose of this test chip is to calibrate the design flow used to model thesubstrate network to silicon data and not to measure all the various options of thesubstrate isolation structures which occupy large die area. Thus, a limited set ofstructures are designed and measured that scans the process technology featuresused for isolation, while different sizes and geometries are deferred for being sim-ulated using the calibrated design flow. The frequency characteristics of substrateisolation structures are a function of their vertical and lateral constructions. Thevertical construction parameters include substrate resistivity, doping profile, waferthickness, and thicknesses of all the process wells (n-well, deep n-well, p-well).The lateral construction parameters include the isolation structures between the twocircuit blocks that acts as the receiver and the transmitter of the substrate noise andtheir geometries and relative location on silicon. A metallic ohmic-contact was madeto the back surface of the die and was connected to the measurement system groundduring the testing. The inductance used in the simulations for the backplane contactto match the measurements is 0.1 nH. The different lateral isolation techniques arediscussed in the next sections.

Figure 3.3 shows the die photograph of the test chip. The test chip has on waferprobing RF GSG (ground-signal-ground) pads that are used to measure the scatter-ing parameter of the substrate structures vs. frequency. The scattering parametersvs. frequency are measured using a probe station, RF probes and a 40 GHz net-work analyzer. The probe pads are designed as two port single ended structures andin some cases an extra DC probe pad is used to bias the different n-wells used.The probe pads de-embedding structures are also designed and measured to isolatethe pads and feed lines parasitics from the total scattering parameters and extract thesubstrate structures contribution alone. The de-embedding technique used in mea-surement is explained later in this chapter, while the measurement setup is discussedin Appendix B. The calibration is done by tuning the doping profile of the various

Fig. 3.3 Die photograph of the test chip used to measure the isolation of different substratestructures


isolation structures to match Si data. The structures are designed in a modular wayto tune the doping concentration of a single implant at a time. For example baselineisolation is used to tune p-sub concentration; p+ guard ring isolation is used to tunethe doping of the p+ implant used in the guard ring and so on.

3.3 Baseline Isolation

To start with baseline information, the isolation between two p+ diffusion regionsis measured. This information will be used to compare the isolation of the differ-ent isolation structures to the bare silicon isolation due to the distance between thenoise transmitter and the noise receiver. The layout used for the baseline isolationis shown in Fig. 3.4. The ground “G” pads are tapped to the substrate and to themeasurement system ground. The “G” pads are connected together in both X andY directions to form an equipotential surface that ensures accurate measurements.Without such connection the measurements were too noisy. The ground connectionin the Y direction is done using top metal layers, while that in the X direction is doneusing lower level metals as shown by the line labeled by G joining the ground padsin Fig. 3.4. This is done to prevent shorting to the signal “S” pad which is put on thetop metal layer to minimize its parasitic capacitance to the substrate. The feed linesconnect the receiver and the transmitter to the signal “S” pads. The resistance of thefeed lines and their vias together with the pad parasitic capacitance are de-embeddedto get the isolation information of the receiver and transmitter only. Two ports singleended s-parameter measurement is done and the isolation S12 in dB vs. frequency

Fig. 3.4 Layout and cross section of the structure used to measure and simulate the baselineisolation

3.3 Baseline Isolation 29

Fig. 3.5 Measurement vs. simulation for baseline isolation structure

after de-embedding is shown in Fig. 3.5. The simulation result is overlaid on themeasurement in Fig. 3.5 after tuning the doping concentration fed to the solver tomatch the Si data. The S12 values shown below are based on a setup where port 1 isthe receiver while port 2 is the transmitter as shown in Fig. 3.2.

3.3.1 Data Analysis

Both the receiver and the transmitter are p+ diffusion regions in a p-well substrate,thus they both have ohmic contact to the substrate. Since the substrate used has aresistivity of 10 �-cm it will behave as a resistive network up to the cutoff frequencyas discussed in Section 2.4.3. Thus, the equivalent model between the receiver andthe transmitter is all resistive and the S12 data looks pretty much constant up to∼15 GHz, as expected from an all resistive mesh. Beyond this frequency which isidentical to the cutoff frequency plotted in Fig. 2.7, the isolation behavior startsto depart from a resistive behavior and it starts to decrease with increasing the fre-quency due to the contribution of the distributed RC network that will now representthe substrate. The existence of capacitive impedance in the substrate due to the non-zero permittivity and the � term in Equation (2.8) will cause a drop in the isolationas frequency increases. The simulation results match the measurement up to 20 GHzthen it starts to deviate beyond 20 GHz but remains well within 0.8 dB of accuracyon the pessimistic side up to 30 GHz.


3.4 Effect of p-Guard Ring on Isolation

The first isolation structure to be studied is the p+ guard ring surrounding the p+

diffusion that acts as the receiver. Figure 3.6 shows the layout and the cross section ofthe isolation structure. The p+ ring surrounds the p+ diffusion that acts as the receiver.The guard ring is connected to the ground pads using a low ohmic contact connec-tion as shown by the connection labeled by G in Fig. 3.6. This ground connection isneeded for the ring to act as a sink to the substrate noise currents. A very low ohmiccontact to the ground connection is needed to ensure strong current sink. The layoutis also used to serve the purpose of measuring the substrate isolation if the guardring surrounds the transmitter. This is achieved by also monitoring S21 in additionto S12, i.e. flipping the roles of the noise transmitter and noise receiver during themeasurement can achieve this goal. Adding a second guard ring to simultaneouslysurround both the transmitter and the receiver can be tricky. The reason is that bothguard rings have to be grounded to sink the substrate noise current and if they areboth tied to the same ground node, this can create a short circuit path to the sub-strate noise current as shown in Fig. 3.7. If Zsh<<Zgnd adding a guard ring aroundthe transmitter will increase noise coupling to the receiver, as shown in Fig. 3.7 lefthand side diagram. If on the other hand the two guard rings are tied to two separateground nodes, isolation is enhanced as shown in Fig. 3.7 right hand side diagram.Figure 3.8 shows the measurement and simulation results of the above mentionedscenarios. The simulation tracks the measurement data fairly well up to 20 GHz,and then deviates to be within ∼2 dB from the measurement data up to 30 GHz. Inthe next chapter the simulation results comparing the different ground connectionsof Fig. 3.7 as well as the impact of the impedances of guard rings will be discussed.

Fig. 3.6 Layout and cross section of the structure used to measure and simulate the p+ guard ringisolation structure

3.4 Effect of p-Guard Ring on Isolation 31

Fig. 3.7 Careful grounding is needed not to increase substrate noise coupling

Fig. 3.8 p+ guard ring isolation once surrounding the receiver and once surrounding thetransmitter


3.4.1 Data Analysis

The isolation provided by the P+ guard ring is superior to the baseline isolation byapproximately 30 dB. The p+ guard ring can effectively eliminate the surface noisecurrent flow by sinking this noise current to the low ohmic ground connection. Asmentioned in the previous section, since p+ guard ring acts as a resistive networkdue to its ohmic contact to the substrate and the substrate behavior is resistive upto the cutoff frequency, the isolation is approximately constant “within 2 dB” up to15 GHz, then starts to degrade with frequency due to the capacitive behavior of thesubstrate beyond the cutoff frequency.

Comparing the scattering parameters shown in Fig. 3.8, it is obvious that addingP+ guard ring contact to surround the noisy circuit block “transmitter” is a moreefficient technique to reduce substrate crosstalk. The isolation in this case is largerthan the case of the p+ guard ring surrounds the receiver by approximately 2.5 dB.Putting the p+ guard ring immediately surrounding the noisy circuit attenuates thesubstrate current before it propagates through the substrate to other locations in thesystem where it is attenuated further by the distance isolation of the high resistivesubstrate. Also the impedance of the guard ring connection to ground can pick upsubstrate noise, specially at high frequency and putting the guard ring around thereceiver degrades the isolation by injecting this picked up noise into the receiver,while putting it around the transmitter leaves room for the residual noise that is notsunk to ground due to this impedance to be attenuated by the distance isolation inthe high resistive substrate.

3.5 Effect of n-Guard Ring on Isolation

The p+ guard ring in the previous section is compared to an n+ diffusion guard ring inan n-well ring isolation structure in this section. The layout of such structure is shownin Fig. 3.9. Two n-guard rings are placed around the receiver and the transmitter.Here two extra DC probe pads are needed to bias the n+ guard ring by DC suppliesto create a reverse bias p-n junction between the n rings and the p substrate. Thestructure can be used to measure the impact of a single n ring around the receiverby keeping the n ring around the transmitter floating and connecting that around thereceiver to vdd1, which will act as an ac ground to sink the substrate noise current. Itis also used to measure the impact of a single n ring around the transmitter by keepingthe n ring around the receiver floating and connecting that around the transmitter tovdd2. If both n rings are simultaneously connected to vdd1 and vdd2 respectively, theimpact of two rings is measured and compared to the above mentioned two cases.Figure 3.10 shows the measurement data for the three cases. Figure 3.11 showsthe simulation results overlaid on the measurement. A good fit is obtained betweenmeasurements and simulations up to the cutoff frequency then a deviation occurswithin 2 dB error between measurements and simulations. At such level of isola-tion ∼65 dB, 2 dB is considered within measurement error. Figure 3.12 compares thep+ guard ring and he n+ guard ring isolation technique in all of their configurations.

3.5 Effect of n-Guard Ring on Isolation 33

Fig. 3.9 Layout and cross section of the structure used to measure and simulate the n+ guard ringisolation structure

3.5.1 Data Analysis

The p-n junction between the n guard ring and the p substrate introduces high ca-pacitive impedance at low frequency. This high impedance reduces substrate noisecurrent reaching the receiver. This is shown in Fig. 3.10 by the dip in the isolation atfrequencies 0.1 GHz up to 1 GHz. Beyond this frequency, this impedance becomes

Fig. 3.10 Measurement data for n+ guard ring isolation structure


Fig. 3.11 Measurement vs. simulation for n+ guard ring isolation structure

Fig. 3.12 Comparison between isolation techniques

3.6 Effect of Deep n-Well on Isolation 35

smaller in comparison to the substrate resistive network, thus the isolation remainsalmost constant up to the cutoff frequency. Beyond this frequency the isolation isdegraded as frequency increases due to the capacitive nature of the substrate be-havior that kicks in beyond the cutoff frequency. The cutoff frequency in this caseis more than the case of the p guard ring due to the fact that the conductivity ofthe n guard ring is larger than that of the p guard ring. As shown in Fig. 3.10,putting the n guard ring around the transmitter is a more efficient isolation tech-nique. Isolation is increased by approximately 2.5 dB if compared to the isolationof the n guard ring placed around the receiver. This conclusion is similar to whatwas concluded for placing the p+ guard rings around the receiver and transmitter inthe previous section. Adding two n guard rings around both the transmitter and thereceiver provides 5 dB more isolation if compared to the isolation of a single guardring placed around the transmitter only, and 7.5 dB if compared to the isolation ofa single guard ring placed around the receiver only, provided that the ac ground ofthe guard rings are separate. The simulation results as shown in Fig. 3.11 tracks theabove mentioned behavior accurately. In Fig. 3.12 the p guard ring is compared tothe n guard ring. The n+ well guard ring provides higher isolation than P+ guardring due to its lower sheet resistivity that provides higher noise sinking ability. Forthe same doping concentration, the n guard ring is ∼2X less resistive due to theelectron mobility in the n guard ring being larger than the hole mobility in the pguard ring.

3.6 Effect of Deep n-Well on Isolation

In this section the effect of a deep n-well guard ring is compared to the p+ and the n+

guard rings. Figure 3.13 shows the layout of this structure. A p+ diffusion represent-ing the receiver is placed in a p-well that is isolated from the common p-substrate bya deep n-well implant. An n-well guard ring is designed to surround the receiver andbe on top of the deep n-well tub. An n+ diffusion is implanted and contacted in the

Fig. 3.13 Layout and cross section of the structure used to measure and simulate the deep n-wellguard ring isolation structure


n-well guard ring and connected via low resistive metal routing to the DC probe padused to bias the n-well to vdd1. The transmitter is designed exactly like the receiver,with the exception of the DC probe pad that is connected to a separate DC supplyvdd2. Figure 3.14 shows the measurement results of the isolation of this structurevs. frequency. The simulation result of the isolation is overlaid on the measurementdata. Figure 3.15 shows the measurement results comparing the isolation of the nguard ring discussed in the previous section to the isolation of the deep n-well guardring, the comparison is performed for the case of two guard rings surrounding thereceiver and the transmitter with the rings tied to separate supplies.

3.6.1 Data Analysis

The deep n-well acts as a low resistive current sink that is buried in the substrate.This will provide a sink to deep substrate noise currents and will extend the effect ofcurrent sinking from the surface to a distance deep down in the substrate. Such de-sign will enhance the isolation if compared to the regular n-well guard ring that onlyprovide current sink to surface currents. A substrate noise current is now forced todive deep in the substrate to reach the receiver, such deep path has more impedancedue to the high resistive nature of the substrate.

Figure 3.15 shows at least 5 dB of isolation enhancement of the deep n-well guardring over the n guard ring. Since the resistivity of the deep n-well is less than thep substrate, its cutoff frequency is pushed beyond the 15 GHz and the isolation re-mains more constant than the case of p guard rings. At low frequency the isolation isbetter due to the reverse biased p-n junction between the n-well and the p-substrate.Figure 3.15 shows that the low frequency behavior of the deep n-well is differentthan that of the n-well. The deep n-well isolation is more at low frequency and itdegrades with increasing the frequency slower than the n-well. The reason for thatis due to the fact that the deep n-well is more lightly doped than the regular n+ well

Fig. 3.14 Measurement and simulation data of the deep n-well guard ring isolation structure

3.7 Effect of Deep Trench on Isolation 37

Fig. 3.15 Comparison between the isolation of two deep n well guard rings and two n well guardrings

and hence the capacitance of its p-n junction with the p substrate is smaller than thatof the n+ well. Being less capacitive increases the capacitive impedance of the p-njunction and hence it takes a higher frequency for this impedance to vanish relativeto the substrate resistive network. At this higher frequency the dip in the isolation atlow frequency vanishes and the isolation reaches its plateau value.

3.7 Effect of Deep Trench on Isolation

Figure 3.16 shows the structure used to measure and simulate the effect of deeptrench on isolation. A deep trench is a trench in the silicon substrate approximately10 um deep that is filled with oxide. A ring of deep trench surrounding a noisereceiver is implemented and the isolation is measured and compared to the p guardring isolation surrounding the noise receiver. Figure 3.17 shows the measured andsimulated data of this isolation structure together with the data of the p guard ringfor comparison.

3.7.1 Data Analysis

The oxide in the deep trench acts as a high impedance insulator that forces thesubstrate noise current to dive deep in the substrate. Hence the isolation is enhancedby adding a deep trench by approximately ∼2 dB. As the frequency increases, theimpedance of the oxide tends to loose its impact and the isolation in the presence ofthe deep trench approaches that of the basic p guard ring.


Fig. 3.16 Layout and cross section of the structure used to measure and simulate the deep trenchisolation structure

Fig. 3.17 Isolation of a p guard ring with a surrounding deep trench as compared to a regular pguard ring

3.8 De-embedding

In this section the procedure that is followed to subtract the effect of the GSG probepad and feed line parasitics is explained. To create an environment which is suitablefor on-wafer RF probing, wiring (feed lines) and probe pads have to be added tothe DUT (device under test). To obtain results for the DUT only the influence of

3.8 De-embedding 39

Fig. 3.18 Layout and equivalent circuit of the GSG structure with the DUT

these additional elements has to be subtracted, i.e. de-embedded. Figure 3.18 showsa typical equivalent circuit for the DUT and the parasitics elements for on-wafermeasurements. Parasitic resistances of the feed lines are in series with the DUTwhile the parasitic signal pad capacitance is parallel to the DUT and the parasiticresistances. To de-embed the pad capacitance and feed line resistance, open andshort structures are designed as part of the test chip. The design and the equivalentcircuit of the open structure are shown in Fig. 3.19, while the short structures areshown in Fig. 3.20. Note that the open structure has the pad capacitance, and iden-tical pads and wiring, while the short structure has both pad capacitance and feedline resistance. The short is created by inserting a very low ohmic path to short thesignals to the ground pads. The procedure for de-embedding is as follows.

Fig. 3.19 Layout and equivalent circuit of the GSG open structure


Fig. 3.20 Layout and equivalent circuit of the GSG short structure

Step 1Convert measured S to Y parametersSmeas,DUT → Ymeas,DUT

Smeas, Short → Ymeas, Short

Smeas,Open → Ymeas,Open

Step 2De-embed DUT and short from parallel pad parasiticsYmeas,DUT-Ymeas,Open = YDUT-Open

Ymeas, Short-Ymeas,Open = YShort-Open

Step 3Convert Y to Z parametersYDUT-Open → ZDUT-Open

YShort-Open → ZShort-Open

Step 4De-embed DUT (without open) from serial resistive parasitics (Short with-out open)ZDUT-Open-ZShort-Open = ZDUT

Step 5Convert DUT’s Z to S parametersZDUT → SDUT

The Y, Z, S parameters are related to each other as given in [28]. Appendix Bexplains the measurement details.

3.9 Conclusion 41

3.9 Conclusion

In this chapter the measurement results of a test chip is presented. The test chiphas different substrate isolation structures that will be used extensively in the nextchapters. The goal of this test chip is two folds. First, is to calibrate the designflow used in simulating the substrate noise coupling and second is to compare isola-tion structures and learn what isolation structures are most efficient for substratenoise isolation as well as the design parameters involved, grounding techniquesand measurement procedures to de-embed the DUT data. The simulation results arecompared to the measurement data and found to be accurate to within 2 dB of themeasurement data across the entire frequency range used. Lots of learning about theefficient usage of isolation structures is captured to be part of the substrate isolationdesign guide presented in the next chapter.

Chapter 4Design Guide for Substrate Noise Isolationin RF Applications

4.1 Introduction

In this chapter a novel substrate noise isolation design guide is developed. Thedevelopment of the design guide is based on the design environment flow studied inChapter 2 that is calibrated to silicon measurements in Chapter 3. First the leaningsfrom the design experiments performed in the previous chapter are discussed whichfocuses on the frequency behavior of the different isolation structures. Next, a se-ries of simulations are performed to expand the design guide to target three majorcategories of factors that affect the noise isolation. First, the backplane connectionis studied and its impact on isolation is highlighted. The frequency dependence ofthe isolation and the impact of the backplane impedance are considered. Second,the isolation as a function of: the geometrical parameters of the isolation structures,the electrical parameters of the substrate, mainly the substrate resistivity, the induc-tance of the bond wires connected to the isolation structures and the frequency ofoperation. Different grounding techniques of the isolation structures are also stud-ied. Third, the chip floor plan and the design of the power and ground domains toenhance isolation. The design guide will be limited to the substrate noise couplingas applied to RF applications, and hence the focus will be only on high resistiv-ity substrates (∼10 �-cm, which is the substrate of choice for this application, asdiscussed in Section 2.5), as well as the RF frequency of operation.

4.2 Isolation in Low Resistivity Substrate

Low resistivity substrates are used in digital CMOS applications as discussed inSection 2.5. In this case the substrate noise currents find a low impedance path inthe substrate bulk and are able to penetrate easily deep in the bulk, the majority ofthe currents pass through the bulk and the surface components of these currents areminimum. Thus, in this case, the surface isolation structures such as guard ringsare ineffective in providing noise isolation. Same applies to the inductance of thebond wires attached to the guard rings. This inductance becomes ineffective for low


44 4 Design Guide for Substrate Noise Isolation in RF Applications

resistivity substrate since almost all the noise is not conducted thought the surfaceof the wafer where the guard rings exist and where their inductances matter. Largegains in substrate isolation are achieved only by lowering the inductance of the waferbackplane connection. This behavior can be expected in low resistivity substratesbecause current flow in these substrates is mostly through the bulk, and providinglow impedance to the backplane acts as a good sink to the noise current in the sub-strate bulk [29]. Guard rings on the other hand are an effective current sink for onlythe surface component of the current which dominates in high resistive substrates.Also the distance between the noise transmitter and receiver is not effective beyond4X of the epi thickness in low resistive substrates [30].

4.3 Isolation vs. Frequency for Different Isolation Structures

The findings of the previous chapter are summarized below to provide a designguide for different isolation structures and their frequency dependence.

Design Guide 1: Baseline isolation (isolation between ohmic contacts to the sub-strate in the absence of any isolation structure) is constant with frequency up to thecutoff frequency. Beyond the cutoff frequency the isolation degrades as frequencyincreases. It is recommended to select the resistivity of the process technology lowenough to ensure a high cutoff frequency and high enough to ensure low substrateeddy current losses.

Design Guide 2: A P+ guard ring with low impedance to ground surroundingthe noise receiver provides better isolation if compared to the baseline isolation at allfrequencies. The guard ring acts as a current sink to the surface noise currents whichare the dominant noise currents in high resistive substrates. The bulk impedance ishigh thus forces noise currents to the surface.

Design Guide 3: Isolation due to P+ guard rings is constant with frequency fornoise receivers and transmitters that are contacting the substrate via ohmic contacts,up to the cutoff frequency. The frequency dependency is not as constant if com-pared to the baseline isolation due to the fact that the impedance of the guard ringconnection to ground increases with frequency hence it weakens the current sinkingcapability of the guard ring as frequency increases.

Design Guide 4: Placing the guard ring around the noise transmitter is a moreeffective isolation technique than placing it around the noise receiver.

Design Guide 5: N+ guard rings provide better isolation than P+ guard ringsspecially at low frequency due to the capacitive nature of the p-n junction that pro-vides high impedance to noise currents at low frequency. As frequency increases theisolation of the N+ ring approaches that of the P+ ring, but still remains better dueto the lower resistivity of the N+ ring which acts as a better sink if compared to theP+ ring of the same geometry at the same frequency of operation.

Design Guide 6: Placing two N+ rings to surround the noise receiver and trans-mitter provides better isolation than a single ring as long as the two rings are con-nected to separate supply lines.

4.4 Effect of Back Plane Connection on the Noise Isolation in High Resistivity Substrates 45

Design Guide 7: As the frequency increases and the guard ring impedance toground increases, the current sinking capability of the ring vanishes and the iso-lation approaches the baseline isolation. Thus, it is crucial to ground the substrateisolation structures using very low impedance connections to keep their effect up tothe frequency of interest.

Design Guide 8: A deep n-well N+ guard ring provides more isolation if com-pared to the N+ guard ring and has a better isolation vs. frequency. Deep n-wellforces the noise current to penetrate deeper in the substrate where it faces highimpedance. Also the low frequency isolation is superior to the N+ guard ring be-cause the deep n-well is lightly doped than the n-well and hence its capacitance tothe substrate is lower, thus its impedance is higher and the isolation degrades slowerwith frequency.

Design Guide 9: A deep trench ring provides more isolation than the baselineand enhances the GR isolation if placed around it.

4.4 Effect of Back Plane Connection on the Noise Isolationin High Resistivity Substrates

The isolation between two surface contacts in a high resistive substrate is simulatedwith and without backplane contact to study the impact of grounding the backplaneon the noise isolation. Figure 4.1 shows the layout of the structure simulated. Twobaseline p+ diffusions are placed in a p substrate structure similar to that used tomeasure the baseline isolation vs. frequency. The parameters that are varied in thesimulation are the following: The simulation frequency is set to 1 GHz and 10 GHz.The backplane inductance is set to 0.1 nH and 2 nH. The distance between the con-tacts is varied from 10 um to 400 um. Figure 4.2 shows the simulation results forthe case with no backplane “bp” i.e. floating the backplane of the wafer at two

Fig. 4.1 Test structure used to simulate the backplane impact on isolation for resistive coupling


Fig. 4.2 Baseline isolation for resistive coupling vs. backplane inductance

frequencies, and then it shows four plots with different frequencies and backplaneinductances. Examining the simulation results in Fig. 4.2, the following designguides are deducted.

Design Guide 10: grounding the backplane of the high resistive substrate pro-vides approximately 5 dB more isolation at small distances (low bulk current) and∼10 dB more isolation at large distances (higher bulk current) if compared to thefloating backplane substrate. Grounding the backplane provides a path to groundfor the bulk noise currents and hence improves the isolation. The improvement isnot significant (few dB) since it is hard for the noise currents to get to the waferbackplane due to the high resistivity of the substrate. The percentage of the noisecurrents that can make it to the backplane increases with frequency as the frequencyapproaches the cutoff frequency and the substrate capacitive impedance starts tolower the overall substrate impedance, but the impedance of the bp inductance in-creases with frequency and its sinking ability decreases.

Design Guide 11: Minimizing the inductance of the backplane slightly enhancesthe isolation. Small inductance provides a better ground current sink to the bulkcomponent, while the improvement is mild due to the fact that backplane current inhigh resistive substrate is not the main noise current path.

Design Guide 12: The isolation gets better as the distance between the noisetransmitter and noise receiver increases. The distance driven isolation saturates asthe distance gets large if compared to the receiver and transmitter areas.

Design Guide 13: The baseline isolation is relatively frequency independent aslong as the frequency remains well below the cutoff frequency and the coupling tosubstrate is ohmic.

For noise sources that are capacitively coupled to the substrate the structure inFig. 4.3 is simulated. The noise transmitter is now a MOS capacitor that is capaci-tively coupled to the substrate via the gate capacitance. Now the isolation becomes a

4.4 Effect of Back Plane Connection on the Noise Isolation in High Resistivity Substrates 47

Fig. 4.3 Test structure used to simulate the backplane impact on isolation for capacitive coupling

function of frequency, with a large enhancement at low frequency. Figure 4.4 showsthe simulation result for the case of capacitive coupling.

Design Guide 14: The isolation at low frequency is enhanced by ∼20 dB relativeto the resistive coupling case. At high frequency ∼10 GHz the improvement in iso-lation due to the capacitive coupling nearly vanishes. The capacitance of the MOScap introduces high impedance at low frequency that diminishes the amount of noisethat is coupled to the substrate relative to the ohmic case. As frequency increasesthe capacitive impedance decreases and the isolation approaches the ohmic case.

Going forward, since grounding the backplane provides better isolation; all theupcoming simulated structures will have the backplane grounded with L = 0.01 nH.

Fig. 4.4 Baseline isolation for capacitive coupling


4.5 Substrate Contacts: Frontside or Backside? Both

In all cases where an electrical contact to the substrate is desired, front side sub-strate contacts are the best recommended way to provide that contact. In otherwords, if a contact to the chip substrate is desired, making a contact to the chipbackside through a conductive mounting is not sufficient. The chip backside mayhave a residual oxide coating that prevents an adequate electrical contact. Also inmost of the situations the chip backside is not metallized. However, it should beunderstood that some electrical contact is likely to exist if the chip is placed ona conductive mounting i.e. the chip backside is not a guaranteed insulator. Sinceit is desirable to maintain the chip substrate at an equipotential to provide a goodAC ground, contact to the chip substrate is desired. The recommended method isto provide many contacts on the front side tied to a good AC ground. Additionally,placing the chip on a conductive mounting and biasing the chip backside to the samepotential as the front side substrate contacts will provide enhanced AC grounding.The connection between the front side contact potential and the backside shouldbe made as symmetrically as possible in order to maintain an equipotential on thebackside. The DC potential of the substrate should be such that the substrate is al-ways reverse-biased with respect to all N-type diffusions. Floating the chip backsideby either not connecting the conductive mounting to any potential, or by mountingon a nonconductive surface, is allowed, but is not recommended as discussed in theprevious section. The design of front side contacts to the substrate “guard rings” isdiscussed next.

4.6 P+ Guard Ring Isolation

In mixed analog-digital designs, a common layout design practice is to use guardrings to improve noise isolation. Because of the uncertainty about the amount ofadditional isolation provided by guard rings, designers may use guard rings thatprovide little isolation or may increase noise coupling. This fact necessitates thequantitative understanding of the isolation provided by the guard rings. It is alsobeneficial in avoiding unnecessary engineering time and area overhead. Guard ringscan be either majority rings, where the guard ring diffusion is of the same type asthe substrate doping (p+ in p-type substrate or n+ in an n-type substrate), or mi-nority rings, where the ring diffusion is of the opposite type of the substrate doping.Figure 4.5 shows the structure that is simulated. The geometrical and the electricalparameters are varied in the next sections to study the impact of D, w, d, LGR, freq,and � on the isolation and compile the design guide lines for designing the guardring. Unless otherwise stated the following are assumed as defaults: D = 120 um,d = 10 um, w = 3 um, LG R = 0.01 nH, f req = 1 GHz, ρ = 10 �-cm.

4.6 P+ Guard Ring Isolation 49

Fig. 4.5 Test structure used to simulate the impact of guard rings on isolation

4.6.1 Guard Ring Isolation vs. D

Figure 4.6 shows the simulation results of noise isolation vs. D for different fre-quencies and guard ring inductances.

Design Guide 15: for all cases, isolation improves with distance “D”.

Fig. 4.6 Guard ring Isolation vs. distance D


Design Guide 16: At low f∗L as the case of L = 0.01 nH and f = 1, 10 GHz,the isolation is enhanced by ∼10 dB as D is changed from 20 um to 400 um. Whileat high f∗L as the case of L = 2, 4 nH the isolation is enhanced by ∼20 dB. Thusthe dependence of the isolation on the distance D is not effective at low guard ringinductance as compared to the cases of high guard ring inductance. This is becausethe isolation is mainly provided by the guard ring sinking the noise current at lowinductance, and increasing the distance adds only slight improvement. While at highinductance the sinking capability is weakened and the distance can contribute moreto the isolation.

Design Guide 17: in all cases the dI/dD is max at low D, thus increasing thedistance leads to diminishing return especially at low inductance.

Design Guide 18: Isolation at both high and low frequencies is very close invalue as long as the inductance is very low. This is because the high frequency isstill below cutoff freq and the guard ring is still a good sink even at high freq due tothe low inductance. This will change in the case of capacitive coupling, where lowfreq isolation is improved significantly.

Design Guide 19: As f and L both go up, D becomes effective in providingisolation. This indicates that more current flows in the substrate and not sunk by theGR. As D increases the isolation is improved since the current that is flowing in thesubstrate faces more impedance.

Design Guide 20: At high f and L the GR approaches being floating and theisolation approaches that of the baseline. In real situations this LGR will inject noisedue to mutual inductance of the neighbor bond wires; in such case the GR is worsethan the baseline, as will be discussed later in this chapter.

4.6.2 Guard Ring Grounding Scheme

Figure 4.7 shows the structure used to simulate the effect of different groundingtechniques on the guard ring isolation. In case B both guard rings are connected tothe same bond wire inductance LGR1, while case A has separate guard ring bondwire connections. As discussed in Section 3.4 and Fig. 3.7, the simulation results ofthe different situations is presented in Fig. 4.8.

Design Guide 21: Figure 4.8 shows that the guard ring is more effective at thetransmitter, dual rings provides better isolation as long as they have separate groundconnections. Tying both rings to the same bond wire injects more noise around thereceiver and degrades isolation.

4.6.3 Guard Ring Isolation vs. d

Next is to study the impact of the guard ring to the noise receiver distance on iso-lation. The distance “d” shown in Fig. 4.5 is varied in a series of simulations thatvary other geometrical and electrical parameters to understand in depth the physical


Fig. 4.7 Guard ring grounding schemes

Fig. 4.8 Guard ring grounding scheme simulation data LGR = 1 nH


Fig. 4.9 Guard ring Isolation vs. distance “d”

phenomena governing the substrate noise isolation. Examining Figs. 4.9 and 4.10yields several design guides.

Design Guide 22: A guard ring that is tightly enclosing the noise receiver pro-vides up to ∼7 dB of extra isolation if compared to a guard ring that is away fromthe noise receiver, as long as the guard ring inductance to ground is kept very small.The degradation in isolation saturates as the enclosure distance “d” increases.

Design Guide 23: As the guard ring inductance increases and as the frequencyincreases the guard ring losses its current sinking capability and its contribution tothe noise isolation. In this case the enclosure distance plays fewer roles in improving

Fig. 4.10 Guard ring isolation vs. distance “d”


the isolation. This is shown in Fig. 4.10 where the isolation improvement due to asmaller distance “d” gets less as f∗L increases. Again it is noticed that the isolationvalue approaches its baseline value as f∗L increases.

Design Guide 24: The increase in isolation due to increasing the distance “D” ismore for a higher resistive substrate. In other words the rate of change of isolationvs. distance “D” dI/dD is directly proportional to ρ. As seen in Fig. 4.9 on the left,the delta in isolation between D = 120 um and D = 400 um when � = 10 �-cmis less than that on the right when � = 50 �-cm. As � gets higher, increasing thedistance “D” causes the impedance between the noise source and noise receiver toincrease rapidly if compared to a lower �.

Design Guide 25: The rate of change of isolation vs. substrate resistivity dI/dρis directly proportional to D. As shown in Fig. 4.9 the delta in the isolation curve onthe top left vs. the top right is smaller than that of the bottom left vs. the bottom right.At small distance “D” changing the substrate resistivity won’t change the isolationmuch if compared to the case of larger “D”.

Design Guide 26: for all cases, isolation improves with substrate resistivity.

4.6.4 Guard Ring Isolation vs. “w”

Figure 4.11 shows the structure used to simulate the relation between the widthof the guard ring and isolation. In this study, the impact of noise coupled to theguard ring through neighbor bond wire inductance is also highlighted. Bond wiresof signals or ground and supply lines that are close to the sensitive circuitry maybe switching at high rates and introduce noise to the guard ring under considerationthrough the mutual coupling between the bond wire inductors.

Fig. 4.11 Structure used to simulate guard ring isolation vs. distance “w”


Fig. 4.12 Guard ring Isolation vs. ring width “w”

Figure 4.12 shows four plots of isolation vs. ring width for different parameterswith and without Vnoise. The bottom two plots have very low ring inductance, whilethe top two plots have high guard ring inductance and high frequency of operation.In the two cases noise is added to see the impact of noise coupling on the isolationbetween the noise transmitter and the noise receiver.

Design Guide 27: For low guard ring inductance, increasing the ring width de-creases its resistivity and provides more current sinking capability and hence betterisolation ∼5 dB. The isolation improvement vanishes at higher “w”, compromisebetween area and isolation improvement is needed.

Design Guide 28: Even in the presence of noise coupling, as long as the guardring inductance is kept very small, the guard ring will sink the coupled noise andisolation will not be degraded, this is clear by examining Fig. 4.12 bottom plot withnoise added, which gives nearly the same isolation as the case where no noise isadded, since L is 0.01 nH in this case. This inductance gives ∼60 m� at f = 1 GHz,which provides a good ground to sink the coupled noise.

Design Guide 29: As f∗L increase the guard ring looses its sinking capabilityand the isolation is degraded, in such case the width of the guard ring becomes anineffective way of providing isolation. In the presence of coupled noise and high f∗La wider guard ring will pick more noise than a narrow ring and isolation degradesbeyond baseline (with no ring altogether).

Design Guide 30: since wider guard rings provide only slight isolation improve-ment and they may inject more noise if coupled to a noisy bond wire, narrowerguard rings with very low inductance to ground are recommended.

Design Guide 31: During chip floor planning, it is highly recommended tospatially separate the noisy signals from sensitive circuits, both on chip as far asmetal and interconnect routing and on the package by separating the bond wires ofthese pins.

4.7 P+ and N+ Guard Rings Isolation 55

4.7 P+ and N+ Guard Rings Isolation

As shown in the previous chapter, adding an N well guard ring provides extra iso-lation if compared to the P guard ring. In the section below both rings are usedsimultaneously to study the impact of a dual guard ring on isolation. Figure 4.13shows the structure used in the simulation, both guard ring connection inductancesare assumed to be very low. The enclosure distance between the receiver and thep guard ring is kept equal to the distance between both rings. This will allow usto isolate the effect of adding the N well guard ring from other parameters. Thefrequency used in the simulation is high enough to remove the low frequency isola-tion enhancement introduced by the capacitive impedance of the p-n junction that isformed between the N well and the P substrate; doing so will ease the comparisonand rule out the parameters that are not present in the case of a P guard ring alone.N guard ring provide extra isolation at high frequency by forming a deep and rela-tively wide current sink area and thus forces the noise currents to deviate deeper inthe substrate. While its pn capacitance enhances the low frequency isolation.

Figure 4.14 shows the simulation results that compare the isolation of a P guardring alone to the case of dual P and N guard rings surrounding the noise receiver.Enclosure distance “d” is varied on the X axis. The substrate resistivity is variedgoing across the charts at a fixed transmitter to a receiver distance “D”, while goingdown, the distance “D” is changed at a fixed substrate resistivity. Examining thecharts below yields the following guide lines:

Fig. 4.13 P and N Guard ring isolation structure


Fig. 4.14 P and N guard ring isolation vs. enclosure distance “d”

Design Guide 32: Adding an N guard ring to the P guard ring consistently im-proves the isolation.

Design Guide 33: The isolation improvement is best at lower substrate resistivityand lower distance “D”. The delta in isolation is reduced moving across the chartsand also is reduced moving down the charts. This could be explained as follows; theincrease in substrate resistance in the case of small D and small � introduced by theuse of n-well ring is significant compared to the original substrate resistance, andtherefore the effect is significant. For the case of large D and large � the change issmall compared to the original substrate resistance and that results in a lower delta.

4.8 Floor Planning Techniques to Minimize Coupling

The next step in the design guide is to design the floor plan and the power domains ofthe chip to minimize substrate noise coupling. Figure 4.15 shows the recommendedmethodology for floor planning. The guide line is to spatially separate the buildingblocks based on their analog and digital nature as well as the voltage amplitudeand frequency of switching. Each block should be surrounded by a guard ring, or adual guard ring connected to a low impedance bond wire, in some cases two bondwires in parallel are used to minimize inductance to ground. In some situations the

4.8 Floor Planning Techniques to Minimize Coupling 57

Fig. 4.15 Floor planning to minimize substrate noise coupling

floor planning may contradict with the signal routing, so the floor plan below isrecommended as long as it is practical to implement vs. other constrains. The powerdomains of each block should be kept separate to avoid noise coupling throughthe switching power supplies. Figure 4.16 summarizes the correct placement andbiasing of the guard rings and ground lines.

The backplane of the die is glued with metal epoxy to the package ground metalplane. This ground metal plane is connected to the external bottom plane of thepackage and connected to the PCB to establish the “external” system ground. Theon die pads that are connected to the different ground domains “internal grounds”are tied down to the package ground plane using bond wires. These on die groundpads are connected to the different guard rings. The guard rings and the grounddomains are designed to reduce substrate coupling by limiting the injected noiseand sinking the transmitted noise. To do so, the digital and analog transistors aretreated differently. The switching digital transistor sources are separated from thetransistor bulks. The sources and bulks are connected to two separate guard ringsas shown in Fig. 4.16 top left section. Doing so will prevent the switching noisefrom being injected to the bulk which is connected directly to the substrate. Toreduce the effect of the current which reaches the bulk, a low-impedance returnpath is of uttermost importance [30]. For heavily doped substrates, the best result isobtained by mounting the die with conductive epoxy to the lead frame using severalbond wires to connect it to the external ground. Eventually, large substrate contacts


Fig. 4.16 Placements and biasing of the guard rings and ground lines

with a dedicated pin filling spare places on the chip can be an alternative. In lightlydoped substrates where most currents flow just underneath the chip surface, a guardring with dedicated pin surrounding the digital block is an effective return pad. Inthese substrates, physical separation of noise sources and sensitive circuits is alsovery effective as the resistance in the noise path continuously increases with thedistance. Substrate noise disturbs the analog circuits through their bulk to sourcevoltage. To reduce this bulk effect, bulk source voltage variations of analog MOStransistors should be minimized. The bulk must thus be tied locally to the analogreference “on die” rather than to the (slightly different) external one “on package”.This is achieved with bulk contacts close to the analog transistors and biased with thelocal analog ground, which results in an optimal output voltage relative to the localon-chip analog reference (analog reference or analog ground in most cases are thesources of MOS devices). A guard ring with dedicated pin around the analog circuitseventually enhances the noise immunity even further [30], but does not eliminatethe need of the good bulk contacts to the local analog ground. For a SiGe processwhere bipolar transistors are more frequently used than MOS transistors the bulkterminal of the bipolar transistors that represent their contact to the substrate asdiscussed in Chapter 2 is connected to a ground pin that is separate from the emittersof the bipolars. Same applies to the bulk of all passive devices in the process. Suchseparation will prevent noise due to the switching transistors to be injected in thebulk and cause substrate injected noise.

4.9 Circuit Techniques to Minimize Coupling 59

Another layout technique to minimize the substrate noise coupling is throughcareful routing. Digital signals should not be routed over or through the analogportion of the chip, or be routed next to sensitive lines. The floor plan should ensurethat the package pin assignment does not route sensitive analog signals near digitalI/Os, supplies, or clock signals.

4.9 Circuit Techniques to Minimize Coupling

Differential circuits are always recommended over single-ended circuits in noisyenvironments [35]. Substrate noise is not an exception. The noise, due to its randomnature, appears as a common-mode signal on the differential outputs. The differen-tial noise signal is typically several orders of magnitude smaller than what would beobserved in a single-ended implementation of the circuit. In this section, the use ofguard rings in differential circuits to reduce substrate noise is discussed. Figure 4.17shows a simple asymmetric differential layout, with both p+ and n-well rings used.The two noise receivers of the structure “a” and “b” are placed asymmetrically withrespect to the noise source. If the noise source is placed symmetrical to the receivers,the differential noise will be close to zero. The simulation results of the baselineisolation, isolation using a p+ guard ring only to surround the two receivers, andthe isolation when dual p+ and n well guard rings are used to surround the noisereceivers are shown in Fig. 4.18.

The delta in the isolation numbers of noise receivers a and b in the case of thebaseline isolation is shown on the left hand side of Fig. 4.18 to be 3.1 dB. On theright hand side of Fig. 4.18 the delta is 1.78 dB in the case of a p guard ring onlysurrounding the noise receivers and 0.43 dB in the case of a dual guard ring.

Fig. 4.17 Layout used to simulate the impact of guard rings on differential noise


Fig. 4.18 Differential isolation using p guard ring and dual p and n-well guard rings

Design Guide 34: A dual guard ring when used for differential configurations,equalize noise coupling on the two sides of the differential structure and decreasethe differential noise if compared to the p guard ring alone. P guard ring minimizesthe differential noise if compared to the baseline isolation.

4.10 Active Guard Rings

Substrate noise suppression circuits are being discussed in several researches[31–34]. The basic idea is to use the passive guard ring in addition to active guardband circuits to sense the substrate noise signal at a specific location and inject anopposite signal in another location to cancel the substrate noise at a target sensitivelocation. This technique proved to provide around 10 dB of extra isolation up to100 MHz, the limitations of this technique is as follows. First the idea is based oncanceling the noise that can reach deep into the substrate bulk, because surface noisecan be suppressed by passive guard rings. Hence, this technique is more suitable tolow resistive substrates and not to high resistive substrates. Second, this techniqueused circuits like operational amplifiers to generate the negative of the noise source;such circuits have a limited band width, thus limiting the effectiveness of this tech-nique to frequencies below the cutoff frequency of the active circuitry. Implementingthese circuits as a high bandwidth designs adds to the complexity and overhead ofthe design. Third, the application of this technique is suitable for small designs,while for large designs it won’t be practical to repeat this circuits several times tosuppress noise in several locations on the chip.

4.11 Conclusion

A novel design guide for the substrate noise isolation structures is developed in thischapter based on a test chip and a deign environment calibrated to measurements.The focus was the RF applications and the substrate types used for such application

4.11 Conclusion 61

together with the frequency band of operation of these applications. The differenttechniques of the isolation structures are studied together with the electrical andgeometrical parameters that affect their performance and guide lines are providedto minimize substrate noise coupling. Next the layout and floor planning, power do-mains and guard ring grounding techniques are discussed. The interaction betweenthe package and the die to define the internal and external grounds is discussed and adifferentiation is made between digital and analog transistors for ground connectionconsideration. The methodology of ground and bulk connection is also highlightedfor CMOS and bipolar process technologies.

Chapter 5On Chip Inductors Design Flow

5.1 Introduction

The performance of on-chip spiral inductors is heavily dependent on the substrateproperties. Further, the substrate isolation structures placed around the inductorscan impact the inductor performance even further. In this chapter a design flowis developed to accurately design and model on chip spiral inductors taken intoconsideration all the substrate properties and interaction effects. The impact of theisolation structures interaction will be studied in the next chapter.

Inductors are used in various RF and wireless circuit’s applications. Main appli-cations are in low noise amplifiers, power amplifiers and LC tank voltage controlledoscillators. Other mixed signal applications are found in high speed serial IO circuitapplications such as band width extension, clock drivers and current peaking. At theheart of any RF receiver is the PLL frequency synthesizer and VCOs. Early researchefforts for the monolithic CMOS VCO had focused on the design and implemen-tation of high-Q resonator components, especially integrated inductors, to achievelow phase noise at an acceptable level of power consumption [36–38]. The two im-portant challenges to implement RF VCOs in a fully integrated RF transceiver are;(i) on-chip noise coupling through cross-talk between blocks and substrate (ii) CMOSfabrication tolerances (process variation) [44]. Fully integrated PLL frequency syn-thesizer solution must address top level implementation issues as well as individualblock design issues. In the next chapter on-chip noise coupling through cross-talkbetween blocks and substrate is studied, while in this chapter a design flow for de-signing on chip inductors that take into consideration design for manufacturing, suchas metal density fill, bump effects for flip chip applications, as well as the processand temperature variations impact on the inductors performance are studied.

5.2 Integrated Inductors

Inductors can be implemented in three different ways in an IC technology; (i) ex-ternal off-chip inductors (ii) packaging bond-wires as inductors (iii) on-chip spiralinductors. The use of external inductors is not preferred with CMOS technologyfor several reasons. The pin parasitics of the package will limit the usable values


64 5 On Chip Inductors Design Flow

of inductors, since cross coupling caps will limit the inductor values especially forinductance larger than 3–4 nH. In addition, the crosstalk paths between pins willinject noise into the resonator tank and degrade the noise performance of the VCO.Also, ESD (electro-static discharge) protection networks in CMOS are probably themajor factor preventing the implementation of external resonator tanks. Althoughbondwire inductors have a very high quality factor, they are not commonly usedin VCOs because of lack of reproducibility and mechanical stability. An excellentreview of design and implementation of bondwire inductors can be found in thereference [36]. On-chip integrated inductors are favored over off-chip ones becausepad and bond wire parasitics are eliminated. Also, on-chip inductors exhibit goodreproducibility since the inductor value is mainly determined by horizontal dimen-sions which are tightly controlled by lithographic resolution in any CMOS tech-nology. The major drawback of on-chip inductors is the low-Q factor and large diearea. On-chip integrated inductors are built in spiral geometries including squares,octagons and circles. Compared to a circular inductor, a square spiral inductor haslarger inductance-to-area ratio but contributes more series resistance which is due tolonger overall metal length for a given inductance value. Therefore, a spiral structurethat more closely approximates a circle (whenever technology permits) is preferredto increase the quality factor. While a square spiral is recommended when highinductance is of more priority than a high quality factor.

For RF applications, the most important parameter for an integrated inductor isthe quality factor. High quality factor directly impact the phase noise of the fre-quency synthesizer and directly affects the wireless channels spacing and frequencyplanning. The quality factor of integrated inductors in CMOS technology suffersfrom three main loss mechanisms; metal sheet resistance (ohmic loss), capacitivecoupling to the substrate, and magnetic coupling to the substrate [39]. Approachesto reduce these losses and obtain high Q on-chip inductors are as follows; Reducemetal sheet resistance by using thicker metallization [40], stacking of metal layers,and using lower resistivity metals (e.g. copper) [41]. Make the dielectric layer be-tween metal layers and the substrate as thick as possible by using top metal layers.Reduce substrate losses by using high-resistivity substrate [45], by selectively re-moving the underlying substrate with post-fabrication steps [42], by using patternedground shield. (This method is quite useful for low resistivity substrates) [43]. Allapproaches depend on the technology parameters. Modern RF CMOS technologiesoffer a thick top metal layer between 2 and 10 um on a medium resistivity substrate(1 �-cm < � < 20 �-cm). One of the key issues in the use of an on-chip inductor ina circuit design is the adequate prediction of its behavior. A straightforward methodused by CMOS foundries is to fabricate and measure a whole batch of inductorswith varying geometries. A library of inductors is obtained from measurement data.This library is also extended by fitting measurement data to simple models. Thefitted simple models allow only changes in one of the geometry parameters aroundmeasured inductors, and hence limiting the available inductors to a certain subsetof the measured inductors. This is obviously not well suited for optimum inductordesign since the maximum Q and the smallest die are needed at a given frequencyof interest.

5.4 Analytical Exploration of the Design Space 65

5.3 Inductor Design Flow

The inductor design flow that is developed in this book allows the designer todesign “custom” inductors that fit the design needs and restrictions. This gives moredegrees of freedom than what a fixed library of limited set of inductors can offer,without sacrificing accuracy. The flow starts by defining the inductor specification.Table 5.1 lists the entire set of the parameters that should be taken care of duringdesigning the inductor. The list is extended beyond what is found in the literature toaccommodate very important design for manufacturing parameters that affects theinductor yield and render the inductors production worthy.

Although there is much focus in the literature on L, Q, fr, there is not much focuson design for manufacturing effects, Maximum DC and rms currents, bump pitch,metal density, metal fill “dummification” and metal design rules. Such rules are vitalfor a production worthy inductors. These DFM rules will limit the inductor designspace and limit the available inductors for a specific application. These specifica-tions should all be met while minimizing the inductor area. Figure 5.1 shows theflow chart of the design flow.

5.4 Analytical Exploration of the Design Space

Closed form analytical formulas are studied in the literature to calculate the L and Qof on chip spiral inductors. The inductance is much easier to calculate analyticallysince its value at high frequency is close to its DC value, given that the inductor isused well below the self resonance frequency, thus the complexity of high frequencyeffects is not included in the inductance calculation. The work presented in [46] isused to analytically predict the inductance of square and octagonal inductors. Theformula works fairly well although it assumes an asymmetric, fully planar struc-ture. However, cross-overs and underpasses are ignored by the formula. Serial andparallel inductors can not be handled accurately by the formula, but the analyticalresults for L gives a good starting point in exploring the design space. Quality factoris much more complex to predict due to the many high frequency factors involved.

Table 5.1 Set of parametersthat should be consideredduring designing the inductor

Inductance LDesired minimum quality factor Q at the operating

frequency foThe operating frequency foMinimum self resonance frequency frMaximum DC currentMaximum rms currentBump pitch for flip chipMaximum metal density rulesMetal design rules, maximum width, minimum width,

minimum spacing


Fig. 5.1 Inductor design flow

Beside DC ohmic loss, the following contribute to the quality factor: skin effect,proximity effect, eddy current losses in the substrate, cross coupling capacitancebetween inductor turns, side way capacitance between the inductor turns, capacitivecoupling with the substrate.

For the quality factor, the physical model in [47] is employed. This model ac-counts for the substrate losses and capacitance, oxide capacitance, inductor resis-tance and self-capacitance. Of these, the self-capacitance is the most approximatebecause it requires a careful analysis of the cross-overs and underpasses in the lay-out. The current approximation assumes an underpass and simple capacitive cou-pling between the top inductor level and the next. The self-capacitance that existswhen the inductor is not planar is not accounted for at all. Both these equations areimplemented in a matlab program that takes as inputs (inductor desired L and Q,range of inductor number of turns N, coil width W, turns spacing S, operating fre-quency and maximum outer diameter OD) and gives as an output the design spacecontours. The set of parameters fed to the program (W, S, N, OD) must take intoconsideration the specific technology design rules and electro-migration specs. Forexample the range of metal spacing S should start at a number that is greater than theminimum metal spacing allowed by the technology design “lithography” rule. Alsothe maximum metal width range should stop at the maximum metal width allowed,or in this case if more metal width is needed, metal slotting should be accountedfor in quality factor and inductance estimation. Metal slotting example is shown inFig. 5.2, together with the parameters definition. This figure shows a parallel induc-tor with two metal layers stacked in parallel, the top metal is usually wide enoughand hence slotting is not needed, the metal layer below the top is what is shownand what needs slotting in most cases. Moreover, the two metal layers are “viad”


Fig. 5.2 Inductor layout showing design parameters and some DFM rules

together to minimize over all resistance. Metal density rules is also a very importantrestriction that should be accounted for. In all modern CMOS technologies, eachmetal layer has a minimum and maximum metal density that should be met in agiven area. For example top metal layer density in a 50 um × 50 um area windowshould be more than 20% but less than 80%. Such rule is needed to avoid manufac-turing problems and ensure uniform litho patterns. Such rule will put a combinedrestriction on the number of turns, coil width and turns spacing collectively. So somecalculations must be carried to make sure that the ranges entered in the contour plotswill meet all the DFM and design rules simultaneously.

Figures 5.3–5.5 shows the L and Q contours of an octagonal inductor as a func-tion of outer diameter on the y-axis and metal width on the x-axis. The number ofturns N, and turns spacing S are given in different plots to avoid more than two di-mensional plots. The contours can be used to study the trade off between the designparameters (OD, W, S, N) to achieve the desired L and Q. L is targeted first since itis more accurate to predict. Q is targeted second, given OD bump distance limitationon the inductor area, (in flip chip application the inductors must be centered awayfrom the package bumps to avoid the interaction of the inductor magnetic fields withthe metal bumps, which degrades L and Q of the inductor) and W and S design rulesand density limitations. Although the analytical formula gives a good initial estimateon the L and Q, it does not talk into account the following: Stacked metal and itseddy current coupling, metal thickness, side wall capacitance and cross couplingcapacitance between the turns, via resistivity.

The current density in a wire is uniform at dc; however, as frequency increases,the current density becomes non uniform due to the formation of eddy currents. Theeddy current effect occurs when a conductor is subjected to time-varying magneticfields and is governed by Faraday’s law [48,49]. Eddy currents manifest themselvesas skin and proximity effects. In accordance with Lenz’s law, eddy currents produce


Fig. 5.3 L contours as a function of OD and W at a given N and S

their own magnetic fields to oppose the original field. In the case of the skin effect,the time-varying magnetic field due to the current flow in a conductor induces eddycurrents in the conductor itself. The proximity effect takes place when a conduc-tor is under the influence of a time-varying field produced by a nearby conductorcarrying a time-varying current. In this case, eddy currents are induced whether ornot the first conductor carries current. This is essentially a transformer action. If thefirst conductor does carry a time-varying current, then the skin-effect eddy currentand the proximity-effect eddy current superimpose to form the total eddy currentdistribution. Regardless of the induction mechanism, eddy currents reduce the netcurrent flow in the conductor and hence increase the ac resistance. The distributionof eddy currents depends on the geometry of the conductor and its orientation withrespect to the impinging time-varying magnetic field. The most critical parameterpertaining to eddy current effects is the skin depth � which is defined as

δ =√

ρ

πμ f(5.1)

where �, � and f represent the resistivity in �-m, permeability in H/m, and frequencyin Hz, respectively. The skin depth is also known as the “depth of penetration” since


Fig. 5.4 Q contours as a function of OD and W at a given N and S

it describes the degree of penetration by the electric current and magnetic flux intothe surface of a conductor at high frequencies. The severity of the eddy current effectis determined by the ratio of skin depth to the conductor thickness. The eddy currenteffect is negligible only if the depth of penetration is much greater than the conduc-tor thickness. Skin effect reduces the benefit of very thick top metal layers found inmodern processes. No matter how thick the metal layer is, if the skin depth is smallerthan the metal thickness the ac resistance will be skin depth limited. Since a spiralinductor is a multi-conductor structure, eddy currents can potentially be caused byboth proximity and skin effects. Eddy currents can also be induced in the substrateand dissipate energy which degrades the Q. Figure 5.6 shows the quality factor asa function of frequency and the different factors impacting the Q as a function offrequency.

Because of the above limitations in the analytical formula, a 3D field solver thatsolves Maxwell’s Equations [50] and that is calibrated to Silicon measurements isused to fine tune the design and include all the above mentioned effects. The outputof the solver is a scattering parameter file that models the inductor. Once the designis finalized a compact macro model that is frequency independent is developed torepresent a broad band fit to the sp data. Such macro model is used in the circuitanalysis that uses the inductor in the next chapter.


Fig. 5.5 L, Q contours as a function of OD and W at a different N and S

5.5 Inductor Model and Substrate Parasitics 71

Fig. 5.6 Q vs. f showing different losses mechanisms

5.5 Inductor Model and Substrate Parasitics

The differential inductor model developed is shown in Fig. 5.7. The model is sym-metrical around the center tap pin “port 3”. Three parallel sections of inductorsare used to model the distributed inductance effect of each half of the differentialinductor Lsec, Lsec1, Lsec2. The three inductors are “de-qued” by series resistorsthat model ohmic losses, skin effect and proximity effect losses in the windingsRsec, Rsec1, Rsec2. Ccoup models the turn to turn capacitance and capacitanceto the underpass and the cross under. The center tap has its inductor and resistorRct and Lct. Mutual coupling coefficient K1 models the positive mutual inductancebetween the two halves of the differential inductor. The substrate loss of the centertap is modeled by Csh2 and Rsh2, while the major substrate network is that assignedto port 1 and port 2. Cox models the oxide capacitance between the inductor metal

Fig. 5.7 Differential inductor macro model


coils and the substrate, Csh1 and Rsh1 model the capacitive and resistive substratemodel as discussed in Chapter 2. They also model the ohmic, eddy and displacementcurrent induced in the substrate. The model is parameterized and a circuit optimizeris used to find the values of the 15 parameters of the model that fits the sp fileproduced by the 3D field solver. Figure 5.8 shows the test bench used to performsuch optimization.

The test bench has the sp module that results from the 3D field solver connectedto ports 3 and 4, while the macro model shown above is connected to ports 1 and 2.Sp simulation is run and six measurement equations are set and six correspondingoptimization goals are minimized. The goal here is to match the sp of the macromodel to the sp of the 3D solver. The first four measurement equations and goals areused to optimize the difference in sp between the sp file and the model to zero. Whilethe second goals are used to optimize the delta Qdiff “DQ” and delta Ldiff “DL”

S111 = mag((S(1, 1) − S(3, 3))/S(3, 3)) (5.2)

S221 = mag((S(2, 2) − S(4, 4))/S(4, 4)) (5.3)

S121 = mag((S(1, 2) − S(3, 4))/S(3, 4)) (5.4)

S211 = mag((S(2, 1) − S(4, 3))/S(4, 3)) (5.5)

DQ = (imag(Z (1, 1) + Z (2, 2) − 2∗Z (1, 2))/real(Z (1, 1) + Z (2, 2)

−2∗Z (1, 2)) − imag(Z (3, 3) + Z (4, 4) − 2∗Z (3, 4))/real(Z (3, 3)

+Z (4, 4) − 2∗Z (3, 4)))/ imag(Z (3, 3) + Z (4, 4) − 2∗Z (3, 4))

/real(Z (3, 3) + Z (4, 4) − 2∗Z (3, 4)) (5.6)

DL = ((imag(Z (1, 1) + Z (2, 2) − 2∗Z (1, 2))/(2∗ pi∗ f req))

−(imag(Z (3, 3) + Z (4, 4) − 2∗Z (3, 4))/(2∗ pi∗ f req)))

/(imag(Z (3, 3) + Z (4, 4) − 2∗Z (3, 4))/(2∗ pi∗ f req)) (5.7)

The physical origin of Rsh1 is the silicon conductivity which is predominately de-termined by the majority carrier concentration. Csh1 models the high-frequency ca-pacitive effects occurring in the semiconductor as discussed in Chapter 2. For spiralinductors on silicon, the lateral dimensions are typically a few hundred micro-meterswhich is much larger than the oxide thickness and is comparable to the silicon thick-ness. Hence, the substrate capacitance and resistance are approx. proportional to thearea occupied by the inductor and can be estimated by a // plate formula

Cox = 1

2A.εox

tox(5.8)

5.5Inductor

Modeland

SubstrateParasitics

73

Fig. 5.8 Test bench used to extract model parameters


Csh1 = 1

2A.Csub (5.9)

Rsh1 = 2

A.Gsub(5.10)

where A is the inductor total area, εox and tox denotes the dielectric constant andthickness of the oxide layer between the inductor and the substrate. Csub and Gsubare capacitance and conductance per unit area for the silicon substrate.

5.6 Calibrating the Field Solver

The field solver is fed with the dielectric and metal stack information which in-clude the conductivities, thicknesses, relative distances and dielectric constants ofthe metal layers used in the process technology as well as the dielectric layers. Thesimulation is compared to the measured data, and the stack information is tweakedto match the measurements. The measurement was done over the corners of thedesign space, to ensure scalability. In most cases the DC inductance was close tothe analytical prediction (not the L at fo, which is not predicted by the analyticalformula) while Q of the analytical formula was off by ∼20–25% depending on thefrequency and the inductor geometry and topology. Figure 5.9 shows the simulationvs. measurement for three differential inductors designed using a stack of the up-per two metal layers. The relevant process information is summarized in Table 5.2.Figure 5.9 shows the simulation vs. measurement data after de-embedding. AppendixB explains the measurement details. The inductor parameters are shown on the plotsand they vary from 180 �m outer diameter to 120 �m, and coil width of 11 �mto 4.7 �m. The target differential inductance is 3.6 nH @ 3.2 GHz and Qmin is8 @ 3.2 GHz. Figure 5.10 is a zoom in on the inductance chart near the oper-ating frequency as well as the three dimensional view of the stacked differentialinductor. Measurement and de-embedding technique is identical to that discussed inChapter 2.

Fig. 5.9 Q and L simulation vs. measurement

5.7 Model Fit 75

Table 5.2 Processinformation relevant to theinductor design

Top metal thickness = 1 �mn–1 metal thickness = 0.6 �mtop metal distance to substrate = 5 �mn–1 metal distance to substrate = 4 �msheet rho of top metal layer = 20 �/�sheet rho of n–1 metal layer = 35 �/�Substrate resistivity = 10 �-cm

Fig. 5.10 Q and L simulation vs. measurement zoom in (left), parallel differential inductor (right)

Figure 5.9 illustrates the effect of layout area on three inductors with the sameinductance but different layout parameters. Three 3.6-nH inductors are designedwith outer dimensions equal to 180, 155, and 120 �m. The inductors fabricatedusing larger area can accommodate wider line width; and as a result, achieve lowerdc series resistance. However, they also have more shunt substrate parasitics be-cause they occupy larger area. At low frequencies, the larger inductors offer higherquality factors because of lower series resistance. At high frequencies, the sub-strate effects dominate and the smaller inductors actually achieve higher qualityfactors.

5.7 Model Fit

The distributed inductor topology together with the substrate network discussedabove shows an excellent fit to the sp file generated by the 3D field solver overa broad frequency range. The model together with the optimization methodologyprovides a perfect fit for a very wide range of inductors of different geometries,topologies and frequency of operation. Figure 5.11 shows the Qdiff f (differentialquality factor based on the sp file “f”) overlaid on the Qdiff m (differential quality


Fig. 5.11 Q and L macro model fit vs. sp file and percentage error

factor based on the macro model “m”). DQ1 and DL1 are the percentage errorsbetween the sp file and the macro model. The inductor parameters are shown inFig. 5.12, together with the macro model and the fitting parameters. The specs are3.6 nH at 3.2 GHz and Qmin is 8 at 3.2 GHz. The same model topology is used atan operating frequency of 10 GHz as shown in Fig. 5.13. In this case also the modelaccuracy is well within 5% of the sp file across a broad band of frequency. The selfresonance, peak frequency and DC inductance are also accurately captured by themacro model shown in Fig. 5.14.

Fig. 5.12a Inductor physicalparameters

5.8 DFM Effects 77

Fig. 5.12b Inductor macro model and its fitting parameters

5.8 DFM Effects

In this section the impact of the design for manufacturing effects on the inductorperformance is studied. The effects are namely, placing an inductor near a bump,process, temperature variation and metal fill. Placing the inductor near a metal bumpdisturbs the magnetic flux that is coupled to the inductor and hence the L and Qof the inductor are impacted. Metal fill or dummification is the process by whichalmost all the process layers as well as vias are required to be present in a specificsize target window (the window size and the window stepping distance depend onthe layer under study) such that its density should be larger than a minimum andsmaller than a maximum percentage density. In oxide chemical-mechanical pol-ishing (CMP) processes, layout pattern dependent variation in the inter level di-electric (ILD) thickness can reduce yield and impact circuit performance. Metal-fillpatterning practices have emerged as a technique for substantially reducing layoutpattern dependent ILD thickness variation [52, 53]. Since inductors occupy largearea, waiving the metal fill in the inductor area can impact the inductor yield andrender it malfunctioning. Process and temperature variation will impact the dielec-tric and metal stack relative location, dielectric constant and metal conductivity aswell as substrate resistivity; such parameters have a direct impact on the inductorperformance.

785

On

Chip

InductorsD

esignFlow

Fig. 5.13 Q and L macro model fit vs. sp file and percentage error (left) inductor parameters (right)

5.8 DFM Effects 79

Fig. 5.14 Macro model fitting parameters

5.8.1 Impact of Bumps

Figure 5.15 shows three relative positions of an on-chip inductor relative to thepackage bumps. The distance “d” is varied and the impact of the bump locationon the L and Q of the inductor is simulated and results are given in Fig. 5.16. Thesimulations compare the inductor performance without bumps and with the bumpsspaced at d = 40 um, 20 um, 5 um and 15 um. The middle Fig. 5.15 shows thed = −15 um which is an overlap of 15 um between the inductor body and the bumps.

Fig. 5.15 Bump relative positions to the on-chip inductor


Fig. 5.16 Impact of bumps on the inductor Q and L (OD = 120 um, W = 4.7 um, S = 0.6 um,N = 5)

Also the case where the bump is right on top of the inductor is compared. Thesimulation results show that unless the inductor is centered between the bumps andkept away by at least 20 um, the Q and L will be impacted badly. The worse casescenario is when the bump is right on top of the inductor. In this case the Q droppedby more than 50% and L dropped by more than 60%. The overlap case is also notrecommended since Q lost 16% of its value at the operating frequency and L lostabout 14% of its DC value. When the distance d = 5 um the Q and L lose about5% of their value, while when d = 20 um the Q, L are almost not affected (only 1%degradation if compared to the no bump case).

5.8.2 Impact of Temperature Variation

The impact of temperature on the inductor performance is studied in this section.The substrate resistivity increases as the temperature increases due to the decreasein carrier mobility at high temperature that is caused by the increase in lattice vi-bration and lattice scattering of the carriers [51]. The thermal motion of the carriersat high temperature also adds to the increase in substrate resistivity as temperaturerises. Increase in substrate resistivity enhances the inductor quality factor becauseof less substrate induced eddy currents and capacitively coupled currents. On theother hand the metal resistivity rises with temperature and this increases the inductor

5.8 DFM Effects 81

Fig. 5.17 Impact of temperature on the inductor Q and L

ohmic loss, which will negatively impact the inductor quality factor. Thus two phe-nomena are competing for the inductor quality factor, and their individual impactis approximately balanced out. Figure 5.17 shows the simulations results of suchimpact. The substrate and metal temperatures are increased one at a time and thenthey are simultaneously increased to get the combined effect. The inductance is notimpacted much by the variation is temperature as it depends mainly on the geometryof the structure; the self resonance is very slightly impacted, while the quality factoris impacted. Compared to room temperature, the combined impact of substrate andmetal resistivity change degrades the inductor Q by about 5%. This indicated thatthe ohmic loss at this operating frequency (3.2 GHz) is more dominant than thesubstrate losses.

The increase of substrate resistivity helps improve Q, especially at the higherfrequencies. The overall relative change in peak Q is ∼5%. At low frequencies,room temperature and substrate-only curves overlap because substrate coupling isrelatively negligible. Likewise, the low-frequency portions of metal-only and metaland substrate curves overlap because metal loss is predominant at low frequencies.

Fig. 5.18 Impact of process variation on inductor performance


5.8.3 Impact of Process Variation

The process technology corners or process “skews” impact the metal and dielectricstack parameters and their relative positions. The metal conductivities, dielectricconstants and doping concentration vary from wafer to wafer and from lot to lot.This variation must be taken into consideration during design and modeling the in-ductors. Figure 5.18 shows the simulation results of the Q and L plots of an inductor(OD = 120 um, W = 4.7 um, S = 0.6 um, N = 5) under typical, slow and fastprocess corners. These process corners are the three sigma process window for themetal and dielectric stack parameters. Such variation should be used in conjunctionwith the transistor model process, voltage and temperature corners during the circuitdesign where inductors are used. Table 5.3 shows the process corners definition andhow relative thicknesses are changed and their impact on the parasitic interconnectresistance and capacitance. It is clear that for the slow corner where the resistanceis less than the typical value and capacitance is more than the typical value, the Qincreases and the self resonance decreases. For the fast corner the reverse is true.Both process and temperature variations model can be combined for the inductor.This will yield nine corners (slow cold, slow room, slow hot, typical cold, typicalroom, typical hot, fast cold, fast room, fast hot) and used in “PVT” process, voltage,temperature simulations during circuit design and validation. The design should berobust enough to accommodate the inductor performance variation across processand temperature.

5.8.4 Impact of Metal Fill

Metal fill is the processes by which metals, poly, vias and diffusion are added tothe layout as dummy cells to ensure uniform density of all layers that is needed toprevent inter level dielectric ILD “dishing” or valley formation if there are very highand/or very low density areas [52, 53]. Adding metal dummies in the neighborhoodof on chip inductors, if not designed properly can increase capacitive coupling andeddy currents that may impact the inductor performance. Figures 5.19, 5.20 and5.21 shows the dummy fill patterns that are recommended to minimize the impact onthe inductor performance. Small islands of metal are symmetrically spaced aroundthe inductor coil. Figure 5.19 (left) shows how the metal fill of the top metal layeris placed around the inductor top metal; much less dense islands are placed nearthe inductor, while denser metal fill is placed away from the inductor. The middlefigure shows the n–1 metal fill together with the n–1 metal coil (inductor is designedusing top metal and n–1 metal stacked in parallel). The figure on the right is the

Table 5.3 Process corner definition

Skew ILD Thickness Metal Thickness R C

fast Increase Decrease Increase Decreaseslow Decrease Increase Decrease Increase

5.8 DFM Effects 83

Fig. 5.19a Inductor with top metal fill pattern

Fig. 5.19b Inductor with n–1 metal fill pattern

Fig. 5.19c Inductor with n–2 metal fill pattern


Fig. 5.20a Inductor with metal fill patterns for other metal layers

Fig. 5.20b Inductor with poly and diffusion fill patterns

Fig. 5.21 Inductor with via fill patterns

5.9 Conclusion 85

Fig. 5.22 Impact of dummification on Q and L

pattern of the n–2 metal, note the less dense pattern under the inductor body tominimize capacitive coupling. Figure 5.20 (left) shows the pattern of the rest ofthe metal layers, while the one on the (right) shows the poly and diffusion pattern.Figure 5.21 shows the dummy via fill pattern, no via is stacked together to minimizecapacitive coupling to the substrate. The impact of the dummy fill on the Q and Lof the differential inductor is shown in Fig. 5.22. This dummification technique hasa minimal impact of L, while the Q is impacted by less than 4%.

5.9 Conclusion

In this chapter an inductor design flow is developed based on analytical formulasthat explore the design space and a commercial 3D field solver that is calibrated tosilicon measurements and that takes into account the substrate parasitics not mod-eled in the analytical formula. A special emphasis is put on the substrate effects thatimpact the on chip inductor performance. A compact macro model is developed thatshows a very good fit to the sp file over a broad frequency band. The design formanufacturing effects is studied and design recommendations are given to designthe on chip inductors taking into consideration yield implications and process andtemperature variations.

Chapter 6Case Studies for the Impacts and Remediesof Substrate Noise Coupling

6.1 Introduction

The problem of substrate noise coupling on the system level is very hard to attack.As the number of devices in the design increases it becomes difficult to take theentire system netlist to a simulator and simulate the over all system performance.Simulation time and simulator capacity become two major road blocks in any pro-duction worthy design. The interconnect parasitics within blocks and those of thetop level routing that connect blocks together adds to the size of the netlist andin many cases causes the simulator to run out of capacity and/or face conversionand runtime issues specially in RF designs where the simulations are based oncomplex Harmonic balance [54] or periodic steady state algorithms [55]. If weare to add to that the substrate model of the entire system to simulate the noisecoupling between major blocks specially in the presence of the digital signal pro-cessing block or a high power interfering signal “blocker”, we will be making itharder for the design environment to handle the problem. For such system levelvalidation problems the industry has come with fast spice simulators and behaviorlevel modeling to aid the issue of system level verification, but both have theirlimitations. First fast spice solvers are transient only based and in an RF chipwhere inter-modulation and phase noise with and without a blocker are impor-tant, it requires very careful simulation setups and fast Fourier transformation togo back and forth between transient and frequency domains and in going backand forth quantization errors are inevitable, in addition to the simulation setupsand runtime hurdles. For behavioral modeling it is fairly impossible to model thesubstrate noise coupling except if you take measurements and fit Si data to thebehavioral model, which is too late in the design cycle. Also scalability is anotherissue in the behavioral modeling. In our design flow the substrate network is se-lectively added only to critical portions of the system where substrate couplingmatters, while the rest of the system remains without such model to achieve theneeded compromise between accuracy on one side and capacity and speed on theother side.


88 6 Case Studies for the Impacts and Remedies of Substrate Noise Coupling

6.2 System Level Case Study

Our case study for the substrate noise coupling on the system level can be summa-rized as follows. The design at hand is a quad band RF front end receiver for cellularapplication. Figure 6.1 shows the high level block diagram of such receiver [56].Four LNA’s are present to handle the quad band input signal. A VCO representingthe local oscillator “LO” and the LO path, that contains the frequency dividers, feedsa quadrature mixer for frequency down conversion. A filter with an automatic gaincontrol is used to produce the final quadrature signals. A digital controller blockreceivers a serial interface input and provides control signals to all the blocks onchip. Two versions of this chip were measured, version A and B, and the problemstatement is as follows.

Version A was marginally meeting some system specs while failing others, someof its blocks were not meeting the block spec. Version B, the enhanced version, wasmeeting all the block specs. For the entire system, the carrier to noise ratio C/N ofthe entire receiver chain in the presence of a strong CW (continuous wave) blockersignal 3 MHz away from the carrier at the high band (1.9 GHz) is failing the spec.,(Version A does not have this specific problem). So the goal of this study is to: usethe substrate noise coupling design flow developed and calibrated in Chapters 2and 3 and the design guide developed in chapter four to analyze the VCO andblocker signals coupling through the substrate for the two versions of the chip, andlook for discrepancies that may explain the different blocker performance on thetwo designs, then provide a solution for this problem to pass the system spec.

6.2.1 Background

The phase noise “PN” performance of an LO signal plays a key role for the overallperformance of the wireless system by determining how closely channels can be

Fig. 6.1 Block diagram of the RF receiver used in the case study

6.2 System Level Case Study 89

placed in narrow-band systems and how closely constellation points can be placedin the I/Q plane in digital modulated systems. The first PN specification dictatesthe phase noise power level with respect to carrier at a given offset frequencyfrom the carrier (dBc/Hz). This specification is usually important in narrow-bandsystems such as cellular systems. The cellular standards strictly define the radioperformance parameters in great details for efficient use of the licensed RF bandsto accommodate more users. The second PN specification dictates the integratedphase noise performance over the signal bandwidth. The second specification isusually more important in broadband systems (WLAN) where high data rate istransmitted to a short distance using a wide bandwidth channel [44]. The PNspecification of a frequency synthesizer at a given offset frequency can be deter-mined from the wireless standard specified blocker performance [38]. The unde-sired sideband energy from the LO phase noise reciprocal mixes with the in-bandor out-of-band undesired signals to generate the interfering signal, I, within thedesired signal band. The power levels for blockers along with the desired signaland the required BER “bit error rate”, which translates to a minimum C/I at thereceiver output, are given by the RF standards. It is assumed that a system noisefloor, N, which include receiver front end noise (from antenna to mixer output) ispresent at the mixer output. The interfering signal I generated by reciprocal mix-ing of blocker with the phase noise at the mixer output will add up to the receivernoise in the desired band as shown in Fig. 6.2. The total undesired signal levelat the mixer output will be the sum of the front-end system noise and interfer-ing signal caused by reciprocal mixing N + I . The phase noise specification forgiven blocker levels and C/I at specified frequency can be calculated using theequation [44].

P N( fspec) < Pd − Pb( fspec) − 10 log(BW ) − C/I (6.1)

Fig. 6.2 LO phase noise specification


where:

P N( fspec) in dbc/Hz is the phase noise specification of the LO signal at thefrequency offset, fspec.

Pd in dbm is the desired signal power level.Pb( fspec) in dbm is the blocker power level at the frequency offset, fspec.BW in Hz is the signal bandwidth.C/I in db is the required minimum carrier-to-interference level.

It should be noted that blockers degrade the receiver performance in three differ-ent mechanisms; reciprocal mixing (local oscillator phase noise), gain desensitiza-tion (compression of amplifier, 1-dB compression point), and inter-modulation (IM)distortion. Reciprocal mixing effect has been discussed above. The gain desensiti-zation and IM distortion have implications on the front-end linearity. Furthermore,there will be other interfering signals falling into the desired band in addition to theinterferer caused by the blockers. The other interferer will come from image signals,second-order distortion (IP2), and spurious mixing products (2RF-3LO, etc.). Theinput IP2 performance is of particular significance in a direct-conversion (zero IF)receiver since second order nonlinearity effects can down-convert continuous wave(CW) as well as AM modulated blockers to DC or near DC. The image signal ismore of a concern for low IF and wide-band IF receiver architectures. The spuri-ous mixing products appear in wide-band IF receivers. These should be taken intoconsideration in the calculation receiver specification [44].

6.2.2 Design Data

Figure 6.3 and Table 6.1 shows the design data for this case study.The specs of the high band (1.9 GHz) C/N is 9 dB, while the design calculations

assumes 12.5 dB, which is 3.5 dB better than the spec. Per silicon measurement

Fig. 6.3 LO phase noise mixing data


Table 6.1 Calculations for the receiver chain

With no blocker and 80 kHz BW,Cout = −99 + 12 + 10 = −77 dBm,Nout1 = thermal noise power + 10 log(BW) + Gain1 + Gain2 + NF1 + NF2/Gain1Nout1 = −174 + 10 log(80 k) + 12 + 10 + 2 + 12/10 = −99 dBmThus C/N (no blocker) = 22 dB

With Pb = −26 dBm, PN = −135 dBc/HzNout2 = PN + 10 log(BW) + Pb∗Gain1∗Gain2 + Nout1Nout2 = −135 + 49 + −26 + 12 + 10 + Nout1 = −90 dBm + Nout1

= −90 dBm − 99 dBm = −89.5 dBmThus C/N (with blocker) = 12.5 dB

data, of the breakouts, each block was meeting its spec specially the VCO phasenoise, yet the carrier to noise ratio in the presence of a strong CW blocker signal3 MHz away from the carrier was failing spec by 1 to 2 dB. Since all the blockspecs were met, the focus is shifted to the top level block interaction namely theinterconnect parasitics that may couple undesirable noise between blocks as wellas the underlying substrate as a media that propagate noise, which may add to theoutput noise and degrades the C/N ratio. As shown in Fig. 6.3, the phase noise ofthe local oscillator (1.9 GHz) at 3 MHz mixes with the 3 MHz blocker and producesnoise at the carrier that decrease the carrier to noise ratio. The model for the extranoise that may cause the C/N to degrade further is shown in Fig. 6.4. The signalof the VCO core that is running at 3.8 GHz can mix with the 2nd harmonic of thehigh band blocker and produce extra in band noise. Both these signals can maketheir way to the mixer inputs via substrate coupling as well as coupling through theinterconnect parasitics. The following section studies the noise coupling accordingto the above model, through the substrate and interconnects, and modifies the designto increase the C/N above the spec limit, without impacting other specs.

After being fed by the process information and after tuning the runsets not todouble count the substrate network found in the device models. The substrate design

Fig. 6.4 Substrate noisecoupling model


flow extracts the substrate model as an R-C mesh extracted at a specific frequency ofinterest. The flow then based on the above information attach the substrate R-C meshto the design netlist (with routing interconnect parasitics included) where the sub-strate access ports are defined, and where the devices are connected to the substrateas described in chapter two. Perturbing and sensitive nodes are defined. A smallsignal analysis is performed on the system netlist to view noise contours and noisedistribution levels at various locations on the chip due to a noise source. Design isaltered to add substrate noise isolation structures and there effect is simulated.

The perturbing nodes are set to be the local oscillator ground (3.8 GHz) thisis at the output of the VCO buffer, and LNA ground (3.8 GHz, 2nd harmonic ofthe blocker). Noise contours using small signal AC analysis is calculated based onthese two sources, one at a time and combined (superposition as it is a small signalanalysis). Package/bond wire parasitics are also accounted for.

Figure 6.5 shows the layout of the VCO, LO and the mixer of both versionsof the chip and the perturbation node for the sake of simulating the substrate noisecoupling of the 3.8 GHz signal of the VCO core to the mixer input. Figure 6.6 showsthe noise distribution assuming a unity noise source at the perturbation node (0 dBlevel at the ground connection of the VCO core). The color code that shows thenoise contour levels relative to the noise source is also shown. The coupled noiselevel at the mixer input is also shown at the victim node.

Fig. 6.5 Layout of the VCO, LO and mixer

Fig. 6.6 Substrate noise coupling distribution (case of vco perturbation)


Fig. 6.7 Substrate noise coupling distribution (case of blocker perturbation)

Figure 6.7 shows the noise contours for the case of a perturbation noise sourceat the input of the chain (LNA ground connection) to represent the 3.8 GHz signalof the blocker 2nd harmonic of the high band. The level of the coupled noise atthe mixer input is shown. Table 6.2 summarizes the data for the above cases, for allcases the interconnect parasitics are included in the simulation model along with thesubstrate model.

Version A shows better Substrate noise isolation than Version B by approxi-mately ∼2.6 dB from the 3.8 GHz of the VCO. Studying the two layouts, this isfound to be due to less substrate taps in the mixer connected to the mixer groundas shown in Fig. 6.8. The distance between VCO buffer and first div is larger inVersion A than Version B by ∼40 um. The distance between VCO output and themixer assembly is larger in Version A than Version B by ∼25 um.

The action taken to decrease Version B noise coupling with no changes to thedesign that can affect other specs is to isolate the VCO block further without chang-ing the grounding schemes, package, and pad frame. This is done by adding doubledeep trenches in and around the VCO block as shown in Fig. 6.9. Deep trenches areregions in the substrate with oxide trench that goes deep into the substrate. Doubledeep trenches are added around each divider, around each buffer and around theentire LO block. The noise distribution levels before and after this modification isshown in Fig. 6.10. The noise level around the dividers and at the boundary of theblock seams to be “cooler” in the plot on the right. Table 6.3 summaries the noiselevels at the victim points in Fig. 6.9; with and without adding the deep trenches.

The noise levels in the VCO block after adding the DT is much less than the orig-inal case without the deep trenches. The modified VCO with DT added is placed onthe top level and its noise coupling to the mixer input is re-simulated and comparedto versions A and B.

Table 6.2 Substrate noise coupling level at mixer input relative to the noise source

Version A Version B Version A Version B

VCO coreperturbation

VCO coreperturbation

Blk 2nd Harm.Perturbation

Blk 2nd Harm.perturbation

−68 dBc −65.4 dBc −32.6 dBc −32 dBc


Fig. 6.8 Layout comparison of both versions

Fig. 6.9 Adding deep trenches in and around the VCO

Fig. 6.10 Noise levels without deep trenches added (left), and with deep trenches added (right)


Table 6.3 Substrate noise coupling level at victim points with and without deep trenches

Probe points With DT (dBc) Without DT (dBc)

1 −54.6 −382 −53 −363 −52 −27.84 −48 −185 −39 −10

Figure 6.11 shows the modified VCO and mixer layout and the locations of theaggressor and the victim points, (points 1, 2, 3 are at the mixer input), togetherwith the substrate noise level contours. Table 6.4 summaries the noise level at thesevictim points for the three cases under study, version A, version B and the modifiedversion B. It is clear that adding the isolation structures in the modified versionB enhances the substrate noise isolation between the vco core and the mixer ifcompared to both version A and B. Note that this is done with no change to thedesign what so ever, so it is considered a low risk edit. Doing so reduced the extranoise that couples to the output of the mixer and increase C/N to pass the spec limit.Figure 6.12 shows a die photo of the VCO, mixer, LO and LNA assembly.

Fig. 6.11 Noise aggressor and victim points using the modified VCO (left), noise levels (right)

Table 6.4 Substrate noise coupling level at victim points for all three versions

Victim points Version A Version B Modified version B

1 −68 −65.4 −71.82 −68.1 −66.2 −70.63 −68.4 −66.3 −70.34 −41.9 −37.8 −54.85 −41.7 −37.7 −54.76 −41.6 −36.3 −53.67 −41.1 −27.8 −52.48 −41.1 −27.9 −52.39 −40.9 −18.8 −50.410 −40.9 −18.8 −50.311 −16 −10 −41.4


Fig. 6.12 A die photograph showing the VCO mixer section

6.3 Block Level Case Study

In the previous section, the substrate noise interaction between circuit blocks in asystem is studied. In this section the substrate noise within a block is studied. Thetest case at hand is a transmit buffer. A transmit buffer is a pre power amplifiervoltage buffer for the high band cellular application 1.9 GHz. The buffer is designedto isolate the output of the transmit chain VCO from the input of the PA. This isdone to prevent VCO pulling by the PA by introducing a high reverse isolationblock that will separate the VCO and the PA. As this buffer is in the phase path ofthe phase modulation in the transmit path, its amplitude response is not importantand it is designed to operate in saturation “above the P1dB” at the power levels thatare being supplied from the transmit chain for better power efficiency. As this bufferis used in the transmit path and this path does not have sharp filtering, the phasenoise contribution of this buffer must be kept to an absolute minimum not to affectthe phase noise of the transmit VCO, and its reverse isolation must be kept at theabsolute maximum to prevent transmit VCO pulling. The buffer is put on a separatepower domain than the TX VCO. The buffer is designed for a typical saturatedoutput power of +6 dBm the high band, while the input power is specified between0dBm to +7 dBm. One of the most important specs is the reverse isolation, S12, forthis reason, cascode transmit buffer was chosen for the high band due to its highreverse isolation.

6.3.1 Design Details

As shown in Fig. 6.13, a cascode high band buffer is designed to have a high reverseisolation. The phase noise spec for the high band (is −140 dBc/Hz at 20 MHz offset).The buffer is resistively loaded on the collector. The input and output are capaci-tively coupled on the PCB. The bias circuit is a current mirror with a beta enhancerand an RC filter to stabilize the bias point. The reference current is generated by a

6.3 Block Level Case Study 97

Fig. 6.13 Transmit buffer schematic without substrate network

resistor to a regulated power supply of 2.75 V. A nominal dc current of 11 mA biasesthe cascode topology. An RC feedback from the collector of the CE transistor to itsbase is designed to establish negative feedback for stabilization and for input andoutput matching. The whole package model is used during the design to utilize thepackage parasitic in the input and output matching. The design is simulated withand without the substrate model. The phase noise and reverse isolation simulationdata in both cases are compared to silicon data.

As shown in Fig. 6.14, the collectors of both transistors Q1 and Q2 have capaci-tance to substrate C3 and C1 respectively. The base of Q2 is connected to a bond padthat has a bond pad capacitance to the substrate C2, the resistors R1 to R5 representa simplified substrate resistive network. If the substrate model is not included in thecircuit simulator, then the collector-to-substrate capacitors will be connected to theground. With the substrate model included, a feedback path between the collectorof Q1 “output of the buffer” and the base of Q2 “input of the buffer” is established.This feedback will decrease the reverse isolation “S12” as the output signal canbe coupled back to the input through this feedback path, especially at high outputpower level. The feedback loop will also impact the power gain and power outputlevel. Figure 6.15 shows the power output and power gain as a function of the inputpower, simulation data with and without the substrate model is plotted together withthe silicon data. It is obvious that adding the substrate model to the simulation is abetter prediction of the silicon behavior.

Figure 6.16 shows the S12 simulation and measurement data, the simulationresults without the substrate model gives a more optimistic isolation value. It isalso shown that the substrate model decreases the isolation and matches the siliconbehavior within 2 dB. Appendix B explains the measurement details.

Next the phase noise of the transmit buffer is analyzed. The phase noise of thebuffer is simulated with and without the substrate model. The thermal noise [57] of


Fig. 6.14 Transmit buffer schematic with substrate network

Fig. 6.15 Pout and Pgain vs. Pin with and without substrate model vs. silicon data at 1.9 GHz

6.3 Block Level Case Study 99

Fig. 6.16 S12 measured vs.simulation with and withoutsubstrate model at 1.9 GHz

the substrate resistive network acts as a white noise source and adds to the bufferphase noise. Figure 6.17 shows the initial layout of the buffer Without any modifica-tion to the layout, the phase noise simulation results with the substrate model addedshows a significant degradation in the phase noise that was not meeting the phasenoise spec (−140 dBc/Hz at 20 MHz offset). Figure 6.19 shows the phase noise sim-ulation data with and without the substrate model. Since the result is not meetingthe spec, the substrate behavior is modified by editing the layout to increase thevalue of resistors R1 to R5. Figure 6.18 shows the addition of deep trenches underand around the transistors. This has the effect of increasing the distance between thedevices and the substrate bulk; hence it increases the effective substrate resistance.In addition a guard ring is added around each transistor that will sink the substratenoise current and reduce the bulk current which in effect increases the value of theresistors bulk. Figure 6.19 compares the phase noise simulation data, with substratemodel of the unmodified layout, without the substrate model, with the substratemodel of the modified layout and finally the measured phase noise of the modifiedlayout.

Fig. 6.17 Transmit buffer layout


Fig. 6.18 Cascode stage inthe transmit buffer layout

It is clear from Fig. 6.19 (right) that the simulation results of the buffer phasenoise, without the substrate model meets the −140 dBc/Hz at 20 MHz offset, whileincluding the substrate network of the unmodified layout, raises the thermal noisefloor due to the thermal noise associated with the substrate resistive network andshifts the phase noise at 20 MHz offset marginally above the specs. This indicatesthe importance of including the substrate network during circuit simulation, with-out such effect, tapping out the buffer as is would render a part that is marginallyfunctional and hence its yield will be badly impacted. The layout is modified asmentioned above to increase the substrate resistance and hence decrease the sub-strate thermal current noise associated with the substrate resistive network. Thephase noise simulation result is shown in Fig. 6.19 (left), together with the mea-surement data of the phase noise of the modified block. The phase noise meets the

Fig. 6.19 Transmit buffer PN unmodified layout (right) modified layout and measurement (left)

6.4 Device Level Case Study 101

−140 dBc/Hz spec at 20 MHz frequency offset. An overall good match is achievedbetween simulation and measurement. The thermal noise floor is accurately pre-dicted by the simulator as shown by the good match of the phase noise measurementand simulation at high frequency offset, while the flicker noise contribution of thephase noise is off from the measurement data as shown at low frequency offset(usually the transistors flicker noise model is on the optimistic side).

6.4 Device Level Case Study

As shown in the previous chapter, the performance of on chip inductors at RF fre-quencies depends mainly on the substrate resistivity. As the substrate resistivity getslower, the eddy currents that can circulate in the substrate at these frequencies getslarger and causes energy losses in the substrate. Such energy losses will lower theinductor quality factor, which impacts lots of noise implications in RF systems.Guard rings are placed around on chip inductors to isolate the substrate noise cur-rent generated by the inductor in the substrate from other noise sensitive parts in thecircuits. A very common example is a tuned low noise amplifier that uses induc-tors as source (emitter) degeneration. In this case study the impact of the substrateisolation structure “guard rings” placed around the inductor is studied. Guard ringsplaced around the inductors can either improve or degrade the inductance and thequality factor depending on how these rings are designed.

An inductor is used as a demonstration vehicle; a commercial electromagnetic 3Dfield solver that is calibrated to silicon [50] as shown in the previous chapter is usedto extract the scattering parameters. The scattering parameters are then convertedto Z parameters. The Z parameters are used to calculate the inductance and thequality factor of the inductor as function of frequency. Four cases are studied andcompared in this case study. First, an inductor with no guard ring around it. Second,the inductor with a closed loop guard ring around it (30 um away from the inductorbody). Third, the inductor with a broken “open” guard ring around it (30 um awayfrom the inductor body). Fourth, the inductor with a closed guard ring very closeto the inductor body (10 um away from the inductor body). For the above cases theinductance and the quality factor are compared and recommendations are concludedregarding the guard ring design and its distance from the inductor. The parametersof the designed inductor together with the relevant process technology parametersare listed in Table 6.5. The inductor is a differential inductor with a center tap. Thecross unders and center tap are using lower metal level.

Table 6.5 Inductorparameters

Square inductor 150 um per sideNumber of turns = 3Width of coil = 18.5 umSpacing between the turns = 2.4 umInductor metal has a sheet rho = 10 m�/�,Distance to substrate is 7 um,Substrate resistivity is 10 �-cm


Fig. 6.20 Inductor test cases

Figure 6.20 shows the layout of the inductor with the above mentioned fourscenarios. While Figs. 6.21 and 6.22 show the simulation results of L and Q re-spectively. It can be seen from Fig. 6.21 that the most degradation in the inductanceis caused for closed guard rings, especially when the guard ring is closer to theinductor body. Substrate guard closed rings will act as a closed loop that have a finiteinductance and will have a negative “Lenz’s law” mutual coupling with the differen-tial inductor that gets bigger as the distance between the ring and the inductor getscloser. Such negative mutual coupling will decrease the effective inductance of thedesigned inductor as compared to the inductance without the guard ring altogether;as shown by the two bottom plots in Fig. 6.21. It is also clear that such degradationis not present for the case of a broken guard ring, where the guard ring loop isnot complete and the mutual inductance is not any more present. As the frequencyincreases towards the self resonance frequency the inductor capacitance to the guardring raises the total capacitance to the substrate by adding a parallel capacitance to

Fig. 6.21 Inductance vs. freqfor the four test cases

6.5 Conclusion 103

Fig. 6.22 Quality factor vs. freq for the four test cases

the inductor-substrate cap. This parallel cap is the inductor to guard ring cap. Thisdecreases the self resonance frequency. This is shown by the case of the brokenguard ring inductance increasing faster than the no guard ring at high frequencies.This is a minor impact and can be neglected if compared to the benefit of the guardring in sinking the substrate noise current around the inductor.

Examining the quality factor plot in Fig. 6.22, shows that closed guards ringwill lower the inductor quality factor due to the lower inductance. As the ring getscloser to the inductor; the quality factor is reduced more. The broken guard ringdoes not cause the quality factor to degrade, and hence the recommendation is toplace a broken guard ring around the inductor, or if this is not allowed by the routingconstraints it is highly recommended to place the guard ring at a large distance awayfrom the inductor body.

6.5 Conclusion

In this chapter three case studies are presented to explore the substrate noise cou-pling on the system level where the different blocks are interacting, within a blockwhere the noise coupling is generated and coupled within a block and finally onthe device level where the substrate isolation structure may affect the device perfor-mance. In all three cases, the design flow that is developed in this book is utilizedto debug and pin point the problem. This is an important step before applying thelearning of the substrate isolation guide that is developed to minimize or eliminatethe coupling the hence solve the problem at hand. It was shown that in some casesthe substrate noise coupling may cause the yield to degrade or even the design to failthe specifications. Uncovering and fixing such issues before tape out is an invaluablesaving to time to market, resources and gross margins.

Chapter 7Conclusion and Future Work

The challenge of overcoming the substrate noise coupling in deep submicron tech-nologies is becoming an increasing problem that faces designers and system archi-tects. In this book a substrate aware design flow is designed and calibrated and usedin the design phase as part of the design and validation methodology. The designflow is used to develop a design guide to minimize the substrate noise couplingand assist the floor planning, power and ground routing. The design of the differentisolation structures is studied in details, their geometries, topologies and bias arepresented. Package parasitics and the frequency of operation were also accountedfor in the set of parameters that impact the signal isolation level. Industrial case stud-ies are presented where the substrate noise coupling manifests itself as a problemthat causes a device, a block or a system to malfunction. The cases are studied usingthe developed design flow and its simulation infrastructure. In every step along theway simulation is validated by silicon measurement and solid recommendations andremedies are provided. An inductor design flow is developed and used to design highquality factor inductors, while taking into consideration design for manufacturingeffects that are not any more second order effects that can be neglected. The sub-strate parameters and parasitics that impact the inductor performance are studied andrecommendation for placing the substrate isolation structures around the inductorsis presented as a conclusion.

The CAD tools found in the industry that are dedicated for such analysis areextremely few, literally there is only one tool [58] that is commercially availableand by all means is not something that you can plug and play in the design envi-ronment, lots of calibration work needs to be done before the results out of this toolcan be trusted. More research is needed to come up with other algorithms that canevolve to commercial tools that can be used as part of the design flow and validationmethodologies. Tools that take into consideration the complexity and number oftransistors in today’s “SOC”.

The magnitude of substrate coupling depends strongly on the type of the pack-age used in the IC. This dependence can be caused by the value of the bond-wireinductances or the availability of good backplane contacts in a package which willinfluence the degree of coupling. A comparison of substrate noise coupling in newpackaging technologies such as multi chip modules and flip chip packages and highend sockets need to be performed.


106 7 Conclusion and Future Work

A more productive approach to handle the substrate noise issue is to model thenoise created by the aggressor circuitry that is injected in the substrate and includeit in the analog circuit simulators similar to device thermal and flicker noise thatare now a main part of the device models needed for RF and high speed designs.In a large design, the digital noise sources cannot be explicitly identified. Noise isgenerated across the chip by the large number of gates transitioning. If the chip isfabricated on a lightly doped bulk substrate, the locations of the noise sources areneeded. This is a more difficult problem, and an estimation of the switching capaci-tance to the substrate would be necessary for each area of the chip. An experimentalchip may be necessary to prove the validity of any digital noise source models.

Appendix AScattering Parameters

A.1 General Definition

At low frequencies two-port systems are described in impedance or admittance rep-resentation. The impedance and admittance parameters relate port voltages to portcurrents (Fig. A.1).

The description of the above system in impedance parameters is:

V1 = Z11I1 + Z12I2

V2 = Z21I1 + Z22I2 (A.1)

To experimentally determine the various parameters it is best to successivelyopen-circuit the ports. Then several terms become zero. Similarly the determinationof admittance parameters is easiest with short circuit conditions. At high frequen-cies it is difficult to provide adequate shorts and opens. Thus different two-portparameters are necessary, the scattering parameters, S-parameters [28]. The portvariables for S-parameter representation are defined in terms of incident (E1i, E2i)and reflected = scattered (E1r, E2r) voltage waves as shown in Fig. A.2

a1 = E1i√Zo

a2 = E2i√Zo

b1 = E1r√Zo

b2 = E2r√Zo

(A.2)

Thus a1, b1, a2, b2 are normalized voltage waves. The normalization is chosento make the square of the magnitude of a variable equal to the power of the corre-sponding wave.

The complex S-parameters describe the relationship between the normalizedvoltage waves by

b1 = S11a1 + S12a2

b2 = S21b1 + S22a2 (A.3)

107

108 A Scattering Parameters

Fig. A.1 Low-frequencydescription of two-port

Fig. A.2 High-frequencydescription of two-port. Z0 isthe characteristic impedanceof the lines

Determination of the parameters is based on the fact that terminating a line in itscharacteristic impedance (here Z0) gives rise to no reflections. For example drivingport 1 with port 2 terminated in Z0 yields a2 = 0 and

S11 = b1

a1= E1r

E1i

S21 = b2

a1= E2r

E1i(A.4)

Similarly S21 and S22 can be obtained, when driving port 2 and terminating port 1.S11 is the input, S22 the output reflection coefficient. S21 is some kind of gain andS12 is the reverse transmission. The transmission coefficients S12 and S21 are usuallydepicted in polar diagrams. For the reflection parameters S11 and S22 a new type ofdiagram, the Smith-plot has been introduced [28].

A.2 Transformation to Y- and Z-Parameters

Measured S-parameters can be transformed to Y-(admittance)-parameters andZ-(impedance) parameters. This is important especially for de-embedding measure-ment results.

Y11 = (1 − S11)(1 + S22) + S12S21

(1 + S11)(1 + S22) − S12S21Y12 = −2S12

(1 + S11)(1 + S22) − S12 S21

Y21 = −2S21

(1 + S11)(1 + S22) − S12S21Y22 = (1 + S11)(1 − S22) + S12 S21

(1 + S11)(1 + S22) − S12 S21(A.5)

Z11 = (1 + S11)(1 − S22) + S12S21

(1 − S11)(1 − S22) − S12S21Z12 = 2S12

(1 − S11)(1 − S22) − S12S21

Z21 = 2S21

(1 − S11)(1 − S22) − S12S21Z22 = (1 − S11)(1 + S22) + S12S21

(1 − S11)(1 − S22) − S12S21(A.6)

Appendix BMeasurements Setup

B.1 S-Parameters Measurements for Substrate IsolationStructures and on Chip Inductors

The measurement has been performed in setup system with two single ended portsE8364B PNA series network analyzer in the frequency range of 0.1–40 GHz, with0 dbm port power. Cascade ground-signal-ground (GSG) probes with 100 �m pitchhave been used for on wafer probing. The setup system is shown in Fig. B.1. Themeasurement steps performed to measure the isolation level S12 of the differentDUT structures are as follows:

1) Calibration: use standard calibration kit to calibrate the setup up to the probetips [59]

2) Measure 2 port single ended S-parameters of DUT3) Measure 2 port single ended S-parameters for short and open calibration struc-

tures4) Apply De-embedding technique studied in Section 3.8

For the case of on chip inductors the following calculations are performed tocome up with the inductor differential L and differential Q. The layout of the in-ductor to be measured is shown in Fig. B.2. Layout of the measured differentialinductors with all de embedding structures is shown if Fig. B.3.

1) After performing the de-embedding calculations as shown in Section 3.8, theZDUT calculated in step 4 represents the 2 port single ended impedanceparameters

ZDUT = Z11 Z12

Z21 Z22(B.1)

2) Differential impedance parameters Zdiff is calculated as follows

Zdiff = Z11 + Z22 − 2Z12 (B.2)

109

110 B Measurements Setup

Fig. B.1 VNA setup tomeasure S-parameters

Fig. B.2 Layout of the measured differential inductors

B.2 Transmit Buffer Pout and Pgain Measurement 111

Fig. B.3 Layout of the measured differential inductors with all de embedding structures

3) Differential Q and differential L are calculated as follows

Q = imag(Zdiff)/real(Zdiff) (B.3)

L = imag(Zdiff)/2∗·∗freq (B.4)

B.2 Transmit Buffer Pout and Pgain Measurement

The measurement setup of the output power vs. input power as well as the powergain of the transmit buffer is shown in Fig. B.4. the measurement steps are asfollows:

1) Cable power losses are calculated before connecting the DUT2) Signal Generated power is varied and recorded

112 B Measurements Setup

calculated lossof cable C1 is

1.13dBm

Calculated loss ofthe cable C2 is

1.13dBm

Sig Gen Pwr Reading dBm

CalculatedDut P indBm

Spec An PWRreading dBm

Calculated Dut Pout dBm

PartGaindBm

DUT ImA

Sig Gen DUT Spec AN

Pwr Sply

C1C2

Test Configuration

Fig. B.4 Transmit buffer measurement setup and calibration steps

3) At each step spec. analyzer reading is recorded4) Cable losses are de-embedded and DUT Pin, Pout and Pgain is recorded.

The S-parameters of the transmit buffer is measured using the 2 port VNA de-scribed above.

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Index

AActive guard rings, 60

BBack Plane, 45–47Bumps, 4, 67, 79–80

CCalibration, 25, 27, 105, 109, 112

DDe-embedding, 6, 27, 29, 38–39, 74,

108–109Deep n-well, 8, 10, 27, 35–36, 45Deep trench, 8, 10, 37, 38, 45, 93–95, 99Design flow, 4–6, 18, 25–41, 63–85, 88,

103, 105Design guide, 4–5, 25, 41, 43–60,

88, 105Design space, 65–69, 74, 85Devices

directly connected to substrate, 10–11indirectly connected to substrate, 11

DFM effects, 4, 6, 77–83Dual guard rings, 55, 56, 59, 60

FField solver, 5, 7, 69, 72, 74–75, 85, 101Floor planning, 25, 54, 56–59, 61, 105

GGSM, viiGuard Ring

grounding scheme, 50isolation vs. d, 50–53isolation vs. D, 49–50isolation vs. w, 53–54

n-guard ring, 32–33p-guard ring, 30–31

IInductor model, 71–74Isolation

baseline, 28–29, 32, 44–46, 50, 53, 59–60in low resistivity substrate, 43–44vs. frequency, 45–47

MMetal fill, 63, 81–82

NNoise

coupling mechanism, 12

PProcess

cross sections, 8–10regions, 7–8

Process variation, 81, 82

SSpiral inductor, 5–6, 63, 64, 65, 72Substrate

contacts, 12, 48doping profile, 18–21, 25, 27model extraction kernel, 20–23, 25

Substrate parasitics, 7, 71–75, 85

TTemperature variation, 4, 63, 77, 80–85Transmit buffer, 96–100, 111–112

VVCO, 4, 63, 64, 88, 91–96

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SUBSTRATE NOISE COUPLING IN RFIC - CAS€¦ · SUBSTRATE NOISE COUPLING IN RFICs Helmy, Ahmed,...

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