Submicron Devices Final Examination
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Transcript of Submicron Devices Final Examination
Submicron DevicesFinal Examination
2004.01.12
Problem 1: Charge Sharing
Page 162, exercise 3.6.
xj+ΔL
Wdm
xj+Wdm
12
1
2)(
)()(22
222
j
dmj
dmjjj
dmjdmj
x
WxL
WxxLx
WxWLx
12
11
12
)2(
2
j
dmj
x
W
L
x
L
L
L
LLL
L
LL
(a)
D
D
ox
sBfbt
ox
sBfbt
Q
Q
C
QVV
C
QVV
ˆ2
2
L
x
x
W
C
qNaW
C
qNaW
L
LL
C
qNaW
WL
WLL
C
Q
Q
QVVV
j
j
dm
ox
dm
ox
dm
ox
dm
dm
dm
ox
s
D
Dttt
12
112
12)(
1ˆ
(b)
Problem 2: Scaling
(a) Please prove that the classical field scaling can maintain the constant power density (power/unit area).
(b) Why does the constant field scaling not work for the small device.
(c) If the E-field increases by a factor of α, how is the power density? Gate leakage is not considered.
(a) Constant-field Scaling
1
kkd
C
1
1:areaunit per Cpacitance
kV
1
k
1dimemsions
1)/1)(( :density chargelayer Inversion kkCVQi
1)1)(1( :locity Carrier ve v
kkvWQI idrift
1)1)(1(
1 :current Drift
2
111 :n dissipasioPower
kkkIVP
1/1
/1 :density Power
2
2
k
k
A
P
(b) Why does the constant electrical field scaling not work for the small device?
Main reason:
In subthreshold region,
)1()1( //)(2
kTqVmkTVVqoxeffds
dstg eeq
kTm
L
WCI
)1()1()0( //)(
2
kTqVmkTVqoxeffgdsoff
dst eeq
kTm
L
WCVII
Ioff is defined as Vg=0,
Thus scaling down the threshold voltage Vt will result in increasing ofoff-current. Since we can not tolerate too large off-current, the scalingof Vt is limited, although the lower Vt can provide faster switching speed.
(c) Generalized Scaling
kV
k
1dimemsions
kkd
C
1
1:areaunit per Cpacitance
)/)(( :density chargelayer Inversion kkCVQi
Velocity saturation Long channel
Carrier velocity
Drift current
Power dissipation
Power density
1)1)(1( v
kkvWQI idrift
)1)((
1
2
2
kkkIVP
22
22
/1
/
k
k
A
P
))(1(v
kkvWQI idrift
2
))((1
2
32
kkkIVP
32
23
/1
/
k
k
A
P
Problem 3: SOC for memory and logic
For the same technology node. Make comparisons of Vt and Vdd for DRAM and Logic. What happens if DRAM and logic are integrated on the same chip? What are the challenges and possible solutions?
In DRAM technology, the off-current requirement is much more stringent forthe access transistor in the cell [Ioff(DRAM) << Ioff(Logic)], thus
)()( LogicVDRAMV tt
And for the purpose to keep the overdrive voltage,
)()( LogicVDRAMV dddd
If DRAM and logic are integrated on the same chip:Considering two cases,
1. Vdd=Vdd(DRAM) It causes large electrical field in logic, and will result in problems of reliability.
2. Vdd=Vdd(Logic) It will result in too low overdrive voltage in DRAM, thus the switching speed of transistor in DRAM will be slow.
Possible solution: use the process that allowed to adjust Vt so that we can obtain proper overdrive voltage.
Problem 4
Prove that for a symmetric doping profile, the effect on Vt are similar to a Delta profile with location corresponding to the symmetrical point and the dose corresponding to the integrated profile dose. The spreading doping has negligible effect on Vt, if the depletion region is wide enough.
Consider a simple symmetrical doping profile first,
Wd
xsi
dxxNq
x )()( Nsslope 0 , )(
ssdsi
ssisi
xx-xWqNa
xqNs
xqNs
Naslope ,
dsdsisi
WxxWqNa
xqNa
ox
ssiBfbt C
VV
2
The electrical field distribution can be obtain by Poisson’s equation,
And Vt is determined by surface field when Ψs=2ΨB
DI
ssis
ox
ssfbg QC
QVV ,
The nonuniform step doping profile discussed above is equivalent to the delta-function profile with an equivalent dose of DI=(Ns-Na)xs centered atxc=xs/2 because both the area under ε(x) and εs are identical between the two cases. (εs is determined by the area under N(x) )The similar arguments can be applied to any other symmetric profiles withsymmetric axis xc. Because the integral of symmetric profile (even function)is an odd function, the increased and decreased area under ε(x) (compared with the equivalent delta-function doping profile electrical field distribution) will be the same.
equivalent
original
area increased = area decreased
For example, considering a triangle symmetrical doping profile:
equivalent
Triangle profile
area increased = area decreased
xc xs
N(x)
Wdm x
DI
ID
Problem 5
If the device temperature increases from the room temperature, how is the Vt, mobility, and ID?
(a) Threshold voltage Vt
ox
sBfbt C
QVV 2
Consider an nMOSFET with n+ polysilicon gate:
dT
dm
dT
dE
qdT
d
C
qN
dT
dE
qdT
dV
C
qN
q
EV
BgB
ox
Basigt
ox
BasiB
gt
122
1/1
2
1
)2(2
2
From semiconductor physics,
kTEgvci eNNn 2/ ,
i
aB n
N
q
kTln
dT
dE
qdT
NNd
NNq
kT
N
NN
q
k
dT
d gvc
vca
vcB
2
1ln
dT
dE
q
m
N
NN
q
km
dT
dV g
a
vct 1
2
3ln)12(
Substituting eq.(B) into eq.(A) we finally obtain,
…(A)
…(B)
equals -1mV/K typically
So tV T
(b) mobility
srphieff 1111
μi : Impurity scattering
μph : Phonon scattering
μsr : Surface roughness scattering
2
11
o
i
i Q
Q
1.21eff
sr
E
3/11eff
ph
E
2964 1025.61045.41062.7 TT
KT TT 120 1096.81022.21062.1 2853
K TTT 1201053.21071.1107.2 2965
2965
2864
1077.71078.5105.7
1036.31018.61086.2
TT
TT
Conclusion:T↑, impurity scattering↓, μi ↑ T↑, phonon scattering↑, μph ↓ T↑, interface roughness scattering↑, μsr ↓ (T>120K)(in general, interface roughness scattering is almost independent of T)
Total effect: T↑ μeff ↓
(c) ID
In saturation region,
)]([2
1)(
2
)( 2
TVVmL
WCTI
m
VV
L
WCI
tgoxeffD
tgoxeffD
D
Dt
I (T)
I )(V
eff
TT
dominates )( I , T large VWhen effDg T
dominates )( I , T small VWhen Dg TVt
Problem 6: Body effect
Please derive the dependence for(a) uniform channel(b) extremely retrograded channel
(a) Uniform channel
VBS
Consider the band diagram at the source terminal:
When there is a reverse bias between bodyand source (VBS), the MOS structure is under non-equilibrium condition. Fermi level of electron and hole should be considered respectively:Efn : electron quasi-Fermi levelEfp : hole quasi-Fermi level (almost unchanged)
As a result, surface inversion occurs when band bending : BSBs V 2
Thus the threshold voltage can be modified:
2 ox
sBfbt C
QVV
ox
SBBasiBfbt C
VqNVV
)2(22
Note that Vt is referred to the source, not body
(b) Extremely retrograded channel
ox
sdasfb
ox
ssfbg
sdassis
si
sdaWd
xsi
C
xWqNV
C
QVV
xWqNQ
xWqNdxxN
qx
)(
)(
)()()(
si
sas
a
sid
Wd
sdsi
a
sis
xqN
qNWxW
qNdxxxN
q
2
2 )(
2)(
2
0
22
Consider general retrograded channel first,from Poisson’s equation:
Substituting eq.(B) into eq.(A) and let to obtain Vt (referred to source)BSBs V 2
…(A)
…(B)
ox
sas
a
BSBsi
ox
aBfbt C
xqNx
qN
V
C
qNVV
2)2(2
2
For extremely retrograded case (xs Wdm), Na must be high enough that to keep Wdm unchanged. We can expand eq.(C) under this limit to obtain
…(C)
aBSBsis qNVx )2(22
)2)(1(2)2(2 BSBBfbBSBoxs
siBfbt VmVV
CxVV
(m is body-effect coefficient = 1+3tox / Wdm =1+3tox / xs for extremely retrograded case)
Channel doping
xxs Wdm
Na
Problem 7: Dopant fluctuation
Which location of the dopant fluctuation has more detrimental effect on Vt? Si/Oxide interface or depletion edge? Why?
We can treat fluctuation as a delta-function doping profile, and determineVt through the surface electrical field. (Vt is defined as Ψs=2ΨB )
Case1: fluctuation is near Si / oxide interface
N(x)
x
N(x)
x
Case2: fluctuation is near depletion edge
ε(x)fluctuation
fluctuation
Δεs
xWdm
ε(x)
Δεs
xWdm
area increased = area decreased
Total area = 2ΨB
area increased = area decreased
Total area = 2ΨB
From above figure we can find that case1 has more effect on surface field,thus has more effect on Vt consequently.
ox
ssiBfbt C
VV
2
Wdm
Wdm