Subject Code HDL 2003[1]

8/8/2019 Subject Code HDL 2003[1]

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Subject Code: ECL 48 IA marks: 25Hours per week: 03 Exam Hours:03Total Hrs: 42 Exam Marks:50Note:

1. Programming can be done using any VHDL compiler. Download the programs on a

FPGA/CPLD board and test performance using 16/32 channel pattern generator and logicanalyzer apart from verification by simulation. 2. Use the pattern generator to generate input signal and truth tables.PROGRAMMING:1. Write VHDL code to realize all the logic gates2. Write a VHDL program for the following combinational designs

a. 2 to 4 decoder b. 8 to 3 (encoder without priority & with priority)c. 8 to 1 multiplexer d. 4 bit binary to gray converter e. Multiplexer, demultiplexer, comparator

3. Write a VHDL code to describe the functions of a Full Adder Using three modeling styles.4. Write a model for 32 bit ALU using the schematic diagram shown below.(example only)ALU should use combinational logic to calculate an output based on the four bit op-code inputALU should pass the result to the out bus when enable line in high, and tri-state the out buswhen the enable line is low.ALU should decode the 4 bit op-code according to the given in example below

OPCODE ALU OPERATIONa) A + B

b)A - Bc) A Complementd) A * Be) A AND Bf) A OR Bg) A NAND Bh) A XOR B5. Develop the VHDL codes for the following flip-flops, SR, D, JK, T.6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and any

sequencecounters.

INTERFACING1.Write VHDL code to display messages on the given seven segment display and LCD and

accepting Hex key pad input data.2 .Write a VHDL code to accept 8 channel Analog signal, Temperature sensors and display the

data on LCD panel or Seven segment display.3. Write VHDL code to simulate elevator operations.4. Write VHDL code to control external lights using relays.5. Write VHDL codes to control speed, direction of DC and Stepper motor.6. Write VHDL Code to generate different waveforms (Sine square Triangle, Ramp etc) using DACchange the frequency and amplitude.


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ABSTRACT

The semiconductor industry has been experiencing an unprecedented growth fuelled bythe developments in the VLSI industry. The VLSI industry has already crossed the quarter-micron threshold and devices with 0.18 micron feature-size are already in market. Thus, it

becomes extremely difficult to design complex circuits with the help of conventional designingmethods. The computer aided design tools introduced serve the purpose.

INTRODUCTION

There are now two industry standard hardware description languages, VHDL andVerilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and megacells written in either VHDL or Verilog. As a result, it is important that designers know bothVHDL and Verilog and that EDA tools vendors provide tools that provide an environmentallowing both languages to be used in unison. For example, a designer might have a model of aPCI bus interface written in VHDL, but wants to use it in a design with macros written inVerilog.

VHDL is a hardware description language that offers a broad set of constructs for describing even the most complicated logic in a compact fashion. The VHDL language isdesigned to fill a number of requirements throughout the design process:

Allows the description of the structure of a system how it is decomposed intosubsystems, and how those subsystems are interconnected.

Allows the specification of the function of a system using familiar programminglanguage forms.

BACKGROUNDVHDL (Very high speed integrated circuit Hardware Description Language) became

IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 10761993". The Verilog hardware description language has been used far longer than VHDL and has

been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 inDecember 1995.

There are two aspects to modeling hardware that any hardware description language

facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior is not prejudiced by structural or design aspects of hardware intent and that hardware structure iscapable of being modeled irrespective of the design's behavior.


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PROCEDURE:

Software part:1. Click on the Project navigator icon on the desktop of your PC. Go to Create New

Project, give project Name.2. Set Spartan 2, xc2s100, tq144. -5 and ISE Simulator / Modelsim for FPGA Family.3. Go to Create new source in process View, Select VHDL MODULE and give name(it

should be other than the project name). i.e. Entity name and give the inputs, outputsand select the architecture name. Then click on next icon & Finish Icon.

4. Then Write the VHDL code and save the file.5. Then click on Check syntax in Synthesis-XST in Process view, and if there is any

error in the code debug it.6. To see output in Test Bench Waveform(ISE Simulator / Modelsim):

Go to Create new source, select TEST BENCH WAVEFORM and give adifferent file name and select COMBINATIONAL for combination circuits andSINGLE CLOCK for Sequential Circuits. Then set the corresponding inputs &outputs, then save and then click on simulate Behavioral model/ Modelsim simulator i.e. depending upon the module.

7. To see output in VHDL kit: Go to Create new source, select IMPLENTATION CONSTRAINTS FILE

and Open a new UCF(User Constraint File) file and assign the pins of the design withFPGA/CPLD I/O pins(for Clock input always P18) and save the file.

8. Implement the design in process view by double clicking on the Implement Designand View Pad Report to verify the pin numbers.

9. Click on Generate Programming File in Process View and then click on ConfigureDevice.

10. Now check the cable connections and select mode as SLAVE SERIAL MODE and

then verify the output at LEDS.11. To see output in Pattern Generator / Logic Analyser:

Repeat steps from 1 to 10 except step 6, then choose appropriate Baud Rate,and thenclick on save and see the output.

Hardware part:1. Connect the FPGA kit to the parallel port of the PC through the cable provided along

with the Kit. Connect the FRC cable provided with the kit to the Bit Pattern generator and logic analyzer.

2. For all the combinational experiments Use FRC1&FRC2 for sending bit patterns toFPGA (pattern generator) and use FRC3 &FRC4 for receiving the logic from FPGA(logic Analysis).

3. For all sequential circuits Use FRC 1 for sending bit patterns to FPGA (patterngenerator) and use last input pin as the clock for the design and connect it to the FPGAclock pin through the jumper provided on the Kit. Use FRC2 for receiving the logicfrom FPGA (logic Analysis).

4. For interfacing the cards connect the required part of the interfacing card to the FRCconnector Provided on the FPGA kit.


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PART-A


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1. Write VHDL code to realize all the logic gates.

Block Diagram :

Truth Table :

INPUTS

OUTPUTS

A B Op_not

(Consideringinput A)

Op_or Op_and Op_nor Op_nand Op_xor Op_xnor

0 0 1 0 0 1 1 0 1

0 1 1 1 0 0 1 1 0

1 0 0 1 0 0 1 1 0

1 1 0 1 1 0 0 0 1

LOGIC GATESB

A

Op_not

Op_or

Op_nor

Op_and

Op_nand

Op_xor

Op_xnor


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Program:

1) Using VHDL

Library IEEE;Use IEEE.STD_LOGIC_1164.ALL;Use IEEE.STD_LOGIC_ARITH.ALL;Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity gate isPort ( A : in std_logic ; -- First Input

B : in std_logic ; -- Second InputOp_not : out std_logic ;Op_or : out std_logic ;

Op_and : out std_logic ;Op_nor : out std_logic ;Op_nand : out std_logic ;Op_xor : out std_logic ;Op_xnor : out std_logic );

End gate ;

Architecture Behavioral of gate isBegin

Op_not


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2) Using Verilogmodule gates (a,b,op_not,op_or,op_nor,op_xor,op_xnor,op_and,op_nand);input a,b;output op_not,op_or,op_nor,op_xor,op_xnor,op_and,op_nand;assign op_not=~a;assign op_or= a| b;assign op_nor= ~(a|b);assign op_xor= a^ b;assign op_xnor= ~(a^ b);assign op_and= a &b;assign op_nand= ~(a&b);endmodule


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2. Write a VHDL program for 2 to 4 Decoder

Block Diagram :

Truth Table :

INPUTS OUTPUTSE D_IN(0) D_IN(1) D_OUT(3) D_OUT(2) D_OUT(1) D_OUT(0)0 0 0 0 0 0 1

0 0 1 0 0 1 00 1 0 0 1 0 00 1 1 1 0 0 0

a) Using Data Flow Model :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Decoder2_4 isport (Enable: in STD_LOGIC ;

D_IN: in STD_LOGIC_VECTOR (1 downto 0) ; -- Two Bit Input for theDecoder

D_OUT: out STD_LOGIC_VECTOR (3 downto 0)) ; -- Four Bit Output for

D_OUT (3:0)

DECODRE 2_4

Enable

D_IN (1:0)


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the Decoder End Decoder2_4 ;

Architecture Data_flow of Decoder2_4 isSignal s1, s2: std_logic ;

Begins1


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End if;End process ;

End Behavioral ;

Using Verilog :

module decoder(data, code);output[3:0]data;input[1:0]code;reg [3:0]data;always @(code)case (code)0:data=4'b 0001;1:data=4'b 0010;2:data=4'b 0100;3:data=4'b 1000;default: data=4'bx;endcaseendmodule


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3. Write a VHDL program for 8 to 3 Encoder withoutPriority.

Block Diagram :

a) Using Behavioral Method :b)

TRUTH TABLE

INPUTS OUTPUTSD_IN(7

)D_IN(6) D_IN(5) D_IN(4) D_IN(3) D_IN(2) D_IN(1) D_IN(0) D_OUT(2) D_OUT(1) D_OUT(0)

1 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 1 0 1

0 0 0 1 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 0 1 0 0 0

D_OUT (2:0)ENCODER 8_4

Enable

D_IN (7:0)


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Entity Encoder8_3 isPort ( ENABLE: in STD_LOGIC; --Enable Pin to Enable the Encoder

D_IN : in STD_LOGIC_VECTOR(7 downto 0); --Eight Input Lines of theEncoder

D_OUT: out STD_LOGIC_VECTOR(2 downto 0) ); --Three Output Linesof Encoder

End Encoder8_3;

Architecture Behavioral of encoder8_3 isBegin

Process (ENABLE,D_IN)Begin

if ( ENABLE = '1') thenD_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT NULL;

end case;end if;

end process;End Behavioral;


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Using verilog

module encoder(code, data);output [2:0] code;

input [7:0]data;reg [2:0]code;always @ (data)case(data)8'b 00000001: code=0;8'b 00000010: code=1;8'b 00000100: code=2;8'b 00001000: code=3;8'b 00010000: code=4;8'b 00100000: code=5;8'b 01000000: code=6;

8'b 10000000: code=7;Default : code=3'bx;endcase

endmodule


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4. Write a VHDL program for 8 to 3 Encoder withPriority.

a) Using Behavioral Method:

Entity pri_Encoder isPort ( ENABLE: in STD_LOGIC ; --Enable Pin to Enable the Encoder D_IN: in STD_LOGIC_VECTOR(7 downto 0); --Eight Input Lines of the Encoder D_OUT: out STD_LOGIC_VECTOR(2 downto 0) ); --Three Output Lines of Encoder End pri_Encoder ;

Architecture Behavioral of pri_Encoder isBegin

D_OUT


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Using veilog

module priority (code, valid_data, data);output[2:0] code;

output valid_data;input[7:0]data;reg[2:0]code;assign valid_data= |data; // reduction or operatoralways @ (data)casex(data)

8'b 1xxxxxxx: code=7;8'b 01xxxxxx: code=6;8'b 001xxxxx: code=5;8'b 0001xxxx: code=4;

8'b 00001xxx: code=3;8'b 000001xx: code=2;8'b 0000001x: code=1;8'b 00000001: code=0;default: code=3'bx;endcaseendmodule


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5. Write a VHDL program for 8:1 MUX

BLOCK DIAGRAM

Select Lines INPUTS OUTPUTS0 S1 S2 A B C D E F G H Mux OUT0 0 0 0 x x x x x x x 00 0 0 1 x x x x x x x 10 0 1 x 0 x x x x x x 00 0 1 x 1 x x x x x x 10 1 0 x x 0 x x x x x 00 1 0 x x 1 x x x x x 10 1 1 x x x 0 x x x x 00 1 1 x x x 1 x x x x 11 0 0 x x x x 0 x x x 01 0 0 x x x x 1 x x x 1

1 0 1 x x x x x 0 x x 01 0 1 x x x x x 1 x x 11 1 0 x x x x x x 0 x 01 1 0 x x x x x x 1 x 11 1 1 x x x x x x x 0 01 1 1 x x x x x x x 1 1

8:1 MUX

AB

C

D

E

F

G

H

MUX_OUT

SEL


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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Mux8_1 isPort ( SEL: in STD_LOGIC_VECTOR(2 downto 0); -- Select Lines

A,B,C,D,E,F,G,H : in STD_LOGIC; -- Inputs of the Mux.MUX_OUT: out STD_LOGIC ); -- OutPut of the Mux.

End Mux8_1;

Architecture Behavioral of Mux8_1 isBegin

Process (SEL,A,B,C,D,E,F,G,H)Begincase SEL is

when "000" => MUX_OUT MUX_OUT MUX_OUT MUX_OUT MUX_OUT MUX_OUT MUX_OUT MUX_OUT null;end case;end process;

end Behavioral;

Using Verilog


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Module mux8x1(I0,I1,I2, I3,I4,I5,I6,I7,y,sel);input I0,I1,I2, I3,I4,I5,I6,I7;input [2:0]sel;output y;

reg y;always @ (I0,I1,I2, I3,I4,I5,I6,I7,sel) begin

case (sel)3'b000 : y=I0;3'b001 : y=I1;3'b010 : y=I2;3'b011 : y=I3;3'b100 : y=I4;3'b101 : y=I5;3'b110 : y=I6;

3'b111 : y=I7;endcaseendendmodule

6. Write a VHDL program for 4 bit binary to gray


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converter.

Boolean Equation:G3=B3;G 2= B 3 xor B 2;G1= B2 xor B 1;G0= B1 xor B0;

BLOCK DIAGRAM

Truth Table:


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Binary Input Gray outputB3 B2 B1 B0 G3 G2 G1 G00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 00 1 0 0 0 1 1 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0

a) Using Data Flow Method:


Entity Binary_Gray isport( B_IN: in std_logic_vector(3 downto 0) ; --Binary Input

G_OUT: out std_logic_vector(3 downto 0 )); --Gray Output

End binary_gray ;

Architecture behavioral of Binary_gray isBegin

G_OUT(3)


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End behavioral ;

Using Verilog

7. Write a VHDL program for 1:4 DEMUX.


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BLOCK DIAGRAM

Select lines INPUT OUTPUTSSel(1) Sel(0) D_in Y(3) Y(2) Y(1) Y(0)

0 0 1 x x x 10 1 0 x x 0 x1 0 1 x 1 x x1 1 0 0 x x x



entity Demux1_4 isport ( d_in: in STD_LOGIC; --Input For Demultiplexer

sel: in STD_LOGIC_VECTOR (1 downto 0); --Select Lineof Demux

d_out: out STD_LOGIC_VECTOR (3 downto 0)); --OutputLines of Demux

end Demux1_4;

architecture demux1_4_arch of Demux1_4 is begin

1:4DEMUX

D_inY

S

4

2


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process (d_in, sel) begin

d_out d_out(0) d_out(1) d_out(2) d_out(3)


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8.Write a VHDL program for N Bit Comparator.


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BLOCK DIAGRAM

TRUTH TABLE

INPUTS OUTPUTS

A B A=B AB0 0 1 0 00 1 0 1 01 0 0 0 11 1 1 0 0

PROGRAM


entity comparator is Generic (N: integer := N); --- Generalizing the Inputs Port ( A,B: in STD_LOGIC_VECTOR (N downto 0); -- Inputs for

ComparisonALB,AGB,AEB: out STD_LOGIC); -- Output Signals to show

Less than,Greater than and Equal.end comparator;

architecture behavioral of comparator is begin process (A,B)

beginif ( A < B ) then ALB


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else AGB


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9. Write a VHDL program for the implementation of Half Adder.


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BLOCK DIAGRAM

TRUTH TABLE

a) Using Data Flow Method:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Halfadder isPort ( A, B : in std_logic ; --2Bit Input

Sum, Carry : out std_logic); --sum& carryend Halfadder;

architecture dataflow of Halfadder i s begin

Sum


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end dataflow;

Using Verilog

10 Write a VHDL program for the implementation


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of Full Adder.

BLOCK DIAGRAM

Truth Table:-

a) Using Data Flow Method:library IEEE;use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder is Port ( Ain : in std_logic; --Input One

Bin : in std_logic; --Input TwoCin : in std_logic; --Carry Input

A BC i

n

SC ou

t

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

FULL ADDER

SUM

Cout

A

B

Cin


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Cout : out std_logic; --Carry OutputSum : out std_logic); --Sum Output

end FullAdder;

architecture dataflow of FullAdder is begin

Sum


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end process; end behavioral;

c)Using Component Instantiation Method(or)strcuctural method


entity FullAdder is Port ( Ain : in std_logic; --Input One

Bin : in std_logic; --Input TwoCin : in std_logic; --Carry InputCout : out std_logic; --Carry OutputSum : out std_logic); --Sum Output

end FullAdder;

architecture structural of FullAdder is Component Halfadder Port ( Ain : in std_logic;

Bin : in std_logic;Sum : out std_logic;

Carry : out std_logic); end Component;


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component or1 is port (p,q :in std_logic;

r : out std_logic); end component;

Signal temp1,temp2, temp3: std_logic; -- Signal Declaration begin

U1: Halfadder port map( Ain, Bin,temp1,temp2);U2: Halfadder port map( temp1,Cin,Sum,temp3);U3: or1 port map (temp2,temp3,Cout);

end structural;

entity halfadder is Port ( Ain,Bin : in STD_LOGIC;

sum, carry : out STD_LOGIC);end halfadder;

architecture Behavioral of halfadder is begin

Sum


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12. ALU

Block Diagram

Truth Table


entity ALU is

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0) ;y : out STD_LOGIC_VECTOR (7 downto 0);e: in std_logic;

opc : in STD_LOGIC_VECTOR (2 downto 0));end ALU;

architecture Behavioral of ALU is

begin process (opc,e)

begin if (e ='0') then

y y y


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when "010" => y y y y y y null; end case; end if; end process;end Behavioral;

Sequential circuits:

11. Write a VHDL program for SR F/F

Block diagram

a) Using Behavioral Method:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rsff isPort ( r,s,reset,clk : in std_logic;

q,qb : out std_logic);end rsff;

architecture Behavioral of rsff is

RESET

CLK SR

FLIP-FLOP

S

R

Q


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signal p:std_logic:='0';begin

process( clk,reset,s,r )begin

if( reset='1' )then p


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Block Diagram

Truth Table INPUT OUTPUTCLK RESET D Q

1 0 1 01 1 0 01 1 1 1



entity dff is Port ( d,rst,clk : in STD_LOGIC;

q : out STD_LOGIC);end dff;

architecture Behavioral of dff is begin process (rst,clk) begin if rst = '0' then

q


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q


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entity jk is Port ( s,r, j,k,clk : in STD_LOGIC;

q : inout STD_LOGIC;qn : out STD_LOGIC := '1');

end jk;

architecture Behavioral of jk is begin process (s,r,clk) begin if r = '0' then q


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1 0 0 01 1 0 01 1 1 Toggle



entity tff is Port ( rst,clk,t : in STD_LOGIC;

q : inout STD_LOGIC);end tff;

architecture Behavioral of tff is begin process (clk,rst) begin

if (rst = '0') thenq


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Using Verilog

VHDL code for 4-bit BINARY COUNTER with Asynchronous Reset


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entity asbin_counter isPort ( sclk,reset: in std_logic;

q : out std_logic_vector(3 downto 0));end asbin_counter;

architecture Behavioral of asbin _ counter is signal count :std_logic_vector(3 downto 0):="0000"; begin

process (clk,reset) begin if (reset='1') then count


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entity sbin_counter is Port ( clk,reset : in std_logic;

q : out std_logic_vector(3 downto 0));end sbin_counter;

architecture Behavioral of sbin_counter is signal count :std_logic_vector(3 downto 0):="0000"; begin

process (clk,reset) begin if (rising_edge(clk)) then if (reset='1') then count


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entity sbcdcounter is Port ( clk,reset : in std_logic;

q : out std_logic_vector(3 downto 0));end sbcdcounter;

architecture Behavioral of sbcdcounter is signal count :std_logic_vector(3 downto 0):="0000"; begin

process (clk,reset) begin if (rising_edge(clk)) then if (reset='1') then count


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entity asbcdcounter is Port ( sclk,reset : in std_logic;

q : out std_logic_vector(3 downto 0));end asbcdcounter;

architecture Behavioral of asbcdcounter issignal count :std_logic_vector(3 downto 0):="0000";

beginprocess (clk,reset)

begin if (reset='1') then count

Subject Code HDL 2003[1]

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