Sub-threshold Design of Ultra Low Power CMOS Circuits Students: Dmitry Vaysman Alexander Gertsman...

Sub-threshold Design of Sub-threshold Design of Ultra Low Power CMOS Ultra Low Power CMOS

CircuitsCircuits

Students:Dmitry VaysmanAlexander Gertsman

Supervisors:Prof. Natan Kopeika Prof. Orly Yadid-Pecht Alexander Belenky

Annual Projects Conference

July 2nd, 2008

2/7/2008 Alexander GertsmanDmitry Vaysman

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Motivation for Power Reduction Motivation for Power Reduction in CMOS circuitsin CMOS circuits

40048008

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8086

286 386 486

Pentium®

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10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

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W/c

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Hot Plate

Nuclear

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Rocket

Nozzle

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Source: IntelSource: Intel

Medical devices

Micro sensors

Portable electronics

Low/Medium PerformanceApplications


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Some Trends – Vdd, VSome Trends – Vdd, VTT, Energy/Operation, Energy/Operation

Source: www.intel.comSource: www.intel.com

Sources: Mary Jane Irwin course, ITRS roadmap for semiconductorsSources: Mary Jane Irwin course, ITRS roadmap for semiconductors


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Some Trends – Subthreshold LeakageSome Trends – Subthreshold Leakage

- Sub-threshold leakage power as a percentage of total power, and it is

already approaching the practical limit of 50%

- “When this leakage power is about 50% of total power, further supply

voltage scaling does not make sense” (Intel, 2006)

Sub-threshold leakage powerSub-threshold leakage power


Sub-threshold leakage power as a Sub-threshold leakage power as a percentage of total powerpercentage of total power



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P-substrate

n+n+Source Drain

Polysilicon Gate

Oxide

I5I1

I2

I3 I4

I6

The most significant component of the IThe most significant component of the IOFFOFF

is the Sub-Threshold current.is the Sub-Threshold current.

thDSth

DS

th

TGS

VVV

V

V

VV

SUB eeeII /0 1

VT=threshold voltageζ = DIBL coefficient η = sub-threshold slope factor

Vth = thermal voltage Instead of fight it we use Instead of fight it we use it!it!

Transistor LeakagesTransistor Leakages

I2 – Sub-threshold current.I1 – pn junction Reverse

I3 – Tunneling into gate oxideI4 – Hot carriers injection I5 – Gate Induced Drain Leakage (GIDL) I6 – Punchthrough


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Sub-threshold benefitsSub-threshold benefits

leakscswtotal PPPP

)( 2CLKDDLSW fVCP DDSCSC VIP DDleakleak VIP

- CL is the loading capacitance- fCLK is the clock frequency- α is the activity factor

•Reduce the switching component by 4 to 81 times!!! •Reduce the ISC leading to “double reduction”: lower VDD and lower ISC

•Reduce leakage power by 2.5 to 9 times.

- ISC Short circuit current

Reducing VDD to a sub-threshold levels will:

- Ileak Leakage current

In total it gives us a reduction of leakage power by 5 to 90 times!!!In total it gives us a reduction of leakage power by 5 to 90 times!!!

- Psw is the switching (dynamic) power consumption - Psc is the short-circuit consumption - Pleak is the leakage power consumption


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Does subthreshold operation Does subthreshold operation is the right way to go?is the right way to go?

VTC of CMOS 90nm InverterVTC of CMOS 90nm Inverter

Vdd [mV]Temp

VIL [mV]

VoH [mV]

VIH [mV]

VoL [mV]

NML [mV]

NMH[mV]

308.571

12598.1291.7159.32573.1132.4

25108.

429816019.289.2138

-40116.

2301.316215.8100.4139.3

Static Power consumption of Static Power consumption of CMOS 90nm InverterCMOS 90nm Inverter

Good noise margins


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InnovationInnovation

-Operation of the MOS transistor in the sub-threshold region is something that most designers try to eliminate.

-We want to employ the sub-threshold leakage and make our circuit work at this area.

-Develop methodologies for sub-threshold logic circuits design.

-Investigate the most appropriate logic style for operation in the sub-threshold regime.


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Simulation results -Ring oscillatorSimulation results -Ring oscillator

OUT

DUT

Ring oscillator setupRing oscillator setup

GateTransistor type

VDD200mV

VDD320mV

VDD 1V

Invertertyp4.4MHz58.7MHz7.7GHz

hvtNRNR7.7GHz

lvt4.4MHz58.7MHz7.7GHz

Oscillation frequencies Oscillation frequencies

Inverter based ring oscillatorInverter based ring oscillator

Total energy of ring oscillatorTotal energy of ring oscillator


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Simulation results –Sequential CircuitSimulation results –Sequential CircuitFour stages 90nm shift register implemented in three different topologies.Four stages 90nm shift register implemented in three different topologies.

MUX

0

1MUX

0

1

D

Q_bar

Q

CLK

MUX

0

1

MUX

0

1D

Q

Q_bar

CLK

MUX

0

1

MUX

0

1D Q_bar

Q

CLK

Delay

Basic FF circuits:

Test CircuitTest Circuit


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Simulation results –Sequential Circuit Simulation results –Sequential Circuit Cont’Cont’

It Works!!!It Works!!!Time domain simulation resultTime domain simulation result Average power consumption of SRAverage power consumption of SR

Time domain simulation represents 200mV operation voltage and 500KHz Clk.Power dissipation of SR is 55nW when operated with 200mV.


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Future StepsFuture Steps- Research different logic families.

- To build generic test circuit.

- Operate this test bench with different activity

factors.

- Evaluate minimum energy point.

- Develop methodology for minimum energy point

operation.

- Test chip fabrication and results verification.

- Fitting transistor models for sub-threshold

operation.

- Create basic logic cells library.


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Any questions?Any questions?

Sub-threshold Design of Ultra Low Power CMOS Circuits Students: Dmitry Vaysman Alexander Gertsman...

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