Sub- Nyquist Sampling Expander Module

Supervisors : Moshe Mishali, Ina Rivkin

Students : Amir Bishara, Morad Awad

AgendaPart A Reminder

Last timeCompleting Part A

NCOPart B

GoalsThe Development process

Migrating between FPGA cards Changes in architecture Simulations

ResultsProject outcome

Memory

CTF(Support recovery) DSP

(Baseband)

AnalogBack-end

(Realtime)Detector

Analog Hardware

Expand1:3

3 1 2

1

2

3

Frequency domain elaboration:

30Mhz

10Mhz

-30Mhz -10Mhz

10Mhz

10Mhz

10Mhz

-10Mhz

-10Mhz

-10Mhz

Reminder

Last TimeCompleted:

AlgorithmArchitectureDesignImplementation (VHDL)Testing

Expander Module

Single Channel Architecture

Modulation

Modulation

Sync

Filter

Filter

Filter

Init Cont.

Completing part AInaccurate results with real data, but good with

synthetic dataImprove testing environment to have automatic

tests for all modulesAll modules work as expected

System level problem

Use MATLAB to perform different parts of the algorithmProblem with the modulation

The modulation module doesn’t produce an accurate cos/sin signals

NCO : Entity

NCOUse Altera’s MegaFunction to produce the

cos/sin signalsThe modulation module uses this component

to produce the cos/sin signalNCO issues

Can choose between 4 architecturesTo get full accuracy the VHDL needs to be

manually modified

Part B : GoalsRunning the system successfully on the FPGASuccessful integration (logic level) with the

DSP and CTF blocks

Development ProcessIntegration with the architecture teamMigrating to the new board

More resourcesFasterMeant to be used in the future

Changes in architectureTo save resources

Changes in designTo meet timing constraints

Adapt the testing environment to the architecture team environment

Testing

Migrating to the new boardWhy?

More resourcesFasterMeant to be used in the future

Issues :The card wasn’t responsiveCreated new ProcWizard projectChanged architecture team software

Changes in the architectureWhy?

Saving resourcesSolving problems arising at hardware

debugging Changes:

NCO module is taken out from modulation module Made global to all channels

Add logic to control NCO phase

cos/sin generator

Set Phase to zero

Changes in designWhy?

To meet timing constraintsHow?

Break the combinational logic using pipelineConvert non-optimized generic code to specific

codeWhere?

Multiplication + addition block Generic code for addition

FIR filter , Polyphase Long Muxing paths

Before

areset

clock

clock_ena

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result[37..0]

areset

clock

clock_ena

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result[37..0]

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a1[17..0]

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a2[17..0]

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a3[17..0]

b3[17..0]

result[37..0]

DATAB

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D QPRE

ENA

CLR

0

0

node6

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node19node20

node21node22

node23node24

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node27node28

node29node30

node31node32

node33

node34

clk_procenable

pause (GND)

enable_pipe_in

enable_pipe_out

A_data_in[215..0]B_data_in[215..0]

data_out[17..0]

dsp_block_noreg:\dsp_blocks:1:dsp

node1

node4

rst


node3reg[3..1]

node2

node5


Adapting the testing environmentThe architecture team expects different

format for input filesOutputs different format for output files

VHDL code converts between the formatsSmall modifications from the files at part A

TestingTesting environment diagram

Results

Showing the resultsSystem

Expander -FPGA

DSP

CTF

אותות משוחזרים

תמך שהתגלה

Matlab Simulation

Preparing the input

FPGA Simulation Matlab Matlab

Interfaces AddedInterfaces Added

FPGA instead of MODELSIMFPGA instead of MODELSIM

ResultsSeveral synthetic inputs were testedThree different real input signals were tested

fm259_252_sin824_809fm259_252_am_872.697am_872.697_sin824

All tests were successful Integration team was able to:

Produce same results independently on FPGA using the new architecture

Run logic simulations of the Expander with DSP and CTF successfully

Demonstrationam_872.697_sin824

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FPGA :Reconstructed sequence #1

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fm259_252_sin824_809

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fm259_252_am_872.697

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Improvements and future developmentFor future expansion :

Create a new module that represents a single output channel Contains a modulation module and Polyphase module Gets modulation signal as input

Mid channel “modulation” signal is 1 Allows changing expansion factor (now is 1->3) easily

Add input signal to Expander system that allows changing modulation frequency at runtime

Make modulation phase shift register changeable at runtime

Resources sharing:Make module that holds filter coefficients

Each filter requests for coefficients Can reduce coefficients memory by a factor of 12

Project outcomeMATLAB simulations files for the algorithmVHDL code implementing the designVHDL + MATLAB code for testing

environmentTwo project booksUser Manual for changing configurations and

testing

Sub- Nyquist Sampling Expander Module

Documents

Transcript of Sub- Nyquist Sampling Expander Module