Styresystemer og Multiprogrammering

Block 3, 2005

Memory Management:

Main Memory

Robert Glück

2

Today’s Plan

• Binding programs to physical memory• Logical / physical addressing

• Allocation: 1 process = 1 block• Contiguous: blocks of variable size

• Allocation: 1 process = n blocks• Paging: blocks of fixed size• Segmentation: blocks of variable size• Segmentation with paging: combination

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Problem of Memory Management

Process 1Logical address space

MemoryPhysical address space

Process 3Logical address space

Process 2Logical address space

?

performance protection limited size fragmentation …

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17

17

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Logical / Physical Address

Logical address – generated by the CPUPhysical address – seen by the Memory Unit

• Basis for the memory management in most of today’s OS; mapping requires HW support.

Logical address space Physical address space

mapping17

14385

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Hardware Support: Dynamic Relocation

register loaded by context switch,each process has a different value

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System Architecture

CPU

memoryI/O bridge

I/O controllerdisk

I/O controllernetwork card

I/O controllerscreen

system bus

I/O bus

cache

MMU

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Memory Management Unit (MMU)

• Hardware device: maps logical addresses to physical addresses.– Example: relocation register, limit register

• Historical Notes:– Motorola 68000 family had MMU with 68030

and later (1986 - …)– Intel x86 family introduced MMU for paging

with 80386 (1985 - …)

• Remark:– Embedded systems: often CPU w/o MMU.

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Binding Times?

Symbolic locations in programs (x, y, … ) can bebound to physical locations in memory at three stages:

1. Compile Time: if memory location is known, absolute code can be generated by compiler; must recompile code if starting location changes.

2. Load Time: compiler must generate relocatable code; loader transforms code to use absolute addresses.

3. Execution Time: binding delayed until run time; need hardware support for mapping between logical addresses and physical addresses.

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Physical Memory is Limited

• Dynamic loading – Routine not loaded into memory until it is called (error routine)

• Dynamic linking – Routine not linked with program until it is called (shared library)

• Swapping – Process swapped out of memory and brought back into memory for execution(more processes than fit into physical memory)

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Contiguous-Memory Allocation

• Characteristics:– 1 process = 1 block– blocks of variable size

• Dynamic Storage-Allocation– strategies: first-fit, best-fit, worst-fit

• Fragmentation Problem– external fragmentation– compaction of fragments

• Memory Protection– limit and relocation register

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Dynamic Storage Allocation

• When a process arrives, it is allocated memory from a block large enough to accommodate it.

• OS maintains information:a) allocated blocks b) free blocks

• Blocks with various sizes are scattered in memory.

OS

process 5

process 8

process 2

OS

process 5

process 2

process 9

OS

process 5

process 9

process 2

process 10

OS

process 5

process 2

process 10

OS

process 5

process 2

process 11

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Dynamic Storage Allocation

Strategies:– First-fit: Allocate the first block that is big enough; can

stop search as soon as a block is found.– Best-fit: Allocate the smallest block that is big enough;

must search entire list, unless list ordered by size. Produces the smallest leftover block.

– Worst-fit: Allocate the largest block; must also search entire list. Produces largest leftover block.

• Performance:– First-fit is generally fastest.– First-fit and best-fit better than worst-fit

in terms of speed and storage utilization.

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External Fragmentation

• External Fragmentation – total memory space exists to satisfy request, but not contiguous.

• Compaction – shuffle memory contents to place all free memory together in one large block.– possible only if relocation is dynamic

and can be done at execution time.– I/O problem: devices often use physical addresses.

• Statistic analysis of first-fit: 1/3 of memory may be unusable due to external fragmentation.

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Internal Fragmentation

• Internal Fragmentation: for reasons of efficiency, memory blocks are often allocated in fixed units(4, 8, 12, ... KB)

• A process requests 7KB,we are left with 1KB internal fragmentation!

• Fragments cannot be reclaimed by compaction

process

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Contiguous-Memory Allocation (cont’d)

• Location of System and User Processes:– Resident operating system: usually held in low

memory with interrupt vector.– User processes: usually held in high memory.

• Memory Protection:– Important: protect user processes from each other,

and from changing operating-system code and data.– limit register: range of logical addresses.– relocation register: value of physical start address.– each context-switch updates registers

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Memory Protection

registers loaded by context switch

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Paging

process 5

process 5:1

process 5:2process 5:3

pages framescontiguousmemory

OS

process 5:3

process 5:2

process 5:1

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Paging

• Characteristics:– 1 process = n blocks– block of fixed size

• Page: block in logical memory• Frame: block in physical memory

(typically 512 bytes to 16 Kbytes)

• Page table: translates logical to physical address• Free-frame list: keeps track of free frames.

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Paging: Address Translation

• Logical address generated by CPU:– Page number: index into a page table which contains

base address of each page in physical memory.– Page offset: added to base address; defines the

physical memory address sent to the memory unit.

• Physical address: found by translating page number into frame address and adding offset:

frame number offset

page number offset

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Paging Architecture

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Example: Page Allocation

page 1

page 2

page 3

page 0logical memory page table

page 0

page 2

page 3

page 1

1

2

34

5

6

0

physical memory

1

2

3

0

free-frame list

13 6 25

5

3

6

2

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Where is the Page Table?

• Page table too large to keep in CPU registers;thus, keep in main memory.

• CPU keeps track of location for each process:– Page-table base register: points to the page table.– Page-table length register: size of the page table.

• Every data/instruction access requirestwo memory accesses:1. access page table for lookup 2. access frame to get data/instruction

• Hardware support: fast-lookup cacheTranslation Look-aside Buffer (TLB)

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Paging Architecture with TLB

associative, high-speed memory,64 - 1024 entries

up to 1M entries

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Access Time with TLB?

Example:• TLB lookup: 20 nanosec• Memory access: 100 nanosec• Hit ratio: 98% (typically)

• Effective Access Time = (20 + 100)*0,98 + (20 + 100 + 100)*0,02 = 122 nanosec (22% more expensive)

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Memory Protection

• Memory protection implemented by associating protection bits with each frame in the page table.

• Valid-invalid bit:– valid: page in the process’ logical address space.– invalid: page not in the process’ logical address

space.

• Permission bits:– page is read-only– page is execute-only– page is read/write

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Paging with Status Bit

page 1

page 2

page 3page 0

logical memory

page table

i

i

v

i

page 0page 3

page 1

5

6

7

4

5

7

4

physical memory

1

2

3

0

v

v

v

v1

2

3

0

0

0

7

0

6

2

5

3

page 4page 26

page 4

frame number valid-invalid

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Size of Page Table?

Example:• Logical addressing: 32 bits• Logical memory: 4 GB (232)• Page size: 4 KB (212)• Number of pages: 1 M (232 / 212)• Page table size: 4 MB (each entry 4 bytes)

Each process may need a table with up to 4 MB contiguous physical memory. Divide page table into smaller pieces.

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Page Table Structures

• Hierarchical Paging– paging the page table– 2-level paging support (Pentium II)– 3-level paging support (SPARC)– 4-level paging support (Motorola 68030)– inappropriate for 64-bit architectures

• Hashed Page Tables– when address space larger than 32 bits

• Inverted Page Tables– 64-bit UltraSPARC, PowerPC

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Two-Level Paging: Address Translation

offsetp1 p2

Logical address (32 bits):

level 1page table level 2

page table

frame in physical memory

p1

p2

f

10 1210

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Two-Level Page Table (Pentium II)

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Hashed Page Table

• In architectures with 64 bit address space, hierarchical page tables become unpractical.– 8 KB pages have 5 levels

• Instead: hashed page table– The page number is hashed into a page table.– Each entry is a chain of elements hashing to the

same location.– Page numbers are compared in this chain searching

for a match. If a match is found, the corresponding frame number is extracted.

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Hashed Page Table

linked list

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Inverted Page Table

• Another solution to the size problem:one entry for each frame in physical memory.

• Each entry consists of the logical address ofthe page stored in that frame, with information about the process that owns that page.

• Page access:– Linear search (slow), or– Hash table over frames to limit search

to one – or at most few – page-table entries.

• Decreases memory: only 1 page table for all processes; but increases access time: need to search the inverted page table

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Inverted Page Table

linear search or hash table

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Shared Pages

• Shared code:– 1 copy of read-only code shared among processes

(i.e., editors, browsers, compilers). – Shared code must appear in same location in the

logical address space of all sharing processes.

• Private code & data: – Each process keeps a separate copy

of private code and data.– The pages for the private code and data can appear

anywhere in the logical address space.

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Shared Pages Example

lib 2

lib 3

lib 1

data

app 1

app 2

0

1

4

6

11

3

Process 1

2

1

12

6

5

3

9

lib 2

lib 3

app 1

lib 1

app 2

data

app 3

Process 2lib 2

lib 3

app 1

lib 1

data 8

1

7

6

3

Process 3

lib 2

lib 3

a2.1

lib 1

a2.2

data1

a2.3

a3.1

a1.2

data3

a1.1

data2

3

6

1

same page numberfor shared pages,read-only access

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Example of Segmentation

stack

user’s view physical memory

main

findmin

stackarray

array

main

findmin

program

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Segmentation

• Characteristics:– 1 process = n blocks– block of variable size

• Segment: a logical unit in a program- main program,- procedure, function, object,- common block,- array, stack, ...

• Normally, compiler arranges segments.• Dynamic storage allocation; fragmentation.

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• Logical address:

• Segment table: maps logical address into physical address; each table entry has– base: physical start address of segment– limit: length of segment– status bits: validity, access permissions

Segmentation: Address Translation

segment number offset

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Segmentation Architecture

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Memory Protection

• Each entry in segment table:– validation bit = 0 illegal segment– access privileges: read / write / execute

• Example: segment contains– code: execution-only– constants: read-only– array: read & write permission

• Example: each array in its own segment– automatic check that array indices are legal

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Sharing of Segmentsshared segments needsame segment number

jump [0,47]

jump [0,47]

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Segmentation with Paging

• Segment table:contains the base address of a page table for a segment, not the base address of the segment.

• Paging each segment:reduces problem of external fragmentation.

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1 tableProcess: 16K segments (214)each segment max. 4GB (232)

13 32

12

1010

Number of entries: 1024 (210)

Page table size:4KB (210 * 4 bytes)

i386 Segmentation w/Two-level Paging

Frame size: 4KB (212)

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Considerations for Memory Management Strategies (1/2)

• Hardware Support / Performance– base and limit registers– cache for page entries– associative memory, …– strategies cannot be implemented efficiently by SW

• Fragmentation / Utilization of Memory:– internal: fixed block size (when paging)– external: variable block size (when segmentation)

• Relocation:– requires logical address be relocatable at run time– compaction: shuffle programs in memory– pack more processes into available memory

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Considerations for Memory Management Strategies (2/2)

• Swapping:– dictated by CPU scheduling: allows more processes

to run than can be fit into physical memory

• Sharing:– share code & data among different users– requires paging or segmentation, dynamic linking

• Protection:– guard against programming errors / attacks– necessary when sharing code and data– requires that sections of user program

are execute-only, read-only, read-write

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Summary

1. Contiguous Memory (1 block, variable size)

2. Paging (n blocks, fixed size)1. Translation Look-aside Buffer (TLB)2. Hierarchical page tables3. Hash-based page tables4. Inverted page tables

3. Segmentation (n blocks, variable size)4. Segmentation with Paging (i386, Pentium)

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Source

• These slides are based on SGG04 and the slides provided by the authors.