STUDENT WORKBOOK.pdf

KIT FOR BASIC ELECTRONICS EXPERIMENTS EDU-2152 STUDENT WORKBOOK

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CONTENTS

Descriptions Page Rectifier Circuits 2 Diode Signals Circuits 12 Zener Diode Characteristics 18 Bipolar Transistor Characteristics 24 Transistor Biasing 33 Common Emitter Configuration 38 Common Collector Configuration 51 Multistage Configuration 57 Junction Field Effect Transistor 63 Operational Amplifier 66 Voltage Feedback 71 Active Filters and Howland Current Source 75 Basic Logic Gates 77


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Rectifier Circuits Objectives At the conclusion of the experiment, students will be able to: a) Describe waveforms in a half wave rectifier b) Describe waveforms in centre tapped power supply c) Describe waveforms in a bridge rectifier power supply d) Perform voltage and current calculations Overview The rectifier is an integral part of power supply circuits where it performs the basic AC to pulsating DC conversion. Common forms of rectifier circuits include wave, full wave centre tap transformer and full wave bridge rectifier circuits. Parts List & Material 1 EDU-2152 Kit 2 Digital Voltmeter 1 Oscilloscope Half Wave Rectification 1) Modify the circuit to reflect Figure 1. Note that the voltmeter to the right of the diode is

measuring pulsating DC.

2) Connect the primary side to 240 volts and measure the DC voltage across the 10K load

resistor. Calculate the theoretical value of the meter reading and record in Table 2. 3) Connect the oscilloscope across the load resistor (point B is the ground lead), observe and

sketch the waveform. Show peak voltages, ground line and period of the waveform. Calculate and record the frequency in Table 1.


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4) Change the oscilloscope connections to look across the rectifier diode. The ground should be at point A with the signal connection at point C. Since the forward voltage of the diode is only 0.7 volts, the signal that is seen is the Peak Inverse Voltage across the diode when the diode is not conducting. Record in Table 1.

5) Sketch the PIV waveform on the chart showing the peak voltage and 0 line.


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6) Add the series resistor and the 47 uF parallel capacitor as in Figure 2.

WARNING Observe the marked polarity of electrolytic capacitors at all times. Reversing an electrolytic may result in explosion and personal injury.

7) Connect the scope across the 10K load resistor ( Y to Z) and measure the DC voltage

with the DVM. Make sure that the coupling of the input on the scope is set for DC and sketch the waveform. This may appear to be a straight line but actually contains ripple.

8) Change the coupling of the oscilloscope input to AC and expand the vertical input until

the ripple shows a deflection of between 2 and 4 cms. Now sketch the ripple shape and note the peak to peak amplitude, period ( and hence frequency).


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9) Set the DVM mode setting to DC volts and measure the voltage plus ripple. Record in

Table 2. 10) Set the DVM to measure AC, measure and record the ripple voltage 11) Change the scope measurement points to measure the peak current thru the 10 W resistor

in series with the diode. The scope measuring point should be at point X and the ground at point Y as in Figure 2. Record the peak voltage in Table 2.

12) Calculate the peak current through the resistor (most of which goes into charging the

capacitor).

13) Calculate the theoretical ripple and note in your report how it compares to the

measurements obtained in Table 2.

14) Change the 10 K load resistor by adding a 1K, 2W resistor in parallel. 15) Move the scope back to measure between Y and Z (on the AC range) and record the new

ripple amplitude. Explain in your report why the ripple has increased compared to the value sketched in step 8).

16) Carefully observe the polarity of a 470 uF, 63 volt electrolytic capacitor before adding it in parallel with the existing 47 uF capacitor. Observe and record the new ripple amplitude. Explain in your report why the ripple has decreased.


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Full Wave Rectification There are two principal types of full wave rectification. One is by means of a centre tapped transformer and the other employs a full wave bridge. There are different requirements imposed on the various components in each configuration. Full Wave: Centre Tapped Transformer 1) Connect up the circuit as in Figure 4. Note that the centre tap of the transformer is used as

a connection. This circuit is in essence similar to that of the half wave rectifier in Figure 1. The essential difference is when the upper diode D1 cuts off, the lower diode D2 begins to conduct. In this manner, both of the halves of the waveform, with respect to the centre tap, are rectified.

2) Measure the DC voltage across the 10 K load resistor. Calculate the theoretical value of

the meter reading and record in Table 3. In your report, explain why this value is the same or different to the value obtained in Table 2 for the half wave rectifier.

3) Connect the oscilloscope to measure the voltage across the load resistor, observe and sketch the waveform on the graph. Show peak voltages, ground line and period of the waveform.

4) Change the oscilloscope connections to look across the rectifier diode. The ground should

be at point A with the signal connection at point C. Since the forward voltage of the diode is only 0.7 volts, the signal that is seen is the Peak Inverse Voltage across the diode when the diode is not conducting. Record in Table 3.


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6) Add the series resistor and the 47 uF parallel capacitor as in Figure 4.

WARNING Observe the marked polarity of electrolytic capacitors at all times. Reversing an electrolytic may result in explosion and personal injury.

7) Connect the scope across the 10K load resistor ( Y to Z) and measure the DC voltage

with the DVM. Make sure that the coupling of the input on the scope is set for DC and sketch the waveform. This may appear to be a straight line but actually contains ripple.


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8) Change the coupling of the oscilloscope input to AC and expand the vertical input until

the ripple shows a deflection of between 2 and 4 cms. Now sketch the ripple shape and note the peak to peak amplitude, period ( and hence frequency).


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Full Wave: Bridge Rectifier 1) Connect up the circuit as in Figure 5. Note that the centre tap of the transformer is not

used as a connection. This circuit is quite different to the full wave centre tap transformer configuration for the current has to flow thru 2 diodes to reach the output. On the positive cycle,current flows forward through D2 to reach point A while the return current mast flow back via D3. When the AC cycle reverses, the forward current is supplied via D4 and the return side flows back via D1. This is a very useful configuration as the output polarity remains the same irrespective of the input polarity.

NOTE The normal schematic for a bridge rectifier power supply is shown to the left with the diodes shown in a diamond shape.

2) Measure the DC voltage across the 10 K load resistor (A to B). Calculate the theoretical

value of the meter reading and record in Table 4. In your report, explain why this value is the same or different to the values obtained in Table 1 for the half wave rectifier and Table 4 for the full wave centre tap transformer.

3) Connect the oscilloscope to measure the voltage across the load resistor, observe and sketch the waveform on the graph. Show peak voltages, ground line and period of the waveform.


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4) Change the oscilloscope connections to look across the rectifier diode. The ground should

be at point A with the signal connection at point C. Since the forward voltage of the diode is only 0.7 volts, the signal that is seen is the Peak Inverse Voltage across the diode when the diode is not conducting. Record in Table 4.



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Diode Signal Circuits Objectives At the conclusion of the experiment, students will be able to: a) Describe positive and negative clippers b) Detail biased limiters c) Demonstrate the DC clamper (restorer) d) Demonstrate peak to peak detection e) Describe unwanted clamping and remedy Background Diodes find use in many types of circuits other than power rectification. In this lab we will explore some of the signal applications of diodes including limiting, DC clamping and voltage multiplication. Material & Equipment Required Function Generator Dual Power Supply Oscilloscope Kikisui Diode Limiter (Positive & Negative) 1) Connect up the circuit as in Figure 1. Set the generator to produce 60Hz with a peak to

peak amplitude of 10 volts.

Figure 1

2) Observe the waveform across the load resistor (scope DC coupled) and sketch the

waveform to vertical and horizontal scale.


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3) Explain why the waveform is the way as per your sketch. 4) Reverse the diode and repeat steps 1 & 2.

Biased Limiter 5) Connect the circuit up as per Figure 2. The batteries may be replaced with the dual

power supply. Adjust both power. supplies for 5 volts. 6) Observe the waveform across the load resistor and sketch the waveform to scale.


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7) Explain the relationship between the AC supply and the voltage seen across the load. 8) Reduce the amplitude of the power supply in series with D1 to zero. Record the

waveform to scale.

9) What conclusions do you draw between the observed wavforms and the amplitude of the

biasing voltage on the diodes?


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DC Restorer (Clamper) It is important to distinguish between the DC restorer or Clamper and the simple Limiter. The simple limiter cuts off all but one side of an AC waveform except for 0.7 volts and looks much like a half wave rectifier. The DC Restorer adds a DC voltage equivalent to the peak to peak of the waveform. The effect is that the waveform appears full amplitude (not rectified) with the lowest peak approximately at ground potential. To be more exact, the bottom of the peak will be at -0.7 volts for a silicon diode. 1) Connect up the circuit as in Figure 3. Set the frequency of the Wavetek generator to 120

Hz and the output level to 4 volts peak to peak. Be careful to observe the polarity of the capacitor.

2) Observe the waveform across the 10 K load resistor and sketch the waveform to scale.

3) Reverse the diode and sketch the waveform for the negative clamper.


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4) How does this circuit work? Explain the factors affecting the choice of time constant RLC.

Peak To Peak Detector The effect of a DC restorer (clamper) is to nearly double the AC voltage with respect to ground. If this signal is now rectified, as in Figure 4, the resultant DC value is nearly twice the original sinewave peak less the diode drop.

5) Connect up the circuit as Figure 4. Set the AC input at 120 Hz, 5 volts peak to peak.

Observe and sketch the waveform/level across the load resistor.


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Unwanted Clamping (No DC Return) Unwanted clamping is a major source of frustration for technologists and engineers. A firm understanding of what is wrong is essential to avoid the problem and to keep frustration within its normal limits! 1) Set up the circuit as in Figure 5 with the switch closed. Observe that there is a half wave

rectified signal across the output as might be expected.

2) Now open the switch across the capacitor and observe the waveform. 3) Explain what is happening to obtain the waveform observed above. 4) Connect a 1K resistor as shown in Figure 6 and observe the waveforms with the switch

open and closed.

5) Explain what is happening and why it is different from the previous case without the 1K

resistor.


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Zener Diode Characteristics Objectives At the conclusion of the experiment, students will be able to: a) Perform functional tests on zener diodes b) Plot diode forward characteristics c) Plot diode reverse characteristics d) Calculate zener resistance General A zener diode is a special type of diode where the diode has been optimized for operation in the reverse or avalache region. This is completely the opposite of normal diodes or rectifiers where every effort is made to keep the diode from breaking down in the reverse direction. The breakdown voltage can be well controlled and yields a device which exhibits a constant breakdown voltage over a wide range of currents. There is always a series resistor to limit the avalanche current and the zener finds great use as a voltage regulator. In the forward direction, the zener diode acts as a normal forward biased diode. Approximations First Approximation The first approximation is to treat the zener diode as a battery equal to the zener voltage when operated in the reverse (zener) mode.

Second Approximation The second approximation treats the zener as a series combination of the zener voltage and the zener resistance.


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Equipment & Material Required 1 EDU-2152 Kit 2 DVM 1 Dual Power Supply 1 Oscilloscope 1 Decade Box

Understanding Functional Zener Checks A zener diode can be checked for functionality using a DMM. This is because the voltage supplied by the DMM is less than 3 volts and (provided that the zener voltage is greater than 3 volts) the zener acts as a nomal diode in the forward direction. In the reverse direction, the zener does not reach the avalanche point and looks high resistance. Diode Tests 1) Connect up the equipment as in Figure 1 with the diode set to operate in the forward

direction.

2) Set the ohmmeter to the diode position (2 volt range). Measure the forward resistance of

the zener and record in Table 1. 3) Reverse the zener diode.Measure the reverse resistance and record in Table 1. 4) Calculate the ratio of the reverse to forward resistances.


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Forward & Reverse Characteristics 1) Connect up the circuit as in Figure 2 using the zener diode 1N4746.

2) Increase the voltage on the Anatek power supply until the voltage across the diode

indicates 0.05 volts. Record the voltage and current in Table 2. 3) Continue increasing the voltage in .05 volt increments and measure the current for the

values shown in Table 2.

4) Plot the forward characteristic of the zener diode on Graph 1


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NOTE Students generally are hesitant to plot during lab time but its the only way to ensure that you have reasonable data. If you only plot at report time, you may have errors which are only correctable by fudging or going back and repeating that part of the experiment.

5) Comment in your report how similar or dissimilar the forward zener characteristic is

compared to the silicon diode that you plotted in previous experiment.


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Zener Mode (Reverse) Characteristics In the reverse mode, the zener will go into controlled avalanche mode and yield a stable voltage over a wide range of applied voltages 1) Connect up the circuit as in Figure 3 using the zener diode.

Note that the zener diode connections have been reversed so that it is now operating in the reverse mode

2) Measure the voltages and currents obtained for the the reverse voltage values shown in

Table 3.

3) Plot the zener diode characteristic in the reverse direction. The reason that the graph

shows all negative values (while your table shows + ve values) is that the zener diode has been reversed with respect to the forward characteristic measurement.


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4) Using the values obtained for the zener characteristic, calculate the zener impedance for a

nominal input voltage of 14 volts. Use the voltage and current readings obtained for 12 and 16 volt inputs.


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Bipolar Transistor Characteristics Objectives At the conclusion of the experiment, students will be able to: a) Perform functional tests on transistors b) Demonstrate DC parameters in amplifier configuration c) Measure parameters for transistor as a switch d) Demonstrate current source parameters General Transistors form the basis for all modern electronics and so it is imperative to gain a good understanding of why and how they work. The single discrete transistor works the same way as any transistor in a complex integrated circuit containing over 100,000 transistors. Material & Equipment Required 1 EDU-2152 Kit 1 DMM 1 Power Supply Checking Transistors It is often necessary to perform a quick check on a transistor to determine if its working and what type it may be. Bipolar transistors are either NPN or PNP depending on the arrangement of materials as in Figure 1.

For purposes of quick testing only, a transistor can be thought of as two back to back diodes as in Figure 2 and hence the transistor can be tested in the same manner as a diode.

1) Connect up the circuit as in Figure 3 using the 2N3904 transistor. Measure the forward

diode directions. Be sure to connect the positive lead of the DVM to the base and be on the diode range of the DMM (2K).


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2) Record the data in Table 1, then reverse the leads and measure from base to emitter and

base to collector with the Com lead on the base. 3) Repeat steps 1) and 2) with the 2N3906 transistor.

Transistor Base to Emitter Base to Collector NPN or PNP

2N3904 + on base 2N3904 - on base

2N3906 + on base 2N3906 - on base

Table 1


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Transistor Amplifier 1) Connect up the circuit as in Figure 4. Set the power supply to on, measure and record the

parameters shown in Table 2 .

Transistor in Switch Mode 1) Connect up the circuit as in Figure 4A. Set the power supply to 15 volts and measure the

values per able 5. Calculate the power supply dissipation in the 1K resistor and in the transistor.


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2) Explain the advantages and operation of switch mode for turning the LED on and off. Transistor Current Source Constant current sources are sometimes difficult for students to understand. The constant current source is not exactly intuitive and can best be explained as the opposite of a contant voltage source. In the voltage source, the voltage remains constant over a range of currents (and loads) while in the current source, the current remains constant over a range of voltages (and loads). There are limits. Eventually, the constant voltage source runs out of current and the constant current source runs out of voltage. 1) Connect up the circuit as in Figure5. The collector current and collector voltage meters

should be left in position while the other measurements can be taken with one meter. Be sure to switch off while moving ammeter instruments. Notice that there are 2 power sources in the circuit and that RLOAD is the Resistance Box


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2) Set the load to zero ohms and take measurements of:

RLOAD The collector load resistance IBASE The base current VBASE The base voltage IEMITTER The emitter current ICOLLECTOR The collector current VCOLLECTOR The collector current

3) Change the load value to the next line in Table 5 and repeat for all values of load resistance shown.

4) Plot the following characteristics during lab time. If there are any anomalies, (such as

may be due to oscillation), go back and check the measurement before proceeding. a) Collector current and collector voltage against load. b) Base to emitter voltage drop across load.


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c) Base current against load The plots should approximate the examples shown on the following page.

5) Comment in your report about why the current remains constant over the load range of 0 to 800 ohms. Explain why the load voltage does not go to zero and why the base current rises when the collector falls out of constant current mode.


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6) Remove the resistance box connect a Light Emitting Diode (LED) in its place per figure

6.

7) Vary the collector power supply between 10 and 20 volts in 5 volt increments and

measure the collector current.


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8) Comment in your report about the LED brightness under varying applied collector voltages.


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Transistor Biasing Objectives At the conclusion of the experiment, students will be able to: a) Describe base bias b) Describe emitter feedback bias c) Describe collector feedbackbias d) Describe voltage divider bias General In order for the transistor to be useful, it needs to be biased in manner suitable for the intended application. Material & Equipment Required 1 EDU-2152 Kit 1 DMM 1 Power Supply Base Bias 1) Connect the resistors shown in Figure 4. 2N3904 is used in this experiment.

2) Calculate theoretical values for IB, IC ,and VC and record them in Table 1. Assume a of

200 for purpose of calculation. Do not proceed without the calculations.


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Calculated Room Temp

VB

IB

VCE

IC

VE 0

IE

200

Table 1

Base Bias 3) Measure the room temperature parameters and make appropriate calculations for:

a) VB Record VB b) V270 K and calculate IB Record IB c) VCE Record VCE d) V750 and calculate IC Record IC e) Calculate IE Record IE f) Calculate Record

Emitter Stabilized Bias 1) Connect up the circuit shown in Figure 5 using the resistor values shown.


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2) Calculate theoretical values for IB, VB, IC , IE, and VCE and record them in Table 1. Assume a of 200 for calculation. Do not proceed without the calculations.


VB

IB

VCE

IC

VE

IE

200

Table 2 Emitter Stabilized Bias

3) Measure the room temperature parameters and make appropriate calculations for:

a) VB Record VB b) V470 K and calculate IB Record IB c) VCE Record VCE d) V910 and calculate IC Record IC e) V100 and calculate IE Record VE , IE f) Calculate Record

Collector Feedback Bias 1) Connect up the circuit as in Figure 6 using the resistor values shown.


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2) Calculate theoretical values for IB, IC ,and VC and record them in Table 1. Assume a of 200 for purpose of calculation and VCE of 8.3 volts. Do not proceed without the calculations.


VB

IB

VCE

IC

VE 0 0

IE

200

Table 3 Collector Feedback Bias


a) VB Record VB b) V220 K and calculate IB Record IB c) VCE Record VCE d) V910 and calculate IC Record IC e) Calculate IE Record IE f) Calculate Record

Voltage Divider Bias 1) Connect up the circuit as in Figure 7 using the resistors shown.


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2) Calculate theoretical values for all table parameters and record them in Table 1. Assume a of 200 for purpose of calculation. Do not proceed without the calculations.


VB

IB

VCE

IC

VE

IE

200

Table 4 Voltage Divider Bias


a) VB Record VB b) V2.2 K and calculate IB Record IB c) VCE Record VCE d) V3..3 K and calculate IC Record IC e) Calculate IE Record IE f) Calculate Record

Stability Which are the most and least stable bias cicuits? Give reasons.


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Common Emitter Configuration Objectives At the conclusion of the experiment, students will be able to: a) Calculate the DC conditions of an unloaded amplifier b) Calculate the peak to peak AC conditions c) Build the circuit and measure the actual conditions d) Calculate the AC conditions of a loaded amplifier e) Build the circuit and measure actual conditions f) Determine input impedance and output swing of an amplifier with emitter swamping resistor Equipment & Material Required 1 EDU-2152 Kit 1 Power supply 1 DVM Fluke 1 Function Generator General This lab is primarily concerned with the transistor in Common Emitter (CE) configuration. In CE, the emitter is grounded with respect to AC. There can be an emitter resistor providing DC stability, however, if it is bypassed, the circuit is in CE configuration. In this lab, the circuits in Figure 1 and Figure 4 are not strictly speaking in CE configuration because of the unbypassed emitter resistors. All the circuits used are AC coupled in and out. The two 10 uF capacitors block DC to both the load and the signal source. The DC conditions are identical for all 4 circuits but the AC conditions vary considerably. In circuit Figure 1, there is no emitter bypass capacitor and so the DC and AC gains are nearly the same. Figure 2 has an AC emitter resistor bypass and thus a different AC gain. In the circuit of Figure 3, the effects of external load resistance and source resistance loading need to be taken into account. Figure 4 contains a swamping resistor to give greater AC gain stability and this in turn has an effect on the AC gain and base input impedance. Students should clearly identify the difference between the external emitter resistor RE which is shown and the internal emitter resistance re which is not shown. The following notations are used with this lab.


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Prelab For the circuit shown in Figure 1, work out the parameters shown down the right margin. Assume = 150 for all circuits


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Amplifier With Emitter Bypass 1) Construct the circuit as in Figure 2 on the breadboard. Keep leads short and use twisted

pair to supply the circuit with power. Be careful to observe the correct polarity of the electrolytic capacitors.

2) Calculate the AC gain and the peak to peak amplitudes of the 1000 Hz AC signal at the

base and collector of the transistor when the AC source voltage has been adjusted to give 50 mV peak to peak at the base of the transistor.

3) Estimate the maximum peak to peak voltage possible (without clipping) and calculate the input at the base of the transistor to give the maximum output.

4) Transfer the following DC data from the pre lab calculations to Table 2 and then measure

the actual values. Account for any descrepancies. 5) Use the DVM on AC scale to adjust the output of the Wavetek generator so that the

reading at the base of the transistor is 17.7 mV (RMS). Verify that the scope indication at the same place is approximately 50 mV peak to peak.


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6) Transfer the following AC data from Table 1 to Table 3 and then measure the peak to

peak values using the oscilloscope. Account for any descrepancies.

7) Plot the AC and DC values on Graph 1 using the same vertical scale. Show all phase

relationships on Graph 2 where you may use any vertical scale to illustrate the point. NOTE The input AC voltage will be so small as not to be plottable. In such cases, draw a line with a slightly exagerated wiggle to distinguish it from the absolute straight line of the DC side. The single vertical scale plot is useful in determining the operating points and estimating maximum swings. For instance seeing the supply voltage and emitter voltage levels gives a first glance approximation of maximum AC swings and the desired collector operating point. The AC signal can not swing above the supply voltage or below the emitter voltage. In similar fashion, the base bias point and associated emitter voltage determine the maximum input signal which will not drive the base/emitter into cutoff and cause distortion. An illustration is shown in Figure 3.


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Amplifier With Load & Source Resistances In the previous section the input voltage was adjusted so that the base voltage was 50 mV peak to peak and the only load was the collector resistor. In reality the source will have a resistance (2K in our examples) and a load. The load resistor RL and the collector resistor are effectively in parallel and so affect the gain.

There is a voltage drop across the source resistance because of the voltage divider action of the source resistance, the base bias resistors and the impedance looking into the base. The latter 3 items are all effectively in parallel. The effect is illustrated in Figure 4.


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The source impedance ZS is a combination of the series capacitor and the series 2K resistor. The impedance of a 10 uF capacitor at 1000 Hz is small (16 ohms @ 1000 Hz) compared to the 2000 ohm resistor and can be ignored for approximation purposes leaving ZS at 2K. The impedance looking in to the base ZB can be approximated as:

When the emitter resistor is fully bypassed with a large capacitor, ZE becomes zero leaving re Note that this discussion concerns the impedance (AC) and not the resistance. If you consider the DC aspects, then looking into the base you will see multiplied by the unbypassed emitter resistance. This is because the bypass capacitor is infinite impedance at DC. You should take special note of this for the last section which deals with a swamped amplifier configuration where there is an unbypassed and a bypassed resistor in the emitter making both the AC and DC gains different and having a different AC and DC impedance looking in thru the base.


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1) Add the 1.5 K resistor to form an external load on the amplifier. 2) Calculate the AC gain and the peak to peak amplitudes of the 1000 Hz AC signal at the

base and collector of the transistor when the AC source voltage has been adjusted to give 50 mV peak to peak at the output of the generator and before the 2K series resistor.

3) Estimate the maximum peak to peak voltage possible (without clipping) and calculate the input at the output of the generator and before the 2K series resistor to give the maximum output.

4) Use the DVM on AC scale to adjust the output of the function generator so that the

reading at the output is 17.7 mV (RMS). Verify that the scope indication at the same place is approximately 50 mV peak to peak.

5) Transfer the following AC data from Table 4 to Table 5 and then measure the peak to peak values using the oscilloscope. Account for any descrepancies.

6) Plot the AC and DC values on Graph 3 using the same vertical scale.


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7) Comment on any differences between you data above and the data obtained in Graph 1.

The DC conditions are the same but the AC conditions will be different.


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Swamped Amplifier While the emitter resistor RE provides DC negative feedback, it is often bypassed with a capacitor to provide greater AC gain. This in turn gives rise to the problem of stability of the AC gain because:

Now re varies with the emitter current and temperature and is generally low (1 to 20 ohms compared with our circuit where the collector resistance of 3300 ohms) and so the AC gain stability is not great. An acceptable way of gaining stability at the expense of some of the gain is to split the emitter resistor into 2 resistors,one of which is left unbypassed. If the value of RE is an order of magnitude greater than re, the changes in gain due to variations in rewill be swamped out by the unbypassed emitter resistor. Thus the name Swamped Amplifier. A secondary effect of having a part of the emitter resistor that is unbypassed is that the AC impedance looking into the base is higher. This in turn means that less voltage is dropped across the source resistance RS.


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1) Change the emitter configuration to reflect Figure 6. Be sure that the bypassed resistor is the 820 ohm and not the 180 ohm.

2) Calculate the AC gain and the peak to peak amplitudes of the 1000 Hz AC signal at the base and collector of the transistor when the AC source voltage has been adjusted to give 50 mV peak to peak at the output of the generator and before the 2K series resistor.

3) Estimate the maximum peak to peak voltage possible (without clipping) and calculate the input at the output of the generator and before the 2K series resistor to give the maximum output.

4) Use the DVM on AC scale to adjust the output of the function generator so that the

reading at the output is 17.7 mV (RMS). Verify that the scope indication at the same place is approximately 50 mV peak to peak.

5) Transfer the following AC data from Table 5 to Table 6 and then measure the peak to peak values using the oscilloscope. Account for any descrepancies.

6) Plot the AC and DC values on Graph 3 using the same vertical scale.


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AC Stability As noted previously, the fully bypassed emitter is vulnerable to temperature changes because of its reliance on re which changes with temperature. It is instructive to measure the change in output in the fully bypassed and swamped configurations. This test is only a demonstration because the actual temperature can not be well controlled. 1) Adjust the generator output so that the output swing at the collector is 2 volts peak to

peak using the circuit of Figure 6. 2) Apply heat at a distance of 12 for 10 seconds and measure the change in peak to peak

signal (do it quickly). Record in Table 7 and calculate the % change. 3) Switch off the power and move the bypass capacitor to the emitter and ground so that the

circuit is now the equivalent of Figure 2 because the 180 ohm and 820 ohm resistors total the same 1K as in Figure 2.

4) Readjust the generator output so that the collector swing is again 2 volts peak to peak. Apply heat at a distance of 12 for 10 seconds and quickly take the peak to peak reading at the collector.

5) Record the result in Table 7 and calculate the % change. Comment in your report on the reasons for different stabilities.


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Common Collector Configuration Objectives At the conclusion of the experiment, students will be able to: a) Calculate the DC conditions of a loaded emitter follower b) Simulate the DC conditions under different loads c) Calculate the AC conditions of a loaded emitter follower d) Simulate the AC conditions under different loads e) Build the circuit and measure actual conditions f) Draw the effect of AC coupling on the load at low loads. Equipment & Material Required 1 EDU-2152 Kit 1 Power supply 1 DVM 1 Function Generator General This lab is primarily concerned with the transistor in Common Collector (CC) configuration. In CC, the collector is grounded with respect to AC (because the power supply is an AC short). The circuits use a PNP transistor and so the power supply is upside down compared to the NPN transistor. Your thinking needs to be upside down too with voltages decreasing from more negative at the collector and becoming more positive towards ground. The Common Collector configuration is usually known by its common name of emitter follower. The signal at the emitter follows the signal at the base and is in phase with the base. At first glance, it would appear that this is not a useful circuit until the circuit impedance is considered. The emitter is low impedance and can therefore can drive low resistance loads without much attenuation (as opposed to what would would happen if the output was taken from the collector). The circuits used are AC coupled in and may or may not be AC coupled out.. The input 10 uF capacitor preserves the bias from being drained into the signal source. The output 470 uF isolates the DC from the load but limits the range of loads more than DC coupling.

VB Voltage between the base and ground VC Collector & power supply voltage VE Voltage between the emitter and ground. RE Emitter resistor Rload External load on circuit


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General This lab is in different format to previous labs. There is less explanation, less requirements for the write up and more requirement to adhere to the order of the procedure. When the instructions say calculate or emulate, they mean now, not later. Do not proceed to a new section without having the previous section signed off by the lab instructor. DC Coupled Emitter Follower 1) For the circuit shown in Figure 1, calculate the DC conditions required for Table 1.

Assume = 150.


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2) Simulate the same conditions and fill in the results in Table 2. Do not forget to set to 150 for your simulation. Keep a copy of your simulation.

3) Calculate the AC gain of Figure 1 when the input signal (function generator output) is

2.82 volts peak to peak (1 volt RMS) @ 10 KHz under the load conditions specified in Table 3.

4) Simulate the AC gains using your previously saved simulations for DC conditions.

Record your results in Table 4.


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5) Fabricate the circuit of Figure 1. Set the Wavetek output to zero and measure the DC voltage parameters required in Table 5. Calculate the current parameters based on voltage and resistance.

6) Set the Wavetek output to 2.83 volts pp (1 volt RMS) and measure the gains at the

various loads specified in Table 6.

AC Coupled Emiter Follower 1) Add the 470 uF capacitor to the existing circuit so that it becomes Figure 2.


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2) Measure and calculate the parameters of Table 7. In each case, carefully draw the output waveform to scale.


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Multistage Configuration Objectives At the conclusion of the experiment, students will be able to: a) Calculate the DC conditions of a two stage circuit b) Calculate the AC conditions of the configuration c) Simulate the circuit d) Build the circuit and measure the actual conditions e) Simplify the circuit and compare to previous circuit Equipment & Material Required 1 EDU-2152 Kit 1 Power supply 1 DVM Fluke 1 Function Generator General This experiment combines the elements of the Common Emitter and Common Collector circuits which were investigated previously. The first stage is used for voltage gain while the second stage acts as a buffer which does not impose undue load on the amplifier stage. The approach to this experiment is the same as before:

Theoretical design calculations Simulation (possibly adjustment of design calculations) Fabrication & test Account for discrepancies

The initial circuits are AC coupled and have individual voltage divider biasing. Inspection of the circuit will show that the common collector (emitter follower) section can be DC coupled to the output of the amplifier stage. The following notations are used with this experiment.

VB Voltage between the base and ground VC Voltage between the collector and ground VE Voltage between the emitter and ground. RE Emitter resistor, bypassed or not. RC Collector resistor Rload External load on circuit


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AC Coupled Configuration 1) The complete AC coupled version of the circuit is shown in Figure 1 2) Calculate the full DC conditions per Table 1. The emitter follower does not have an effect

on the DC conditions of the voltage amplifier. Assume a of 150.


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3) Calculate the AC conditions and record in Table 2.

NOTE This is more complex than the DC conditions because you must take the loading of both input and output stages into account. In general, you will need to work backwards from Q2. Calculate the output load on Q2, then Z base looking into Q2. Zbase and the Q2 bias resistors are now effectively in parallel with the collector load resistor of Q1. Work out the gain of Q1 using re , the unbypassed part of the emitter and the total collector load. In similar fashion, calculate the Z base looking into Q1. Z base and the Q1 bias resistors are effectively in parallel and form a voltage divider with the source input resistor (1K). Now you are in a position to apply the 300 mV RMS signal and calculate the AC voltages per Table 2.

4) Calculate the stage gains and the overall gain:

Gain of Q1 stage: ________ Gain of Q2 stage: ________ Overall Gain: ________

5) Simulate the complete circuit showing both the DC conditions and the AC conditions. You may change your voltmeters from DC to AC instead of having 6 voltmeters. Print both DC and AC readings. Save your circuit.

6) Transfer your data to Tables 3 and 4.


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7) Account for descrepancies between the calculated and simulated values. Building The Circuit 1) Fabricate the circuit of Figure 1 on a prototype board but do not connect the coupling

capacitor between the collector of Q1 and the base bias resistors of Q2. 2) Set the Wavetek output to zero, measure the DC values associated with the circuit and

record in Table 5.

3) Investigate and correct descrepancies. 4) The collector voltage of Q1 is similar to the bias voltage of Q2 with the latter being

slightly higher in the design. Variation in may have reversed which one is actually higher. Connect the 47 uF coupling capacitor between the Q1 collector and Q2 base observing the polarity of your system.

5) Adjust the output of the function generator to 300 mV RMS @ 1000 Hz. Measure and record the AC voltages per Table 6.


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NOTE Measuring RMS voltages with a DVM yields more accurate readings than can be obtained with student oscilloscopes. The assumptions are that the frequency is within the range of the DVM and that the waveform is a sine wave. If the waveform is partially cut off or otherwise distorted, the DVM will not tell you! For this reason, it is good practice to also look at the measurement points with the oscilloscope.


Simplification The astute student will have noticed that the bias of Q2 and the collector of Q1 are similar and that the circuit can be simplified by removing the interstage coupling capacitor, and the base biasing resistors for Q2. The arrangement is shown in Figure 2.

1) Simplify the circuit per Figure 2. Do not adjust the function generator output. Measure

the actual AC signals per Table 6.


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2) Compare the gains and output levels with Table 6. Explain why the final output is higher

in the simplified circuit. 3) Recalculate the AC levels in the circuit as result of the insights obtained in step 3. Show

your working out (neatly).


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Junction Field Effect Transistor Objectives At the conclusion of the experiment, students will be able to: a) To determine the stability of different methods of bias for the JFET. b) To build a common source amplifier and a source follower. Equipment & Material Required 1 EDU-2152 Kit 1 Function Generator 1 Power supply 1 Oscilloscope 1 DMM Gate Bias Refer to the data sheet for the MPF102. Note the VGS(off) has a maximum of -8V; the minimum is not specified. Also notice that IDSS has a minimum of 2 mA and a maximum value of 20 mA. Connect the circuit as shown in Figure 1a. Upon power up, measure the drain current IDSS quickly and power down. Refer to the data sheet and explain why this should be done quickly. Connect the circuit as shown in Figure 1b. Gate bias is being applied where a fixed gate voltage reverse biases the gate of the JFET. This produces a drain current less than IDSS. The problem here is that you cannot accurately predict the drain current in mass production because of the variation in the required VGS. Measure VGS, ID and VD. Obtain three other sets of data taken from other students. Comment on your findings.

Use the same gate biased circuit to measure VGS(off) . This is done by increasing the negative gate supply voltage until the drain current is approximately 1A. Record VGS(off) .


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Self Bias Connect the circuit shown in Figure 2. Assume Vgs = -2V (for pre-lab). Calculate and measure ID, VD and VS (for your report recalculate expected values based on IDSS and VGS(off) measured in part 1 rather than the assumed value for Vgs). Obtain three other sets of data from other groups and compare. Comment on the stability of ID .

Voltage Divider Bias Calculate and measure ID, VD and VS for the circuit shown in Figure 3 (for pre-lab assume VGS = -2V, IDSS = 10 mA and VGS(off) = -4V ; for write-up recalculate based on actual values of IDSS and VGS(off) of your JFET found in part 1). Obtain three other sets of data from other groups and compare.


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Current Source Bias Calculate and Measure ID, VD, and VS for the circuit shown in Figure 4. Obtain data from three other groups and compare. Calculate and measure VD and VC for each of the troubles:

i) R2 shorted ii) R3 open One purpose of this lab is to determine the stability of different methods of JFET bias. Compare the stability of the four methods of bias.

Source Follower For the JFET amplifier of Figure 5, assume a gm of 2000S. For pre-lab, calculate the unloaded voltage gain, output voltage and output impedance. For your report, recalculate the quantities above based on actual gm. Connect the circuit with RL equal to infinity and input a signal of 1Vpp at 1kHz. Measure and record the output voltage and calculate the voltage gain. Measure and record the output impedance by attaching a 1k ohm pot to the output and adjusting the pot until Vout is half of its no load value (open circuited load). The output impedance will be equal to the resistance value of the potentiometer.


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Operational Amplifier Objectives At the conclusion of the experiment, students will be able to: a) To build and measure the foregoing quantities of the differential amplifier. b) To connect and test a basic op amp circuit. Equipment & Material Required 1 EDU-2152 Kit 1 Function Generator 1 Power supply 1 Oscilloscope 1 DMM The Differential Amplifier 1) Connect the circuit as shown in Figure 1. Notice the pair of swamping resistors (22 )

which have been included to improve the match between the discrete transistors. (Assume hFE is 200). Calculate and measure the tail current and the base current in each transistor (by measuring the voltage across each base resistor). With the calculated data, calculate the values of input offset current and input bias current. With the measured data, determine the Iin(off) and Iin(bias).


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2) Connect the circuit as shown in Figure 2. The output voltage would have a value of +7.85V if all the following are true: the base of Q1 is grounded by a jumper wire, both transistors are identical (VBE is 0.7V) and all components have the values shown.

Show the above statement is true. Any deviation from the +7.85V stated above is an output offset voltage.

Ground the base of Q1 with a jumper wire and measure the dc output voltage. Calculate the output offset voltage. Remove the ground from Q1 and adjust the potentiometer until Vout = 7.85V. Measure the base voltage of Q1. This voltage is V1off (input offset voltage). The output offset voltage over the input offset voltage gives the measured gain of the amplifier. Compare to expected gain.

3) Connect the circuit as shown in Figure 3. Calculate the differential voltage gain A

(include the effects of the swamping resistor) and the common mode voltage gain Acm. With the applied signal, measure the output signal and determine A. Put a jumper wire between the basses of your circuit and increase the signal level until the output voltage is 0.5Vpp. Measure the peak to peak input voltage and determine Acm. With these data, calculate the theoretical and experimental values of the common mode rejection ratio (CMRR).


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The Operational Amplifier 1) The 741C has a typical input bias current of 80nA. Assuming that this is the base current

in each 220k resistor in Figure 4, calculate the dc voltages at the inverting and non inverting inputs. Connect the circuit and measure the dc voltages at each input. With this data, calculate Iin(off) and Iin(bias). Note is quite normal for your value to be significantly different than the typical value.

2) Connect the circuit shown in Figure 5. Measure the dc output voltage (Vout(off) ) and

determine the input offset voltage (assuming gain = 1000). For your prelab just give the equation that relates input and output voltages. This will allow you to calculate the input offset voltage during the lab; it is too small to measure directly.


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3) Starting with the same circuit disconnect the 100k resistor from pin 6 (the output) and

connect the now free end of this resistor to +15V. This will apply 15mV to the inverting input to saturate the op-amp. Replace the 10k load with the DMM as an ammeter and record the maximum output current.

4) Connect the circuit shown in Figure 6 with an R2 of 100k. Using the scope, set the input signal at 5kHz and adjust the signal level to get hard clipping on both peaks of the output waveform. The output will no longer look like a sign wave but more like a square wave having sloping edges. Calculate the slew rate from the measured slope of the rising edge of the wave.


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5) Change R2 to 10K. Set the input signal to 1kHz and adjust the signal level to get 10Vpp out of the op-amp (you will get a sign wave out this time). Slew rate distortion will become evident as the frequency is increased from 1 to 20kHz. Record the approximate frequency at which slew rate distortion begins. The data sheet states a minimum value for the slew rate of the op-amp. Calculate the minimum frequency at which slew rate distortion could start based on the minimum slew rate in the data sheet.

6) Set the signal generator at 1 kHz and increase the signal level until clipping starts on either side. Record the AC output compliance of the op-amp.


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Voltage Feedback Objectives At the conclusion of the experiment, students will be able to: a) To investigate the four distinct types of negative feedback. b) To measure and calculate the bandwidth for different voltage gains in order to confirm that the gain bandwidth product is a constant. c) To measure the output offset voltage of an operational amplifier. Equipment & Material Required 1 EDU-2152 Kit 1 Function Generator 1 Power supply 1 Oscilloscope 1 DMM Non-Inverting Current Feedback Connect the circuit shown in Figure 1. For each dc input voltage from 1.0 to 10V in steps of 2.0V, calculate the dc output current. In obtaining a set of experimental values, adjust the decade resistance box to get different input voltages and measure the resulting current. Inverting Voltage Feedback Connect the circuit shown in Figure 2. For each input current from 1 mA to 10 mA in steps of 2mA, calculate the output voltage. Again, adjust the decade resistance box to get the experimental values. Inverting Current Feedback Connect the circuit shown in Figure 3. For each input current from 0.1 mA to 1 mA in steps of 0.2 mA, calculate the output current. Again, adjust your decade box to get the output currents. Non-inverting Voltage Feedback a) Connect the circuit shown in Figure 4. For each dc input voltage from 0.1V to 1.0V in

steps of 0.2V, calculate the dc output voltage. In obtaining a set of experimental values, adjust the decade resistance box to get each dc input voltage.

b) Calculate the closed loop voltage gain ACL for each value of R1 = 10k, 22k, 47k, 68k, 100k in the circuit of Figure 5. The typical gain bandwidth product of a 741C is 1mHz. Calculate the closed loop cutoff frequency for each R1. Why is it important to know that the gain bandwidth product is constant?


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Connect the circuit and measure ACL = Vout/Vin for each value of R1. Obtain two other sets of data from other groups and comment on the stable voltage gain for different op-amps. For each value of R1 measure the upper cutoff frequencies. Comment on how to increase the bandwidth of a circuit.

c) Differences in the VBE values and the base currents imply there is a dc input offset voltage in Figure 6. Assume the total input offset voltage is 2mV. Calculate the output offset voltage for each value of R1 listed in (b). Connect the circuit in Figure 6 and measure the output offset voltage for each value of R1.


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74


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Active Filters and Howland Current Source Objectives At the conclusion of the experiment, students will be able to: a) To test a first order low pass filter. b) To measure the cutoff frequency of a second order low pass filter. c) To experiment with a second order high pass filter. Equipment & Material Required 1 EDU-2152 Kit 1 Function Generator 1 Power supply 1 Oscilloscope 1 DMM First Order Low Pass Filter Connect the circuit shown in Figure 1. Set the signal generator at 100Hz and adjust the signal level to get 1Vpp at the output of the filter. Record both the input and output peak-to-peak values. Repeat this for the frequency range of 100 Hz to 10kHz in the appropriate steps. Calculate the voltage gain for each frequency, and then calculate the equivalent decibel gain. Plot the decibel gain against log f and determine the cutoff frequency. Determine how fast the voltage gain decreases above cutoff. What is the theoretical voltage gain at 100Hz? Explain why this may be different from the measured result. Second Order Low Pass Filter Connect the circuit shown in Figure 2 (use two 0.01mF capacitors in parallel for the 0.02mF capacitor specified). Repeat the procedure outlined in 1 a) and 1 b). Compare your results with that in Procedure 1. Comment on the advantage of this filter over that in Procedure 1. Second Order High Pass Filter Connect the circuit shown in Figure 3. Set the signal generator at 10kHz and adjust the signal level to get 1Vpp at the output of the filter. Repeat the procedure as outlined in 1 a) and 1 b). If you want to double the cutoff frequency, what changes must you make? Connect the Howland circuit. Obtain data of load current vs. input voltage. What is the load current as the op amp saturates. Change the load resistance and repeat.


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Basic Logic Gates NOT Gates The binary number system is essentially a code which require two discrete states, generally designated 1 and 0. This representation is basic to digital devices and systems, and these two states are easily realized as voltage levels in and electronics circuit. Any two voltages could be used, but in currently available integrated circuits (ICs) the most common voltage chosen are +5 and 0V dc. One then makes the following definitions:

1 = +5V dc 0 = 0V dc

These two states are often referred to as logic levels, and this a voltage of +5V dc represents a logic level 1 (sometimes called logical 1), while 0V dc represents a logic level 0 (logical 0). An important fundamental logic function is the conversion from one logic level to the other, i.e., the ability to change a 1 to 0 or a 0 to 1. Changing from one logic level to the other is called complementing. A unit which will provide the complement is quite easy to realize with an electronic circuit, since this simply means changing +5V dc to 0V dc or vice versa. A basic electronic circuit whose output is the complement of its input is the inverting amplifier. The symbol for an inverter as used in digital electronics is shown in Figure 1(a). The triangular part of the symbol shows that this is an amplifier; it is especially important to note that the small circle o on the output signifies signal inversion.

(a)

VIN VOUT 0 1 1 0

(b)

Figure 1 (a) Inverter (b) Truth Table

VIN VOUT


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Thus, if VIN = 0V dc, then VOUT = +5V dc, and if VIN = +5V dc, then VOUT = 0V dc. A tabular listing of the voltage outputs for each input voltage for the inverter is called a truth table, and this is shown in Figure 1(b). The typical Transistor-Transistor Logic (TTL) inverter is composed for a number of transistors, resistors, and diodes and as a result the inverter output voltage levels depart somewhat from the ideal values of +5V and 0V dc. To establish acceptable operating limits, the manufacturers will list on data sheets the maximum, minimum and typical values for the output voltage levels. Figure 2 is a graphical representation of the inverter output voltage V0. When the inverter output is at logic level 1, the manufacturer guarantees that the output voltage in this high state will be somewhere in the band labeled VOH in Figure 2. The maximum voltage level, VOH, max is +5V dc (VCC), and the minimum voltage level is given as VOH, min on the data sheet. Most inverter circuit has a logic 1 output level, VOH, typical, near the middle of the high-level band. The 54/74LS06 data sheet lists VOH, typical = 3.4V dc (the AS04 is slightly different). If you measure VOH and find that the voltage level is not within the limits specified by VOH, min and VOH, max, the unit should be considered defective and it should be replaced.

Figure 2 TTL output voltage levels. When the inverter is at logic level 0, the manufacturer guarantees that the output voltage in this low state will be somewhere in the band labeled VOL, min, is 0V dc [which is ground (GND)], and the maximum voltage is given as VOL, max on the data sheet. Most inverters have a logic 0 output level, VOL, typical, near the bottom edge of the low-level band. The 54/74LS06 data sheet lists VOL, typical as +0.2V dc. If you measure VOL and find that the voltage level is not within the limits specified by VOL, min and VOL, max the unit should be considered defective, and it should be replaced. Except when switching from one state to the other, the inverter output voltage level must be either in the high band or in the low band. The transition region in Figure 2 is therefore a forbidden output voltage region, except for the short time required for the inverter output to switch from one voltage level to the other.


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Since the output of an inverter may be used as the input to another inverter, or indeed to any of a multitude of other TTL logic, limits must be placed on the input voltage levels to ensure that all TTL logic circuits are compatible with one another. Acceptable TTL input voltage levels are summarized in Figure 3.

Figure 3 TTL input voltage levels

In order for an inverter input voltage to be recognized as a logic 1, it must be somewhat within the band specified by VIN in Figure 3. The maximum value, VIH, max, is of course +5V dc (+VCC), and the minimum value VIH, min is specified on a data sheet. If the input voltage applied to an inverter is with these two limits, the manufacturer guarantees that the inverter output will go to the low state. If you observe otherwise, the unit should be replaced as faulty. In order for an inverter input voltage to be recognized as a logic 0, it must be somewhere within the band specified by VIL in Figure 3. The minimum value, VIL, min, is of course 0V dc (GND), and the maximum value, VIL, max to an inverter is within these two limits, the manufacturer guarantees that the inverter output will go to the high state. If you observe otherwise, the unit should be replaced as faulty.


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Equipment and parts required: 1 hex inverter, 74LS06 1 volt-ohm-miliammeter (VOM) 1 oscilloscope, dc-coupled 1 square-wave signal generator, 0 to 5V dc, variable frequency 1. Examine the data sheet for the 74LS06 hex inverter. It is called hex since there are six

inverters. Note carefully the required power-supply voltage VCC and the proper pin connections. Apply power to the 74LS06. Record here the exact device you are using.

2. The simplest method for determining proper operation of an inverter is a static test. This is

performed by simply connecting a clip lead to the inverter input. The other end of the clip lead to the inverter input. The connected to ground (VIN = 0V dc) or + VCC (VIN = +5V dc) while monitoring the output to see if it does indeed provide the complement of the input. Use a clip lead to perform this static test on each of the inverters; monitor the output with a VOM to determine proper operation. Complete the truth table here for one of the inverter tested.

VIN VOUT

0V dc +5V dc

3. Record the value of VOUT when VIN open-circuited = ___________________. 4. To verify that one inverter can indeed drive another, connect two inverters in cascade as

shown in Figure 4. Apply the voltage for V1 as shown in the following table (used a clip lead on the input of INV 1), and record the resulting values for V2 and V3.

V1 V2 V3

0V dc +5V dc

Figure 4

V1 V3 V2

INV 1 INV 2


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Use the oscilloscope to adjust the output of the square-wave generator. The generator output must be adjusted with the low level at 0V dc and the high level at +5V dc. Set the frequency at any convenient value between 1KHz and 100KHz. Display this waveform on one channel of the oscilloscope, and at the same time apply this waveform to the input of an inverter. Display the output of the inverter on the other input channel of the oscilloscope such that the input and output signals can be compared. Draw here the two resulting waveforms. Take care to show amplitudes and time periods for both waveforms. OR Gates An OR gate is designed so that an output signal will occur any time there is an input signal. Since we are discussing digital electronics, it must be clear that the presence of a signal is represented as a logical 1 and the absence of a signal is represented as a logical 0. The symbol for a 2-input OR gate is shown in Figure 5(a); A and B are the 2 inputs and x is the output.

(a)

Input B A

Output, X

0 0 0 0 1 1 1 0 1 1 1 1

(b)

Figure 5 (a) A 2-input OR gate. (b) Truth table It is possible to have either a 0 or a 1 present at input, and since there are 2 inputs to this gate there must be four possible combinations of input signals as shown in Figure 5(b). This table of combinations is known as a truth table.

A

B X = A + B


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The first input-signal combination (A = 0, B = 0) represents no input signal at either A or B, and thus there is no output signal (x = 0). The second combination has an input signal at A but no signal at B (A =1, B = 0), and thus an output signal occurs (x = 1). The third combination has an input signal at B but none at A (A = 0, B = 1), and this must also provide an output signal (x = 1). The final combinations has input signals at both A and B (A = 1, B = 1), which of course provides an output (x = 10). The operation of this OR gate can be summarized by saying an output occurs for an input at either A or B or both. An OR gate can of course have more than 2 inputs, and a truth table having 2N input combinations (count in straight binary) can be constructed for any gate having N inputs. For example, the 3-input OR gate (N = 3) shown in Figure 1-6 has 23 = 8 input combinations.

(a)

C B A X 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

(b)

Figure 6 (a) A 3-input OR gate (b) Truth table

In logic notation, the symbol + means OR. Thus the operation of a 2-input OR gate can be written in logic equation form as x = A + B. Similarly, for a 3-input OR gate, x = A + B + C. take careful notice that these are logic expressions, and the + symbol does not means ordinary addition. The expressions should be read equals A or B or

A B C

X = A + B + C


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AND Gate AND gate is so designed that an output signal will occur only when there are signals at all inputs. The symbol for a 2-input AND gate is shown in Figure 7(a) and the corresponding truth table is given in Figure 7(b). For this AND gate, the last entry in the truth table is the only case where all inputs are 1 (A = 1 and B = 1), and thus this is the only combinations where the output is 1. For this AND gate, one can say an output occurs only for an input signal at both A and B.

(a)

B A X 0 0 0 0 1 0 1 0 0 1 1 1

(b)

Figure 7 (a) A 2-input AND gate (b) Truth table

There are, of course, AND gates with more than 2 inputs, and a truth table having 2N entries for an N-input gate can be constructed. For example, a 3-input AND gate and the appropriate truth table are shown in Figure 8.

(a)

A

B X = AB

C B

A X = ABC


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C B A X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1

(b)

Figure 8 (a) A 3-input AND gate (b) Truth table

The symbol for AND in logic notation is . thus the operation of a 2-input AND gate is written in logic equation form as x = A . B = AB). This statement is not to be confused with ordinary multiplication, and should be read as x = equal A and B. Frequently the . is omitted and the and is understood in the resulting expression (for example, x = A . B = AB). For more than 2 inputs, the expressions becomes x = ABS . Notice that the And gate can be considered as an all-or-nothing gate since there must be a 1 at all inputs to get a 1 at the output. In contrast, the OR gate can be thought of as an any-or-all gate since a 1` at any input will provide a 1 at the output. Positive and Negative Logic Any digital system can be based on positive logic or negative logic. The difference between the two is simply a matter of definition. For positive logic, the 1 is defined as the more positive voltage level, and for negative logic, the 0 is taken as the more positive voltage level. Most commercially available integrated circuits (ICs) use logic levels of +5V dc and 0V dc. Thus, if we define 1 = +5V dc and 0 = 0V dc, we are using positive logic. On the other hand, we can define 1 = 0V dc and 0 = +5V dc if we want a negative-logic representation.


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Equipment and parts required 1 OR gate, 2-input, 74LS32 1 VOM 1. Examine the 74LS32 data sheet, and note carefully the required supply voltage, VCC =

_________ and the maximum supply current required Icc, max = _____________. Apply power to the OR gates. Record here the exact devices you are using. ___________________________________________

2. Use 0 = 0V dc and 1 = +5V dc, record the gate output voltages for each input combination

shown in the following table. (Notice that a 3-input gate will function as a 2-input gate when two of the inputs are connected together as I part 4 of the Self-test.)

Input, V dc Output B A 0 0 0 +5 +5 0 +5 +5

Record the actual measured values for: 0 = VOL = ____________________, and 1 = VOH = _____________________.

3. A 3-input OR gate can be constructed from two 2-input OR gates as shown in Figure 9, and verify the proper operation by applying the input-signal combinations shown and recording the resulting gate output voltages.

(a)

A

B C

X = A + B + C


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C B A X

0V dc 0V dc 0V dc 0V dc 0V dc +5V dc 0V dc +5V dc 0V dc 0V dc +5V dc +5V dc +5V dc 0V dc 0V dc +5V dc 0V dc +5V dc +5V dc +5V dc 0V dc +5V dc +5V dc +5V dc

(b)

Figure 9 (a) Logic diagram (b) Truth table

4. Connect one OR gate as a 1-input unit by wiring all inputs together, and determine the gate

output for each input shown in Figure 10.

(a)

A X 0V dc +5V dc

(b)

Figure 10 (a) Logic diagram (b) Truth table

5. Using 0 = 0V dc and 1 = +5V dc, record the gate output voltages for each input combination

shown in the following tables. The table corresponds to the 3-input AND gate in Figure 9 which is combination of two 2-input AND gates.

A X


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Input, V dc Output

C B A 0 0 0 0 0 +5 0 +5 0 0 +5 +5 +5 0 0 +5 0 +5 +5 +5 0 +5 +5 +5

0 = VOL = _________________________________________ 1 = VOH = _________________________________________ 6. A 4-input AND gate can be constructed by connecting three 2-input AND gate as shown in

Figure 11. Connect three 2-input AND gates as shown in Figure 12 and verify the proper operation by applying the input signal combinations given below and recording the resulting gate output voltages.

Figure 11

Input A 0 +5 0 +5 0 +5 0 +5 0 +5 0 +5 0 +5 0 +5 Input B 0 0 +5 +5 0 0 +5 +5 0 0 +5 +5 0 0 +5 +5 Input C 0 0 0 0 +5 +5 +5 +5 0 0 0 0 +5 +5 +5 +5 Input D 0 0 0 0 0 0 0 0 +5 +5 +5 +5 +5 +5 +5 +5 Output

NOR Gates

A

C B

DX = ABCD


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A popular and widely used digital logic fate is the NOR gate. Its logical properties are essentially equivalent to an OR gate followed by an inverter. A NOR gate can be used to accomplish the OR and the AND operations. A NOR gate is therefore considered to be a universal gate, since any logical operation can be expressed entirely in terms of AND, OR and NOT (inversion) operations. Logical Properties Consider the 2-input OR gate followed by an inverter shown in Figure 12(b). The inverter output, also shown in the truth table, is the complement of A + B; that is, x = A + B. Expressed in words, x equals not A or B. This is the source of the term, NOR and the logic symbol and expression for a NOR gate are shown in Figure 12(c).

(a)

B A A + B X = A + B 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0

(b)

(c)

Figure 12 (a) OR gate and inverter (b) Truth table (c) NOR-gate symbol and expression.

(a)

A

B X = A + B

A + B

A

B X = A + B

A B

C

X = A + B + C


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C B A X = A + B + C 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0

(b)

Figure 13 (a) a 3-input NOR gate (b) Truth table

Note that the symbol is simply an OR gate with an inversion circle on the output. The NOR gate shown in Figure 12(c) is exactly the equivalent of the combination of gates in Figure 12(b) is simply the complement of A + B, and it represents the response of the NOR-gate output to the 4 input combinations of A and B. Two statements are helpful in remembering how a NOR gate works: (1) if either input is 1, the output must be 0; (2) the only time the output is 1 is when both inputs are 0. Examine the truth table in Figure 12(b) until you are comfortable with both these statements. The symbol and truth table for a 3-input NOR gate are shown in Figure 13. Study them carefully and notice that the two statements of operation for the 2-input NOR gate apply equally well for this 3-input gate. In working with NOR gates, care must be taken to state the operation properly. For the 3-input NOR gate, one says x = equals not A or not B or not C. Notice that the bar which signifies inversion is a solid line over the entire expressions A + B + C and not three separate lines. Inverter In Figure 14, a 2-input NOR gate has its 2 inputs connected together. This corresponds to the first and last entries in the truth table in Figure 12(b); there are only 2 possible inputs (0 or 1), and clearly the output is the complement of the input in each case.

Figure 14 NOR gate as in inverter

Thus, a 1-input NOR gate performs exactly the same as a simple inverter. OR Operation

A X = A


90

The two NOR gates in Figure 15 are connected in series, with the first gate performing the 2-input NOR function. The second gate is connected as in inverter, and its output is simply the complement of the first NOR-gate output, or x = A + B = A + B. Clearly the combinations of NOR gates can be used to accomplish the OR operation.

Figure 15 OR operation using NOR gates AND Operation The logic network in Figure 16 consists of a 2-input NOR gate preceded by two NOR gates operating as inverters. Recall the second statement describing the NOR-gate operation; the only time the output is 1 is when both inputs are 0. Now, since the 2 inputs to the NOR gate in Figure 16 (a and b) are complemented, we can describe the operation of this entire network as follows; the only time the output is 1 is when both inputs A and B are 1. But this statement

Figure 16 AND operation using NOR gates

is exactly the same as for a simple AND gate. Thus, the combination of NOR gates in Figure 16 can be used to accomplish the AND operation.

A

B

A + BX = A + B

A

B

A

B

X = AB


91

Gate Loading In the logic networks shown in Figure 15, NOR gates are used to drive other NOR gates, and this brings up the question of gate loading. That is, how many gates can be driven from one gate output? The number of gate inputs that can be connected to the output of a single gate is defined as fanout. For example, a NOR gate with a fanout of 6 can be used to drive 6 NOR-gate inputs; alternatively, 6 NOR gate inputs can be connected to the output of this simply gate. Fanout is a device characteristic and should be determined from the data sheet for each individual gate. Equipment and parts required: 1 NOR gate, 2-input, 74LS02 1 VOM 1. Record here the exact device you are using __________________________. 2. Examine the data sheet for a 74LS02. Note that value of VCC = __________, and the

maximum required supply current ICC = ______________. 3. Apply the power to the 74LS02 and verify proper operation of one of the 3-input gates by

measuring the output voltage level for each of the 8-input signal combinations shown in Figure 17. Use input voltage levels of 0 = 0V dc, 1 = +5V dc, and use the measured output voltage levels to complete the truth table below.

Figure 17

A 0 +5 0 +5 0 +5 0 +5 B 0 0 +5 +5 0 0 +5 +5 C 0 0 0 0 +5 +5 +5 +5 X

4. Connect the 3-input on one of the gates together so it can be used as an inverter. Verify that

the gate operates as an inverter by applying 0V dc, and then +5V dc to the input and recording the corresponding outputs.

A

B

C X

C X


92

Input, V dc 0 +5 Output V dc

5. Determine whether or not a 3-input NOR gate will function as an inverter if 2 of the inputs

are left unconnected and the third is used as the single input.____________________________________________________

6. Connect two of the NOR gates as shown in Figure 15, and complete the truth table below to

verify operation as an OR function.

A 0 +5 0 +5 B 0 0 +5 +5 X

7. Connect three of the NOR gates as shown in Figure 16 and complete the truth table below to

verify operation as an AND function.

A 0 +5 0 +5 B 0 0 +5 +5 X

NAND Gates One of the most popular and widely used digital logic gates is the NAND gate. Its logical properties are essentially equivalent to an AND gate followed by the inverter. A combinations of the NAND gates can be used to accomplish the OR gate and the AND operation. A NAND gate is therefore considered a universal gate, since any logical operation can be expressed entirely in terms of AND, OR, and NOT (inversion) operation. Logical Properties Consider the 2-input AND gate followed by an inverter, as shown in Figure 18a. The AND-gate output AB is shown in the truth table in Figure 18b. The inverter output, also shown in the truth table, is the complement if AB that is X = AB.

(a)

A

B

ABX = AB


93

B A AB X =AB 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0

(b)

(c)

Figure 18 (a) AND gate and inverter. (b) Truth table. (c) NAND-gate symbol and expression. Expressed in words, X = equals not A and B. This is the source of the term NAND, and the logic symbol and expression for a NAND gate are shown in Figure 18c. Note that the symbol is simply and AND gate with an inversion circle on the output. The NAND gate shown in Figure 18c is exactly the equivalent of the combination of gates in Figure 18a. The right-hand column in the truth table in Figure 18b is simply the complement of AB, and it represents the responses of the NAND-gate output to the 4-input combinations of A and B. There are two statements which are helpful in remembering how a NAND gate works: (1) if either input is 0, the output must be 1; (2) the only time the output is 0 is when both inputs are 1. Examine the truth table in Figure 18b until you are comfortable with both of these statements. The symbol and truth table for a 3-input NAND gate are shown in Figure 19. Study them carefully and notice that the two statements of operation for the 2-input NAND gate apply equally well for this 3-input gate. In working with NAND gate, care must be taken to state the operation properly. For the 3-input NAND gate, one say, X equals not A and B and C. It is quite incorrect to say X equals not A and not B and not C. Notice that the bar which signifies inversion is a solid line over the entire expression ABC and not three single lines.

(a)

A

B X = AB

AB

CX


94

C B A X = ABC 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0

Figure 19 (a) A 3-input NAND gate. (b) Truth table.

Inverter In Figure 20, a 2-input NAND gate has its 2 inputs connected together.

Figure 20 NAND gate as an inverter.

This corresponds to the first and last entries in the truth table in Figure 18b; there are only 2 possible inputs (0 or 1), and clearly the output is the complement of the input in each case. Thus, a 1-input NAND gate performs exactly the same function as a simple inverter. AND Operation The two NAND gates in Figure 21 are connected in series, with the first gate performing the 2-input NAND function. The second gate is connected as an inverter, and its output is simply the complement of its input. Thus, X is the complement of the first NAND-gate output, or X = AB = AB. Cl

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