Stop Watch & Digital Watch 구현

Stop Watch & Digital Watch Lecture #14

Team Project - , VHDL Stop Watch Digital Watch VHDL

Stop Watch

Stop Watch Design SpecificationStop Watch VHDL : Clock : 10KHz Key 2 : RESET, START_STOP

: 6 : Com0, Com1, Com2, Com3, Com4, Com5Segment LED 7 : A, B, C, D, E, F, G

Stop Watch Design Specification( Input Device )2 RESET, START_STOP 1 , 0 RESETSTART_STOP

Stop Watch Design Specification(Output Device)6 7 Segment LED .:2, :2, 1/100:2 1/100

Stop Watch Design SpecificationStop Watch (1) POWER ON RESET

- 00 : 00 : 00- START_STOP KEY

00000.00000000

Stop Watch Design Specification(2)

- 00 : 00 : 00 .. 00 : 00 : 99 00 : 01 : 00 .. 00 : 59 : 99 01 : 00 : 00 .. 59 : 59 : 99 00 : 00 : 00 - START_STOP KEY - START_STOP KEY 1/100 - RESET KEY 00:00:00 ,

=59590.99595999

Stop Watch

Stop Watch VHDL Top Diagram

Stop Watch VHDL Top DiagramENP 1 , 0 RESET Key 1 , Nclr Active Low. 6 FND . 6 1 0 1 .A,B,C,D,E,F,G Segment LED 1 LED . 2 , , 1/100 . 100Hz

Stop Watch Top Level Entitylibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity stopwatch is port( clk: in std_logic; reset: in std_logic; start_stop: in std_logic; com0: out std_logic; com1: out std_logic; com2: out std_logic; com3: out std_logic; com4: out std_logic; com5: out std_logic; A : out std_logic; B : out std_logic; C : out std_logic; D : out std_logic; E : out std_logic; F : out std_logic; G : out std_logic );end stopwatch;

Stop Watch Top Level Entityarchitecture a of stopwatch iscomponent Hz100ctrl port( clk,nclr : in std_logic; Hz100 : out std_logic);end component;component keyif port( start_stop: in std_logic; clk, nclr: in std_logic; enp: out std_logic);end component;component timecontrol port( clk, nclr : in std_logic; enp: in std_logic; SSL : out std_logic_vector(3 downto 0); SSH : out std_logic_vector(3 downto 0); SECL: out std_logic_vector(3 downto 0); SECH: out std_logic_vector(3 downto 0); MINL: out std_logic_vector(3 downto 0); MINH: out std_logic_vector(3 downto 0));end component;component outputif port( clk, nclr : in std_logic; SSL : in std_logic_vector(3 downto 0); SSH : in std_logic_vector(3 downto 0); SEC: in std_logic_vector(3 downto 0); SECH: in std_logic_vector(3 downto 0); MINL: in std_logic_vector(3 downto 0); MINH : in std_logic_vector(3 downto 0); com_out: out std_logic_vector(5 downto 0); seg_out: out std_logic_vector(6 downto 0));end component;

Stop Watch Top Level Entitysignal nclr : std_logic;signal Hz100 : std_logic;signal enp: std_logic;signal SSL : std_logic_vector(3 downto 0);signal SSH : std_logic_vector(3 downto 0);signal SECL : std_logic_vector(3 downto 0);signal SECH : std_logic_vector(3 downto 0);signal MINL : std_logic_vector(3 downto 0);signal MINH : std_logic_vector(3 downto 0);signal com_out: std_logic_vector(5 downto 0);signal seg_out: std_logic_vector(6 downto 0);begin

nclr

Stop Watch 100Hz Gen.10KHz Clock(=clk) 1/100 100Hz(=Hz100) 100Hz 1/100 Stop Watch 1/100 . TimeControl KeyIF 10KHz:100Hz=100:1 10KHz 100 100Hz 1 . 10KHz

Stop Watch 100Hz Gen.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity Hz100ctrl is port( clk,nclr : in std_logic; Hz100 : out std_logic);end Hz100ctrl;architecture a of Hz100ctrl issignal cnt : std_logic_vector(5 downto 0);signal sHz100 : std_logic;beginprocess(nclr,clk)beginif( nclr='0') thencnt

Stop Watch Key InterfaceStart_Stop Stop Watch / ENP ENP 1/100 Hz100 Shift Register 100Hz ENP 1 , 0 Clk Clk Start_Stop 1 , StartStop

Stop Watch Key Interfacelibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity keyif is port( start_stop : in std_logic;clk,nclr : in std_logic; enp: out std_logic);end keyif;architecture a of keyif issignal q : std_logic_vector( 1 downto 0);signal RisingShotPules : std_logic; signal s_enp: std_logic;Begin

process(nclr,clk) -- shift register 2bits :beginif( nclr='0') thenq

Stop Watch Key Interface

-- enp generationprocess(nclr,clk)beginif( nclr='0') thens_enp

Stop Watch Time Control ENP 0 , 1 00:00:00 .. 00:00:99 00:01:00 .. 00:59:99 01:00:00 .. 59:59:99 00:00:00 5900 00 00590.99ENP 1 , 0 100Hz

Stop Watch Time Controllibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity timecontrol is port( clk,nclr : in std_logic; enp: in std_logic; SSL : out std_logic_vector(3 downto 0); SSH : out std_logic_vector(3 downto 0); SECL : out std_logic_vector(3 downto 0); SECH : out std_logic_vector(3 downto 0); MINL : out std_logic_vector(3 downto 0); MINH : out std_logic_vector(3 downto 0));end timecontrol;architecture a of timecontrol issignal s_SSL : std_logic_vector(3 downto 0);signal s_SSH : std_logic_vector(3 downto 0);signal s_SECL : std_logic_vector(3 downto 0);signal s_SECH : std_logic_vector(2 downto 0);signal s_MINL : std_logic_vector(3 downto 0);signal s_MINH : std_logic_vector(2 downto 0);begin Counter ENP=1 . 1/00

Stop Watch Time Controls_SSL_cnt: process(nclr,clk)beginif( nclr='0') thens_SSL

Stop Watch Time Controls_SECL_cnt: process(nclr,clk)beginif( nclr='0') thens_SECL

Stop Watch Time Controls_MINL_cnt: process(nclr,clk)beginif( nclr='0') then s_MINL

Stop Watch Output Interface, , 1/100 6 7 Segment LED a,b,c,d,e,f,g 6 7 Segment LED 6 6 7 Segment LED BCD-7 Segment Decoder 1 2 3 4 9 0 112340.90BCD-7 Segment Decoder 6 1 0 1 High FND Low FND

Stop Watch Output Interfacelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity outputif is port( clk,nclr : in std_logic; SSL : in std_logic_vector(3 downto 0); SSH : in std_logic_vector(3 downto 0); SECL : in std_logic_vector(3 downto 0); SECH: in std_logic_vector(3 downto 0); MINL: in std_logic_vector(3 downto 0); MINH: in std_logic_vector(3 downto 0); com_out: out std_logic_vector(5 downto 0); seg_out: out std_logic_vector(6 downto 0));end outputif;architecture a of outputif issignal muxout : std_logic_vector(3 downto 0);signal cnt : std_logic_vector(2 downto 0);begin

-- modulo 6 counterprocess(nclr,clk)beginif( nclr='0') thencnt

Stop Watch Output Interface

-- com signal gen : 3X8 decoder process(cnt)begincase cnt iswhen "000" => com_out com_out com_out com_out com_out com_out com_out muxout muxout muxout muxout muxout muxout

Stop Watch Output Interface

-- BCD to 7 Segment gen process(muxout) begincase muxout iswhen "0000" => seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out seg_out

Digital Watch

Digital Watch Design SpecificationVHDL : Clock : 10KHz Key 3 : RESET SW, SET SW, INC SW

:LCD Interface : E, RS, RW, D0, D1, D2, D3, D4, D5, D6, D7

Digital Watch Design Specification( Input Device ) 3 RESET SW, SET SW, INC SW 1 , 0

Digital Watch Design Specification (Output Device) Character LCD 20 2

D.D.RAM

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Digital Watch Design SpecificationDigital Watch

(1) POWER ON RESET ( = Initial_State )

- AM 12 : 00 - AM 12 00 0.5 - SET KEY TIME AM/PM SETTING MODE

DIGITALWATCHTIME:AM12:00

Digital Watch Design Specification(2) TIME AM/PM SETTING MODE ( = Time_AmPm_Set_State )

- AM/PM LED 0.5 DISPLAY ON - INC KEY AM/PM - SET KEY TIME HOUR SETTING MODE TIME HOUR SETTING MODE ( = Time_Hour_Set_State )

- HOUR LED 0.5 - INC KEY 1 12 1 2 3 4 5 6 7 8 9 10 11 12 .. - SET KEY TIME MIN HIGH SETTING MODE Set Key Inc Key 2 Key .=> .

DIGITALWATCHTIME:AM12:00

DIGITALWATCHTIME:PM12:00

Digital Watch Design Specification(2)

TIME MIN HIGH SETTING MODE ( = Time_Min_High_Set_State )

- HIGH LED 0.5 - INC KEY 1 0 1 2 3 4 5 0 .. - SET KEY TIME MIN LOW SETTING MODE

TIME MIN LOW SETTING MODE ( = Time_Min_Low_Set_State )

- LOW LED 0.5 - INC KEY 1 0 1 2 3 4 5 0 .. - SET KEY NORMAL TIME MODE



Digital Watch Design Specification (3) NORMAL TIME MODE ( = Normal_Time_State )

- - SET KEY TIME AM/PM SETTING MODE

DIGITALWATCHTIME:PM2:35:00

Digital Watch VHDL .CharacterLCD.LCD .

Digital Watch Top Level

Digital Watch Top Level Digital Watch FND Interface .LCD Interface BCD -> ASCII

Digital Watch Top Level Entity (1)-- purpose : clock top block-- ver 2 : LCD interfaceLIBRARY IEEE;USE IEEE.std_logic_1164.all;

entity clocklcd isport( clk : in std_logic; reset_sw: in std_logic; set_sw : in std_logic;inc_sw : in std_logic; --;e: out std_logic;rw: out std_logic;rs: out std_logic;data: out std_logic_vector(7 downto 0));end clocklcd;

Architecture a of clocklcd issignal set_button, inc_button : std_logic;signal set_shot, inc_shot : std_logic;signal reset, Hz100 : std_logic;signal state : std_logic_vector(3 downto 0);signal time_set_mode : std_logic;

-- time counters for 7 segmentsignal time_ampm : std_logic;signal time_hour_high : std_logic;signal time_hour_low : std_logic_vector(3 downto 0);signal time_min_high : std_logic_vector(2 downto 0);signal time_min_low : std_logic_vector(3 downto 0);signal time_sec_high : std_logic_vector(2 downto 0);signal time_sec_low : std_logic_vector(3 downto 0);signal led_blink : std_logic;signal buzzer_blink : std_logic; -- for 0.5 sec buzer blink

Digital Watch Top Level Entity (2)signal initial_state: std_logic;signaltime_ampm_set_state: std_logic;signaltime_hour_set_state: std_logic;signaltime_min_high_set_state: std_logic;signaltime_min_low_set_state: std_logic;signalnormal_time_state: std_logic;

signals_select_hour_high: std_logic; -- for hour_high=0 : display Off;

signal LCD_time_ampm_ap : std_logic_vector(7 downto 0);signal LCD_time_ampm_m : std_logic_vector(7 downto 0);signal LCD_time_hour_high : std_logic_vector(7 downto 0);signal LCD_time_hour_low : std_logic_vector(7 downto 0);signal LCD_time_min_high : std_logic_vector(7 downto 0);signal LCD_time_min_low : std_logic_vector(7 downto 0);signal LCD_time_sec_high : std_logic_vector(7 downto 0);signal LCD_time_sec_low : std_logic_vector(7 downto 0);signal LCD_time_sec_colon : std_logic_vector(7 downto 0);

component statemachine port ( clk : in std_logic; reset : in std_logic; set_shot : in std_logic;initial_state: out std_logic;time_ampm_set_state: out std_logic;time_hour_set_state: out std_logic;time_min_high_set_state: out std_logic;time_min_low_set_state: out std_logic;normal_time_state: out std_logic; time_set_mode : out std_logic);end component;

Digital Watch Top Level Entity (3)component timecount port( clk : in std_logic; reset : in std_logic; inc_shot : in std_logic; set_shot : in std_logic;initial_state: in std_logic;time_ampm_set_state: in std_logic;time_hour_set_state: in std_logic;time_min_high_set_state: in std_logic;time_min_low_set_state: in std_logic;normal_time_state: in std_logic; -- time counters for 7 segment time_ampm : buffer std_logic; time_hour_high : buffer std_logic; time_hour_low : buffer std_logic_vector(3 downto 0); time_min_high : buffer std_logic_vector(2 downto 0); time_min_low : buffer std_logic_vector(3 downto 0); time_sec_high : buffer std_logic_vector(2 downto 0); time_sec_low : buffer std_logic_vector(3 downto 0); buzzer_blink : buffer std_logic -- for 0.5 sec buzer blink);end component;

component ledblink port( clk : in std_logic; reset : in std_logic; set_shot : in std_logic; inc_shot : in std_logic;initial_state : in std_logic;time_set_mode: in std_logic; led_blink : buffer std_logic);end component;

Digital Watch Top Level Entity (4)component LCD_IF port(clk : in std_logic; -- 10KHz : 0.1msec = 100usecresetb: in std_logic; -- LCD input : time informationLCD_time_ampm_ap : in std_logic_vector(7 downto 0);LCD_time_ampm_m : in std_logic_vector(7 downto 0);LCD_time_hour_high : in std_logic_vector(7 downto 0);LCD_time_hour_low : in std_logic_vector(7 downto 0);LCD_time_min_high : in std_logic_vector(7 downto 0);LCD_time_min_low : in std_logic_vector(7 downto 0);LCD_time_sec_high : in std_logic_vector(7 downto 0);LCD_time_sec_low : in std_logic_vector(7 downto 0); LCD_time_sec_colon : in std_logic_vector(7 downto 0);e: out std_logic;rw: out std_logic;rs: out std_logic;data: out std_logic_vector(7 downto 0));end component;

component Hz100ctrl port( clk,nclr : in std_logic; Hz100 : out std_logic);end component;

component shotpulse port( clk: in std_logic; reset : in std_logic; d : in std_logic; rising_shot : out std_logic);end component;

Digital Watch Top Level Entity (5)component ToLCDBlink port(initial_state: in std_logic;time_ampm_set_state: in std_logic;time_hour_set_state: in std_logic;time_min_high_set_state: in std_logic;time_min_low_set_state: in std_logic;normal_time_state: in std_logic; led_blink : in std_logic;

-- time clock time_ampm : in std_logic; time_hour_high : in std_logic; time_hour_low : in std_logic_vector(3 downto 0); time_min_high : in std_logic_vector(2 downto 0); time_min_low : in std_logic_vector(3 downto 0); time_sec_high : in std_logic_vector(2 downto 0); time_sec_low : in std_logic_vector(3 downto 0);

-- LCD input : time information LCD_time_ampm_ap : out std_logic_vector(7 downto 0); LCD_time_ampm_m : out std_logic_vector(7 downto 0); LCD_time_hour_high : out std_logic_vector(7 downto 0); LCD_time_hour_low : out std_logic_vector(7 downto 0); LCD_time_min_high : out std_logic_vector(7 downto 0); LCD_time_min_low : out std_logic_vector(7 downto 0); LCD_time_sec_high : out std_logic_vector(7 downto 0); LCD_time_sec_low : out std_logic_vector(7 downto 0);

LCD_time_sec_colon : out std_logic_vector(7 downto 0));end component;

Digital Watch Top Level Entity (6)beginU1: statemachine port map( Hz100, reset, set_shot, initial_state, time_ampm_set_state, time_hour_set_state,time_min_high_set_state, time_min_low_set_state, normal_time_state, time_set_mode);

U2: timecount port map( Hz100, reset, inc_shot, set_shot, initial_state, time_ampm_set_state, time_hour_set_state, time_min_high_set_state, time_min_low_set_state, normal_time_state, time_ampm, time_hour_high, time_hour_low, time_min_high, time_min_low, time_sec_high, time_sec_low, buzzer_blink );

U3: ledblink port map( Hz100, reset, set_shot, inc_shot, initial_state, time_set_mode, led_blink);

U4 :Hz100ctrl port map( clk,reset,Hz100);

U5: shotpulse port map( Hz100, reset, set_button, set_shot );U6: shotpulse port map( Hz100, reset, inc_button, inc_shot );

reset

Digital Watch - Shot Pulse Gen.100Hz Clk Clk 1 100Hz 1 1 100Hz Shot Pulse

Digital Watch - Shot Pulse Gen.-- purpose : rising shot pulse generatorLIBRARY IEEE;USE IEEE.std_logic_1164.all;

entity shotpulse isport( clk : in std_logic; reset : in std_logic; d : in std_logic; rising_shot : out std_logic);end shotpulse;

architecture a of shotpulse issignal qa,qb : std_logic;beginprocess(clk,reset)begin if(reset='0') then qa

Digital Watch - 100Hz Gen.10KHz Clock(=clk) 1/100 100Hz(=Hz100) 100Hz 1/100 Stop Watch 1/100 . TimeControl KeyIF 10KHz:100Hz=100:1 10KHz 100 100Hz 1 . 10KHz

Digital Watch - 100Hz Gen.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity Hz100ctrl is port( clk, nclr : in std_logic; Hz100 : out std_logic);end Hz100ctrl;architecture a of Hz100ctrl issignal cnt : std_logic_vector(5 downto 0);signal sHz100 : std_logic;Begin

process(nclr,clk)beginif( nclr='0') thencnt

Digital Watch - Mode Control(Flow)S0S1S2S3S41111100000 : S0 .Set_Shot 1 , 0 . S4 Set_Shot 1 , S5 . S5 Set_Shot 1 S1 AM/PM .S510Input : Set_Shot Set_Shot Set Key 1 1 Shot Pulse . 6 .S0 : Initial StateS1 : AM/PM Setting StateS2 : Hour Setting StateS3 : Minute High Setting StateS4 : Minute Low Setting StateS5 : Normal Time State S1, S2, S3, S4 Mode.

Digital Watch - Mode Control(Flow)-- purpose : mode control. ver2LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.all;entity statemachine isport( clk : in std_logic; reset : in std_logic; set_shot : in std_logic;

initial_state: out std_logic; time_ampm_set_state: out std_logic; time_hour_set_state: out std_logic; time_min_high_set_state: out std_logic; time_min_low_set_state: out std_logic; normal_time_state: out std_logic;

time_set_mode : out std_logic);end statemachine;

architecture a of statemachine issignal cnt : std_logic_vector(2 downto 0);signal decout : std_logic_vector(5 downto 0);begin: Time_set_mode 1 .

Digital Watch - Mode Control(Flow)process(clk,reset)begin if(reset='0') then cnt

Digital Watch - Mode Control(Flow)initial_state

Digital Watch - Time Control FlowAM/PMHour 10 1912509

Digital Watch - Time Control Flow1= time_Cnt=25 & Buzzer_Blink=1959595995995959125959115959

Digital Watch - Time Control-- purpose : time counter control(revised 3)LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;entity timecount isport( clk : in std_logic; reset : in std_logic; inc_shot : in std_logic; set_shot : in std_logic;initial_state: in std_logic;time_ampm_set_state: in std_logic;time_hour_set_state: in std_logic;time_min_high_set_state: in std_logic;time_min_low_set_state: in std_logic; normal_time_state: in std_logic;

-- time counters for 7 segment time_ampm : buffer std_logic; time_hour_high : buffer std_logic; time_hour_low : buffer std_logic_vector(3 downto 0); time_min_high : buffer std_logic_vector(2 downto 0); time_min_low : buffer std_logic_vector(3 downto 0); time_sec_high : buffer std_logic_vector(2 downto 0); time_sec_low : buffer std_logic_vector(3 downto 0); buzzer_blink : buffer std_logic -- for 0.5 sec buzer blink);end timecount;

Digital Watch - Time Controlarchitecture a of timecount isCONSTANT AM : std_logic := '0';CONSTANT PM : std_logic := '1';signal time_cnt : std_logic_vector(5 downto 0); -- for 0.5 sec countsignal sec_high5,sec_low9 : std_logic;signal min_high5,min_low9 : std_logic;signal hour_high1,hour_low1,hour_low2,hour_low9 : std_logic;signal sec_59 : std_logic;signal min_sec_959 : std_logic;signal min_sec_5959 : std_logic;signal hour_min_sec_95959 : std_logic;signal hour_min_sec_115959 : std_logic;signal hour_min_sec_125959 : std_logic;signal hour_12 : std_logic;signal one_sec : std_logic;beginsec_high5

Digital Watch - Time Controlprocess(clk, reset)begin if(reset='0') then time_ampm

Digital Watch - Time Controlprocess(clk, reset)begin if(reset='0') then time_hour_low

Digital Watch - Time Controlprocess(clk, reset)begin if(reset='0') then time_min_low

Digital Watch - Time Controlprocess(clk, reset)begin if(reset='0') then time_sec_low

Digital Watch - Time Controlprocess(clk,reset)beginif(reset='0') then buzzer_blink

Digital Watch LedBlink (Flow) FND Display .1. (Initial_State) Set Key , Set Key 0.5 FND Display ON 0.5 Display OFF . 2. (Time_Set_Mode) Set Key Inc Key 2 Key Display On 0.5 Display ON 0.5 Display OFF .3. Led_blink_cnt 30(Half_CnT) .4. Led_blink 1 Display ON, 0 Display OFF .

Digital Watch - LedBlink-- purpose : led blink controlLIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;

entity ledblink isport( clk : in std_logic; reset : in std_logic; set_shot : in std_logic; inc_shot : in std_logic;initial_state : in std_logic;time_set_mode: in std_logic; led_blink : buffer std_logic);end ledblink;

architecture a of ledblink issignal led_blink_cnt : std_logic_vector(5 downto 0);begin

Digital Watch - LedBlink

-- 0.5 sec led blink controlprocess(clk,reset)beginif(reset='0') then led_blink_cnt

Digital Watch - LedBlink

process(clk,reset)begin if(reset='0') then led_blink

Digital Watch LCD_IFlibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;use work.myLCD.all;

entity LCD_IF isport(clk : in std_logic; -- 10KHz : 0.1msec = 100usecresetb: in std_logic; -- LCD input : time information LCD_time_ampm_ap : in std_logic_vector(7 downto 0); LCD_time_ampm_m : in std_logic_vector(7 downto 0); LCD_time_hour_high : in std_logic_vector(7 downto 0); LCD_time_hour_low : in std_logic_vector(7 downto 0); LCD_time_min_high : in std_logic_vector(7 downto 0); LCD_time_min_low : in std_logic_vector(7 downto 0); LCD_time_sec_high : in std_logic_vector(7 downto 0); LCD_time_sec_low : in std_logic_vector(7 downto 0); LCD_time_sec_colon : in std_logic_vector(7 downto 0);e: out std_logic;rw: out std_logic;rs: out std_logic;data: out std_logic_vector(7 downto 0));end LCD_IF;

architecture hb of LCD_IF issignal dsp_data: std_logic_vector(7 downto 0);signal clk2 : std_logic; -- 5KHz : 0.2msec = 200usecsignal Fclk2 : std_logic; -- 5KHz : 0.2msec = 200usecsignal LCD_mode : std_logic_vector(3 downto 0);signal cnt5 : std_logic_vector(4 downto 0); -- modulo 21 countersignal Func_Set_shot : std_logic; signal Normal_Mode : std_logic;signal Write_shot: std_logic;signal Line : std_logic_vector(1 downto 0); -- 2 bits counterbegin

clk=100usASCII Code LCD

Digital Watch LCD_IFprocess(clk, resetb) -- modulo 2 counter gen.beginif(resetb='0') thenclk2

Digital Watch LCD_IFprocess(clk2, resetb) -- LCD Mode Allocationbeginif(resetb='0') thenLCD_mode

Digital Watch LCD_IF-- Write_Shot gen.process(Normal_Mode, cnt5)beginif(cnt5 = "00000" and Normal_Mode ='1') thenWrite_Shot

Digital Watch LCD_IFprocess(clk)beginif( Line = "00") then case cnt5 iswhen "00000" =>dsp_datadsp_data dsp_data dsp_data dsp_data dsp_data dsp_datadsp_datadsp_datadsp_datadsp_datadsp_datadsp_datadsp_data

Digital Watch LCD_IFcase cnt5 iswhen "00000" =>dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data dsp_data

Digital Watch LCD_IF Timing16.8ms16.8ms16.8ms16.8ms16.8ms16.8ms16.8ms16.8ms16.8msec rs, e Function Set.7 LCD .Function SettingFunction SettingFunction SettingFunction SettingDisplay ClearEntry Mode SettingDisplayOn/Off settingDD Ram Addr = 00H

Digital Watch LCD_IF TimingCnt5 Modulo 21 CounterLine Cnt5 20

Digital Watch LCD_IF TimingLine cnt5=20 Line=3 0 LCD_Mode Line=3, cnt5=20

Digital Watch LCD_IF TimingLCD_Mode Line=3, cnt5=20 4x21=84(clkx2)84x0.2msec=16.8.msec 16.8msec rs, e .0.5 clk = 0.5 x 0.1msec=0.05msec=50usec50usec50usec100usecLCD Setup Time, Hold Time .

Digital Watch LCD_IF Timing 20 .DD Ram Addr = 00H

Digital Watch LCD_IF Timing1 : 00111100Function Setting

Digital Watch LCD_IF Timing5 : 00000001Display Clear

Digital Watch LCD_IF Timing6 : 0000110Entry Mode Setting

Digital Watch LCD_IF Timing7 : 00001100Display On/Off setting

Digital Watch LCD_IF Timing8 : 10000000DD Ram Addr = 00H 1-3 lcd : SPACE 4 lcd : D 4 lcd : I

Digital Watch ToLCDBlinkLibrary IEEE;use ieee.std_logic_1164.all;use work.myLCD.all;entity ToLCDBlink isport(initial_state: in std_logic;time_ampm_set_state: in std_logic;time_hour_set_state: in std_logic;time_min_high_set_state: in std_logic;time_min_low_set_state: in std_logic;normal_time_state: in std_logic; led_blink : in std_logic;

-- time clock time_ampm : in std_logic; time_hour_high : in std_logic; time_hour_low : in std_logic_vector(3 downto 0); time_min_high : in std_logic_vector(2 downto 0); time_min_low : in std_logic_vector(3 downto 0); time_sec_high : in std_logic_vector(2 downto 0); time_sec_low : in std_logic_vector(3 downto 0);

-- LCD input : time information LCD_time_ampm_ap : out std_logic_vector(7 downto 0); LCD_time_ampm_m : out std_logic_vector(7 downto 0); LCD_time_hour_high : out std_logic_vector(7 downto 0); LCD_time_hour_low : out std_logic_vector(7 downto 0); LCD_time_min_high : out std_logic_vector(7 downto 0); LCD_time_min_low : out std_logic_vector(7 downto 0); LCD_time_sec_high : out std_logic_vector(7 downto 0); LCD_time_sec_low : out std_logic_vector(7 downto 0);

LCD_time_sec_colon : out std_logic_vector(7 downto 0));end ToLCDBlink;

BCDASCII Led_blink=0 (State)

Digital Watch ToLCDBlinkArchitecture a of ToLCDBlink isbeginprocess( initial_state, time_ampm_set_state, time_hour_set_state, time_min_high_set_state, time_min_low_set_state, normal_time_state, led_blink)beginif( (initial_state or time_ampm_set_state or time_hour_set_state or time_min_high_set_state or time_min_low_set_state)='1' ) then LCD_time_sec_colon

Digital Watch ToLCDBlinkif( (initial_state='1' or time_min_high_set_state='1' ) and led_blink='0') thenLCD_time_min_high

Digital Watch myLCD(Package)-- LCD Library Header File : myLCD.vhdlibrary ieee; use ieee.std_logic_1164.all;

package myLCD isCONSTANT Ascii_space : std_logic_vector(7 downto 0) := "00100000"; -- 20CONSTANT Ascii_colon : std_logic_vector(7 downto 0) := "00111010"; -- 3aCONSTANT Ascii_semicolon : std_logic_vector(7 downto 0) := "00111011"; -- 3bCONSTANT Ascii_0 : std_logic_vector(7 downto 0) := "00110000"; -- 30CONSTANT Ascii_1 : std_logic_vector(7 downto 0) := "00110001";CONSTANT Ascii_2 : std_logic_vector(7 downto 0) := "00110010";CONSTANT Ascii_3 : std_logic_vector(7 downto 0) := "00110011";CONSTANT Ascii_4 : std_logic_vector(7 downto 0) := "00110100";CONSTANT Ascii_5 : std_logic_vector(7 downto 0) := "00110101";CONSTANT Ascii_6 : std_logic_vector(7 downto 0) := "00110110";CONSTANT Ascii_7 : std_logic_vector(7 downto 0) := "00110111";CONSTANT Ascii_8 : std_logic_vector(7 downto 0) := "00111000";CONSTANT Ascii_9 : std_logic_vector(7 downto 0) := "00111001"; -- 39CONSTANT Ascii_A : std_logic_vector(7 downto 0) := "01000001"; -- 41CONSTANT Ascii_B : std_logic_vector(7 downto 0) := "01000010";CONSTANT Ascii_C : std_logic_vector(7 downto 0) := "01000011";CONSTANT Ascii_D : std_logic_vector(7 downto 0) := "01000100";CONSTANT Ascii_E : std_logic_vector(7 downto 0) := "01000101";CONSTANT Ascii_F : std_logic_vector(7 downto 0) := "01000110";CONSTANT Ascii_G : std_logic_vector(7 downto 0) := "01000111";CONSTANT Ascii_H : std_logic_vector(7 downto 0) := "01001000";CONSTANT Ascii_I : std_logic_vector(7 downto 0) := "01001001";CONSTANT Ascii_J : std_logic_vector(7 downto 0) := "01001010";CONSTANT Ascii_K : std_logic_vector(7 downto 0) := "01001011";CONSTANT Ascii_L : std_logic_vector(7 downto 0) := "01001100";CONSTANT Ascii_M : std_logic_vector(7 downto 0) := "01001101";CONSTANT Ascii_N : std_logic_vector(7 downto 0) := "01001110";CONSTANT Ascii_O : std_logic_vector(7 downto 0) := "01001111";CONSTANT Ascii_P : std_logic_vector(7 downto 0) := "01010000";CONSTANT Ascii_Q : std_logic_vector(7 downto 0) := "01010001";CONSTANT Ascii_R : std_logic_vector(7 downto 0) := "01010010";CONSTANT Ascii_S : std_logic_vector(7 downto 0) := "01010011";CONSTANT Ascii_T : std_logic_vector(7 downto 0) := "01010100";CONSTANT Ascii_U : std_logic_vector(7 downto 0) := "01010101";CONSTANT Ascii_V : std_logic_vector(7 downto 0) := "01010110";CONSTANT Ascii_W : std_logic_vector(7 downto 0) := "01010111";CONSTANT Ascii_X : std_logic_vector(7 downto 0) := "01011000";CONSTANT Ascii_Y : std_logic_vector(7 downto 0) := "01011001";CONSTANT Ascii_Z : std_logic_vector(7 downto 0) := "01011010"; -- 5aCONSTANT Ascii_small_a : std_logic_vector(7 downto 0) := "01100001"; -- 61CONSTANT Ascii_small_b : std_logic_vector(7 downto 0) := "01100010";CONSTANT Ascii_small_c : std_logic_vector(7 downto 0) := "01100011";CONSTANT Ascii_small_d : std_logic_vector(7 downto 0) := "01100100";

ASCII Code

Digital Watch myLCD(Package)CONSTANT Ascii_small_e : std_logic_vector(7 downto 0) := "01100101";CONSTANT Ascii_small_f : std_logic_vector(7 downto 0) := "01100110";CONSTANT Ascii_small_g : std_logic_vector(7 downto 0) := "01100111";CONSTANT Ascii_small_h : std_logic_vector(7 downto 0) := "01101000";CONSTANT Ascii_small_i : std_logic_vector(7 downto 0) := "01101001";CONSTANT Ascii_small_j : std_logic_vector(7 downto 0) := "01101010";CONSTANT Ascii_small_k : std_logic_vector(7 downto 0) := "01101011";CONSTANT Ascii_small_l : std_logic_vector(7 downto 0) := "01101100";CONSTANT Ascii_small_m: std_logic_vector(7 downto 0) := "01101101";CONSTANT Ascii_small_n : std_logic_vector(7 downto 0) := "01101110";CONSTANT Ascii_small_o : std_logic_vector(7 downto 0) := "01101111";CONSTANT Ascii_small_p : std_logic_vector(7 downto 0) := "01110000";CONSTANT Ascii_small_q : std_logic_vector(7 downto 0) := "01110001";CONSTANT Ascii_small_r : std_logic_vector(7 downto 0) := "01110010";CONSTANT Ascii_small_s : std_logic_vector(7 downto 0) := "01110011";CONSTANT Ascii_small_t : std_logic_vector(7 downto 0) := "01110100";CONSTANT Ascii_small_u : std_logic_vector(7 downto 0) := "01110101";CONSTANT Ascii_small_v : std_logic_vector(7 downto 0) := "01110110";CONSTANT Ascii_small_w : std_logic_vector(7 downto 0) := "01110111";CONSTANT Ascii_small_x : std_logic_vector(7 downto 0) := "01111000";CONSTANT Ascii_small_y : std_logic_vector(7 downto 0) := "01111001";CONSTANT Ascii_small_z : std_logic_vector(7 downto 0) := "01111010"; -- 7a

-- Hex to Ascii decoderfunction HexToAscii(hex_in : std_logic_vector(3 downto 0)) return std_logic_vector ;end myLCD;

package body myLCD is-- Hex to Ascii decoderfunction HexToAscii(hex_in : std_logic_vector(3 downto 0)) return std_logic_vector isvariable Ascii_out : std_logic_vector(7 downto 0);begin case hex_in iswhen "0000" => Ascii_out := Ascii_0;when "0001" => Ascii_out := Ascii_1;when "0010" => Ascii_out := Ascii_2;when "0011" => Ascii_out := Ascii_3;when "0100" => Ascii_out := Ascii_4;when "0101" => Ascii_out := Ascii_5;when "0110" => Ascii_out := Ascii_6;when "0111" => Ascii_out := Ascii_7;when "1000" => Ascii_out := Ascii_8;when "1001" => Ascii_out := Ascii_9;when others => Ascii_out := Ascii_space; end case; return (Ascii_out);end HexToAscii;end myLCD;ASCII Code BCD to ASCII Code

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