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Statistical Analysis and Modeling for Error Composition in Approximate

Computation Circuits

Wei-Ting Jonas Chan1, Andrew B. Kahng1, Seokhyeong Kang1, Rakesh Kumar2, and John Sartori3

1VLSI CAD LABORATORY, UC San Diego2PASSAT GROUP, Univ. of Illinois

3Univ. of Minnesota

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Threats to traditional IC design approach ...Extreme variations / Reliability issues / Cost:

Approximate Computation:Relaxing the requirement of correctness can dramatically reduce costs of the design

Why Approximate Computation? Threats to traditional IC design approach ...

Extreme variations: PVT variation uncertainty leads to design overheadReliability issues: Hard errors (NBTI, latchup), Soft errors (α-particle)Cost: Cost (power/performance) of perfect accuracy is too high!

Approximate ComputationRelaxing the requirement of correctness can dramatically reduce costs of the design

What is the square root of 10 ?

“a little more than three”

“3.162278....”

Approximation could be faster and more powerful

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Reduce Design Cost with Approximations

Simplified critical paths but with errors

Accurate hardware

Approximate hardware

Approach: insert approximate hardware modules on critical paths

What is the output quality of this circuit?

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Building Blocks: Approximate Hardware Modules

Zhu et al. TVLSI 2010 ETAI : accurate part + inaccurate part Reduce error size Error rate is high

ETAIIM : limited carry-chain run-length Extra protection hardware Reduce error rate and significance

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(c)~(f) have 50% power of accurate adder (b), BUT……

Result Quality Estimation of Approximate Computation

Image smoothing(Addition operations executed by different approximate adders)(a) Original image(b) Accurate adder(c) ACA(d) ETAI(e) ETAII(f) LU

(a) (b) (c)

(d) (e) (f)

How can system designers estimate result quality metrics for circuits containing approximate adders?

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Problem: Result Quality Estimation

Correct results Approximate results

Arithmetic hardware replacement

Accurate hardware

Approximate

hardware

Given: Input statistical propertiesHardware configurationsTopologies of circuits

Output:Estimated error metrics

Goal: quantify degradation of result accuracy after approximate hardware modules are inserted

How to compose errors at circuit level?Solution from this work:

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Outline Related Work Problem Modeling and Proposed Approaches Results and Conclusions

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Related Work

[HuangLR12] Propagates error metrics Improves estimation accuracy and

runtime

Our work

Category Gate level RoundingApproxima

te Arithmetic

VDD scaling

Manipulated Elements Logic cell Arithmetic Arithmetic Multiple Levels

Error Source Appx. HW Rounding Appx. HW Over-scaled VDD

Probabilistic Errors N N N Y

Intensively characterize error distributions over different intervals

Propagate distributions with interval arithmetic

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Related Work [HuangLR12] Intensively characterize error distributions over different intervals Single intervals represent multiple values in log scale

quantization inaccuracy

Positive ErrorsNegative Errors

abs(log(Probability))

PDF PMF

2min, 2max-2max, -2min

If the inputs are out of range, there will be extra inaccuracy

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Related Work [HuangLR12] Source of estimation inaccuracy: quantization errors from

interval representation Accuracy does not scale with characterization runtime

10 100 1000 100001000000.10

1.00

10.00

0.23 0.260.39

1.78

Sample Size (K)

Tot

al C

hara

cter

iza-

tion

Run

time

(hr)

For better accuracy, alternative approach is required

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Error Metrics for Quality Estimation

• Error rate (ER): measures the frequency of error occurrences

• Error significance (ES): measures the magnitude of errors• Average relative error significance (ARES): measures the ratio

between error magnitude and signal magnitude

• Mean square error (MSE): common metric in signal processing • Signal to Noise Ratio (SNR): common metric for quality of

image processing

• Max error (MAXE): measure the upper bound of errors

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Outline Related Work Problem Modeling and Proposed Approaches Results and Conclusions

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Our Quality Estimation Approach

Traverse the design to propagate

statistical property

Look up EMin

in pre-characterized library

Compute EM at output by propagations

Pre-characterized STD tables

Pre-characterized EMin tables

Stage 1:Hardware characterization

Stage 2: Composition of EMs

Statistical property

Information of EMs

STD: standard deviationEMin: intrinsic error metric

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Our Quality Estimation Approach

Traverse the design to propagate

statistical property

Look up EMin

in pre-characterized library

Compute EM at output by propagations

Pre-characterized STD tables

Pre-characterizedEMin tables

Stage 1:Hardware characterization

Stage 2: Composition of EMs

Statistical property

Information of EMs

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Hardware Characterization: Observation #1 Observation #1: EMs of approximate hardware depend

on input patterns

Input patterns decide whether carry chain will lose bits

ETAIIM

CLA

RCA

CLA

RCA

CLA

RCA

CLA

RCA

‘0’

k guard blocks for MSBMSB

{A, B} {A, B} {A, B} {A, B}

EMin = f( k, STDA, STDB )

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Hardware Characterization: Observation #2 Observation #2: EMs in ETAIIM-type adders depend on

input distribution and hardware configuration

k = # of guard blocks to mitigate errors

Log(ES) vs. input STDs ER vs. input STDs

k = 1k = 2

k = 3k = 4

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Hardware Characterization: Our Solution Generate lookup tables to store pre-characterized EMs

Generate libraries

STDZ tables

STD A

STDB

Hardware configurations

EMin tablesST

D A

STDB

Hardware configurations

EMs vs. input STDs

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Our Quality Estimation Approach

Traverse the design to propagate

statistical property

Look up EMin

in pre-characterized library

Compute EM at output by propagations

Pre-characterized STD tables

Pre-characterized EMin tables

Stage 1:Hardware characterization

Stage 2: Composition of EMs

Statistical property

Information of EMs

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Composition of EMs: Error Propagation

EMin: EM generated by approximate hardware

{STD{A,B}, EM{A,B}}: propagated standard deviations / EMs from previous stages

{EMZ, STDZ}: EMs and STDs at output nodes

{STDA, EMA} {STDB, EMB}

{STDz, EMZ}

EMin

+* +*

+*

+*: approximate adders

Key issue: enable error propagation in circuit topology

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Composition of EMs: Observation Observation: EM (e.g., rate, magnitude) at a node

depends on both intrinsic and propagated EMs

ERA ERB

ERZ

ERin

+* +*

+*

ESA ESB

ESZ

ESin

+* +*

+*

ESZ = ESin + ESA + ESB(assume no cancellations between all error sources)

Pass RatePass Rate

Pass Rate

ERZ = 1-(1-ERin)⋅(1-ERA)⋅(1-ERB)

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Composition of EMs: Our Method Our method:

– Traverse the circuit and propagate STDs in its topology– EMs are looked up in the pre-characterized libraries

A B C D E F

Function= ((A+B)+(C+D))+(E+F)ERZ = 1−(1−ERin) · (1−ERA) · (1−ERB)EMZ = EMin + EMA + EMB

For each node, EMs are propagated as follows:

Traverse and propagate

(for EMs other than ER)

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Outline Related Work Problem Modeling and Proposed Approaches Results and Conclusions

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Results: Table-Lookup Approach

• Testcase: 5-node adder tree

• Input distributions: zero mean normal distribution with different STDs

• Different configurations of ETAIIMs

• Compared with Monte Carlo simulation

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Experimental Results: FIR Filter

NET11

NET1

C1 = 0.1

NET2

C2 = 0.2

NET3

C3 = 0.3

NET4

C4 = 0.4

NET10

NET9

NET5 NET6 NET7 NET8

Net Type Error Estimation Inaccuracy (%)ER ES ARES MSE SNR MAXE

NET9ETAII

M IN 0.3% 6.4% 17.0% 6.4% 19.1% 0.0%

NET10ETAII

M IN 1.3% 2.6% 61.9% 3.3% 10.7% 0.0%

NET11ETAII

M IN 1.0% 6.3% 419.6% 6.2% 6.1% 0.0%

NET11ETAII

M P13.4

% 5.8% 692.3% 5.8%436.4

% 0.7%

Approximate FIR Adders are approximate Multipliers are accurate

Estimation inaccuracies at each node for different error metrics

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Experimental Results: MAC

C0

A0 A1

level 1

C1 Ci

Ai

level i

Output

...

...

Approximate MAC(multiply-accumulate) Adders are approximate Multipliers are accurate 14 levels of MAC are tested20 testcases for each #level

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MAC: Comparison with HuangLR12

[HuangLR12] Relative inaccuracy = 109

beyond the lower bound of characterization

ES ER

Our method interpolates continuously changing EM in lookup table

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MAC: Speedup and Accuracy Improvement

Speedup= 8.4x Accuracy improvement = 3.75x

Faster runtime allows designer to evaluate more design combinationsBetter accuracy reduce the iterations due to mis-prediction

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Conclusions We propose an approach for output quality

estimation of approximate designs Our approach achieves 8.4× runtime

improvement for error composition and 3.75× average accuracy improvement for ES compared to previous (DAC-2012) work of Huang et al.

We demonstrate results on FIR filter and MAC circuits with up to 30 nodes

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Future Work Improve accuracy of EM estimation for relative

error metrics (e.g., ARES and SNR) Extend our approach to other approximate

modules, including multipliers Develop a synthesis flow for approximate

circuits using our EM analysis approach Generalize our approach to arbitrary input

distributions

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Thank You!

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Backup Slides

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Experiment and ResultsApproximate circuit: Random-generated circuits Netlists are randomly generated with accurate multipliers and different ETAIIM approximate adders

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Regression study of EM Composition

We also tried to generalize our propagation model with parameter regression

General form of error propagation models:

Simulated EM results from different hardware configurations and input distributions/EMs are used for regression

Parameters in the models are fitted with simulation data

are regression parameters

𝐸𝑅𝑍=1−10𝛼𝐶 ∙ (1−𝐸𝑅𝑖𝑛 )𝛼 𝑖𝑛 ∙((1−𝐸𝑅𝐴 ) ∙ (1−𝐸𝑅𝐵 ))α 𝑃

)

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Regression study of EM Composition

Results of parameter regression

Regression Parameters

ER ES ARES MSE SNR MAXE

1.03E+00 1.00E+00 2.42E-02 1.00E+00 3.46E-01 9.40E-01

1.26E+00 9.98E-01 9.76E-01 1.00E+00 7.15E-02 7.98E-01

-5.85E-03 5.74E-08 -5.92E-03 -5.55E-09-1.27E+00 8.65E-05Estimation Inaccuracy

w/o Reg. 4.15E-02 7.77E-02 8.38E+02 1.08E-01 1.35E+02 1.28E-01

with Reg. 7.40E-03 5.55E-01 2.09E+02 4.44E+04 4.04E-01 1.88E+01

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Experimental Results: FIR Filter

Approximate FIR Adders are approximate Multipliers are accurate

Estimation inaccuracies at each node for different error metrics NET11

NET1

C1 = 0.1

NET2

C2 = 0.2

NET3

C3 = 0.3

NET4

C4 = 0.4

NET10

NET9

NET5 NET6 NET7 NET8

Net Type Error Estimation Inaccuracy (%)ER ES ARES MSE SNR MAXE

NET9ETAII

M IN 0.3% 6.4% 17.0% 6.4% 19.1% 0.0%

NET10ETAII

M IN 1.3% 2.6% 61.9% 3.3% 10.7% 0.0%

NET11ETAII

M IN 1.0% 6.3% 419.6% 6.2% 6.1% 0.0%

NET11ETAII

M P13.4

% 5.8% 692.3% 5.8%436.4

% 0.7%