Static and Dynamic CMOS Design - RNBS Web page ... CMOS Design, H20/4/25 1 Static and Dynamic CMOS...
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Mattausch, CMOS Design, H20/4/25 1
Static and Dynamic CMOS Design• Basic Considerations• Important Technical Concepts
– Transfer (DC) Characteristic and Switching Point – Transient (AC) Characteristic as well as Rise-Time, Fall-Time and Delay Time– Fan-In and Fan-Out
• Static CMOS-Logic– Conventional Complementary MOS Logic– Pseudo n-MOS Logic– Pass-Transistor Logic
• Dynamic CMOS-Logic– Precharge-Evaluate (PE) Logic
– NP Domino Logic– CMOS Domino Logic
CMOS Logic Circuit Designhttp://www.rcns.hiroshima-u.ac.jp
Link(リンク): センター教官講義ノート の下 CMOS論理回路設計
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Basic Considerations
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Meaning of Static and Dynamic CMOS Logic
LogicOutput
VDD(1)
VSS(0)
Noise Noise Noise
Dynamic Logic
Static Logic
Time
Static CMOS logic actively restores the logic output values,while dynamic CMOS logic does not.
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Advantages of Static and Dynamic CMOS Design
- high functional reliability
- easy circuit design
- unlimited validity of logic outputs
The most important design goals determine, whether a static or a dynamic design technology is chosen.
dynamic design
- high switching speed
- small area consumption
- low power dissipation
static design
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Important Technical Concepts- Transfer (DC) Characteristic and
Switching Point
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Transfer (DC) Characteristic(Example Inverter)
Inverter Circuit Inverter Transfer Characteristic
VOH = “high” output voltageVOL = “low” output voltageVIL = max. “low” input voltageVIH = min. “high” input voltageVIL -VSS =“low” noise marginVDD - VIH = “high” noise margin
The transfer characteristic of CMOS logic is analog. The region between points A and B (slope = 1) is logically invalid.
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Switching Point VSP(Example Inverter)
At the switching point both transistors M1 and M2 are in the saturation region and have equal conductance.
Switching-Point Definition Switching-Point Condition
VSP =
βn
β p
⋅ VTH, n + (VDD − VTH, p )
1+βn
βp
ID, n− MOS = ID, p−MOS
βn
2VSP − VTH, n( )2
=β p
2VDD − VSP − VTH ,p( )2
β p ≈ βn ; VTH , p ≈ VTH, n VSP ≈VDD
2
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Transfer Characteristic and Transistor-Size (Example Inverter)
p- and n-MOS transistor design influences the transfer characteristic
Correlation between β and MOS-transistor parameters
The choice of MOS-transistor length L and width W is a major design freedom in CMOS circuit design.
β =µ ⋅ε ⋅ W
tox ⋅ L
µ = carrier mobilityε = gate-insulator permittivitytox = gate-insulator thicknessW = MOS transistor widthL = MOS transistor lengthµn ≈ 3µ p
β p ≈ βn Wp ≈ 3Wn
SP3
SP2
SP1
<<1
>>1
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Transfer Characteristic of NAND Gates
VSP =
βn
Nmβp
⋅VTH ,n + (VDD − VTH , p )
1+βn
N mβ p
; m = 1~2
N-input NAND Gate Switching-point N-input NAND Gate
N
,inv
, N-NAND
SPinv
SPN-NAND
<<1
To keep the switching point of the N-input NAND gate at about VDD/2, it is necessary to choose Wn~NWp/3.
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Transfer Characteristic of NOR Gates
To keep the switching point of the N-input NOR gate at about VDD/2, it is necessary to choose Wp~3NWn.
VSP =
Nmβn
βp
⋅ VTH, n + (VDD − VTH, p )
1+N mβn
β p
; m = 1~2
N-input NOR Gate Switching-point N-input NOR Gate
N
,inv
, N-OR
SPinv
SPN-OR
>>1
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Important Technical Concepts- Transient (AC) Characteristic as well as
Rise-Time, Fall-Time and Delay Time
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Rise-, Fall- and Delay-Time of Logic Circuits
Rise-, fall and delay time are the main quantities for characterizing the performance of a logic CMOS circuit.
50% (VDD/2)
VDD
VDD
Logic Gate Transient Input and Output Rise-, Fall- and Delay-Time
Rise-Time trTime for a transient waveform to rise from 10% to 90% of its steady state values.
Fall-Time tfTime for a transient waveform to fall from 90% to 10% of its steady state values.
Delay-Time tdTime difference from the 50% transition level of the input waveform to the 50% transition level of the output waveform.
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Simple AC Model/Equations for CMOS Logic
Pull-down, pull-up network and the load capacitance CLdetermine the AC-performance of the CMOS logic circuit.
VDD
VSS
VDD
VSS
t f = kf
CL
β pd,eff ⋅ VDDtdf ≈ 1
2 tf;VDD
Ckt
effpu
Lrr ⋅
=,β
tdr ≈ 12 tr;
rise time: pull-up networkfall time: pull-down network
td,av ≈tdr + tdf
2; kf and kr depend on fabrication technology (~2-4)
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Important Technical Concepts- Fan-In and Fan-Out
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Definition of Fan-In and Fan-Out for Logic Gates
The fan-in of a logic gate is the number of its inputs.The fan-out of a logic gate is the number of its output
connections to other gates.
fan-in = m fan-out = k
123
m-1m
2
1
3
k
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Delay-Time Effect of Fan-In (m) and Fan-Out (k) (Constant n-MOS and p-MOS transistor W/L-ratios, respectively)
The fan-in has a quadratic impact on NAND-Gate fall times as well as NOR-Gate rise times.
)k(mm fexfindf,NAND ttt ⋅+⋅⋅=
rexrindr,NAND ttt ⋅+⋅= km
NAND-Gate
)k(mm rexrindr,NOR ttt ⋅+⋅⋅=
fexfindf,NOR ttt ⋅+⋅= km
NOR-Gate
tfin and trin are internal fall- and rise-time of a minimum sized inverter, due to its own gate and drain capacitances, respectively.
tfex and trex are external fall- and rise-time of a minimum sized inverter, due the external load of a minimum sized inverter with typical routing capacitance, respectively.
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Static CMOS-Logic - Conventional Complementary MOS(CMOS) Logic
- Pseudo n-MOS Logic- Pass-Transistor Logic
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Conventional Static CMOS Logic
Conventional CMOS logic is static because 1 and 0 are restored by pull-up and pull-down network, respectively.
Conventional CMOS principle Example with fan-in equal 5
A
B
Pull-UpNetwork
Fu (A , B , ⋅ ⋅ ⋅, N )
Fd (A,B,⋅ ⋅ ⋅,N)
Pull-DownNetwork
N
Fd (A,B,⋅ ⋅ ⋅,N)
= Fu (A , B , ⋅ ⋅ ⋅, N )
Pull-UpNetwork
Z = A • (E + D) + (B • C) • (E + D)
Pull-DownNetworkZ = A• (B+ C) + (D• E)
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Pseudo n-MOS Logic
Advantage: Less transistors and lower input capacitance. Disadvantage: High power dissipation and low pull-up speed.
Principle:Use only the pull-down network.Chose pull-up strength of p-MOS smallerthan pull-down strength of network.
Pull-DownNetworkZ = A• (B+ C) + (D• E)
Example with fan-in equal 5
A
B
Fd (A,B,⋅ ⋅ ⋅,N)
Pull-DownNetwork
N
Fd (A,B,⋅ ⋅ ⋅,N)
VSS
VDD
VSS
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Pass-Transistor Logic
Any logic function FP can be constructed by controlling a set of pass signals Pi by another set of control signals Vi.
V1 V2 Vk
P1
P2
Pk
FP =P1(V1) + P2(V2 ) + ⋅⋅⋅ +Pk (Vk )
Pass-Transistor Logic Gate
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Operation P1 P2 P3 P4
NOR(A,B) 0 0 0 1
XOR(A,B) 0 1 1 0
NAND(A,B) 0 1 1 1
AND(A,B) 1 0 0 0
OR(A,B) 1 1 1 0
Realization Table of 2-Input Gates
Implementation with n-MOS transistors(Disadvantage: Noise-margin of “high” level reduced by Vth,n)
2-Input Pass-Transistor Gate Example
The pass-transistor logic has a good implementation density, but may have slow switching speed.
Implementation with n-MOSand p-MOS transistors
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Dynamic CMOS-Logic - Precharge-Evaluate (PE) Logic- NP Domino Logic- CMOS Domino Logic
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Precharge-Evaluate (PE) Logic
Advantage: Low power dissipation and high speed. Disadvantage: Low reliability and difficult design.
clock
VSS
AB
Fd (A,B,⋅ ⋅ ⋅,N)
Pull-DownNetwork
N
Fd (A,B,⋅ ⋅ ⋅,N)
VDD
Principle: Use only the pull-down network.clock=0: Precharge output to 1.clock=1: Evaluate pull-down network.
Example with fan-in equal 5
Pull-DownNetwork
Z = A• (B+ C) + (D• E)
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NP Domino Logic
Low power and high speed, but difficult to design.
VDD
VSS
clock
VDD
VSS
clock
VDD
VSS
clock
AB
N
Pull-DownNetwork
F1
Pull-UpNetwork
F2Pull-DownNetwork
F3
Alternating cascade of PE-logic with pull-up/pull-down networks.
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CMOS Domino Logic Gate
CMOS domino logic achieves a good balance of switching speed, area/power consumption and design reliability.
VDD
VSS
clock
Pull-DownNetwork
Fd (A,B,⋅ ⋅ ⋅,N)
Fd (A,B,⋅ ⋅ ⋅,N)
AB
N
Buffer and “high” level restoring elements
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CMOS Domino Logic Circuit
A CMOS domino logic circuit uses only pull-down networks.
VDD
VSS
clock
Pull-DownNetwork
Fd1
AB
N
VDD
VSS
clock
Pull-DownNetwork
Fd 2
VDD
VSS
clock
Pull-DownNetwork
Fd 3