Solution processed molecular floating gate for flexible flash memories

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A L

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Published: 31/10/2013

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Publication details:Zhou, Y., Han, S-T., Yan, Y., Huang, L-B., Zhou, L., Huang, J., & Roy, V. A. L. (2013). Solution processedmolecular floating gate for flexible flash memories. Scientific Reports, 3, [3093].https://doi.org/10.1038/srep03093

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Solution processed molecular floatinggate for flexible flash memoriesYe Zhou, Su-Ting Han, Yan Yan, Long-Biao Huang, Li Zhou, Jing Huang & V. A. L. Roy

Department of Physics and Materials Science and Center of Super-Diamond and Advanced Films (COSDAF), City University of HongKong, Hong Kong SAR.

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltagenonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanismof the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine(F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentaceneas semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trappedelectrons alone due to abundant electron density. All the devices exhibited large memory window, longcharge retention time, good endurance property and excellent flexibility. The obtained results have greatpotential for application in large area flexible electronic devices.

The next-generation electronic systems are expected to be light, flexible and portable for applications inintegrated circuits (ICs), organic light emitting diodes (OLEDs), solar cells, radio frequency identification(RFID) tags and so on1–9. Memory is an essential part of electronic systems for data processing, storage and

communication; however, currently available inorganic memories are not compatible with flexible substrates.Thus new approaches to develop flexible memory are necessary to realize large area flexible electronics.Tremendous efforts have been made towards developing high-density, high-speed and nonvolatile memorydevices10–15. Among many types of nonvolatile memory, transistor-based flash memory with nano-segmentedfloating gate architecture have attracted huge interest due to the massive memory capacity and advanced fab-rication technology16. The stored charges are located in the potential well of the blocking and tunnelling dielectriclayers, resulting in nonvolatile memory operations. If the charge storage layers are made up of thin films, anydielectric defects would leak the stored charges and degrade the retention property of the device. Therefore, amonolayer consists of well-separated nanoparticles could be a best choice to store the charges. On this regard,multidisciplinary efforts have been taken in recent years to fabricate metal nanocrystal based floating gate layer,including thermal evaporation17,18, electrostatic self-assembly19,20, micro-contact printing21 and synthesis in blockcopolymer22,23. However, nanoparticle assembly and morphology of the nanoparticle film should be controlledcarefully to avoid nanoparticle-to-nanoparticle charge tunnelling. One solution to the problem is to utilizealternate charge storage elements with high charge-carrier binding energies and large area densities. Molecularmaterials, which are on the order of nanometer or even sub-nanometer in size, represent such idealized candi-dates with high charge density storage sites24. Among them, C60, the most common buckyball clusters in fullerenefamily, are of great interest due to their potential applications in electronic devices using their semiconductingfeatures25,26. Most of the reports on C60 are based on time-consuming vacuum sublimation process, which is notcompatible with large area roll-to-roll fabrication method27. A facile solution processing method to obtain thefloating gate layer should be favorable for technological applications. C60 derivatives have gained a lot of attentionin transistors, photovoltaic devices and memory cells due to their high solubility in organic solvent28–33. However,the synthesis of C60 derivatives are still complicated and expensive; meanwhile their electronic performances arenot as good as pristine C60

34. Pristine C60 is reasonably soluble in organic solvents which could pave a way forsolution processed molecular gated flexible flash memories. The preparation of defined density of molecularcharge trapping elements via simple solution process remains challenging.

In this work, we demonstrate a simple approach for the preparation of C60 molecular floating gate layer on aflexible substrate. The coverage of the molecular floating gate or the density of molecular charge trapping layer isfacilely controlled by spin-coating method in a single step. We systematically study the charge trapping mech-anism of the C60 floating gate under ambient conditions. Flash memory transistors with air-stable p-typepentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) as semiconductors have been fabricated.The pentacene device exhibited a memory window of 4 V with both hole and electron trapping ability, while the

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Received29 July 2013

Accepted11 October 2013

Published31 October 2013

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should be addressed toV.A.L.R. (val.roy@

cityu.edu.hk)

SCIENTIFIC REPORTS | 3 : 3093 | DOI: 10.1038/srep03093 1

F16CuPc device trapped electrons alone with a memory window of2 V. All the devices exhibited charge retention larger than 104 s withgood cell-to-cell uniformity. The electrical performances of all thedevices are well-maintained even after 500 programming/erasingcycles and did not degrade substantially upon bending.

ResultsDevice struture and operation mechanism. The overall fabricationof the memory transistor is illustrated schematically in Figure 1a.Atomic layer deposited aluminum oxide (Al2O3) was selected as theblocking dielectric layer on top of the silver (Ag) gate electrode onflexible poly(ethylene terephthalate) (PET) substrate. The atomiclayer deposition technique allows for a high quality, defect-freedielectric layer with good barrier properties at low substratetemperature. Al2O3 has been demonstrated as a promising high-kdielectric candidate to minimize gate leakage current and achieve lowvoltage operation in thin film memory transistors35–38. C60 was spin-coated over the Al2O3 and then thermally annealed at 120uC for10 min. A thin layer of poly(4-vinylphenol) (PVP) was then spin-coated onto the C60 layer using orthogonal solvents in order toprevent the dissolution of the C60 layer. A detailed description ofthe fabrication process is given in the experimental section. PVPpossesses high resistivity and thermal stability, and has beendemonstrated as a good polymer dielectrics19. In our designeddielectric system, PVP has relatively low dielectric constant (4.7)compared with Al2O3 (7)39,40. According to the equation E1 5 Vg/(d1 1 d2 (e1/e2)), where ei are the dielectric constants and di are thethicknesses of the two dielectric layers, the applied electrical field inPVP layer (E1) is relatively stronger than in Al2O3 layer. Therefore,this system enables efficient charge transfer from the semiconductorlayer to charge trapping layer through the tunnelling dielectric layer.Due to their good stabilities in ambient, pentacene and F16CuPc werechosen as the p-type and n-type semiconductor to investigate thecharging mechanism of the C60 floating gate layer. Figure 1billustrates the chemical structures of the organic small molecularmaterials used in this study. Figure 1c displays the atomic force

microscopy (AFM) image of the C60 film spin-coated at 1000 rpm.The C60 film exhibited a surface morphology of separated islands,which is favorable for charge storage. The surface morphology of theC60 film spin-coated through high speed is also analyzed and showsrelatively low densities (see supporting information Figure S1).Previous studies have shown that the memory capacity is depen-dent on the charge trapping element density, while the memorywindow increases with enhanced trapping sites36. Therefore, unlessotherwise mentioned, all the memory devices are based on a C60 layerresulting from the low spin-coating speed (1000 rpm).

Electrical performance of p-type memory device. To investigate thetrapping capability of C60 in the p-type memory device, we firstfabricated a transistor with pentacene as the semiconductor layer.The schematic representation of the tunnelling of charge carriers inpentacene device is illustrated in Figure 2a. The holes are tunnelledthrough the PVP layer from the highest occupied molecular orbital(HOMO) of pentacene to C60 layer while electrons are tunnelledfrom the lowest unoccupied molecular orbital (LUMO) of penta-cene to C60 trapping layer. It should be noted that intrinsic holedensity is higher than electron density in pentacene41,42. Figure 2bshows the electrical characteristics of the pentacene memory devicebefore and after applying the negative gate pulses (25 V for 100 ms).The electrical properties were found to be uniform by examiningdifferent devices. The memory transistors show a hole mobility ofabout 5 3 1022 cm2 V21 s21 and current on/off ratio of about 103

while the transistors without C60 possess a mobility of about 0.1 cm2

V21 s21. The slightly decreased mobility can be attributed to theincreased surface roughness when introducing the C60 layer underPVP. The applied electrical field is about 1.1 MV/cm in thetunnelling PVP layer, which is appropriate for efficient chargeinjection. The high mobility of C60 can guide fast charge distribu-tion and assist the charging process when the charge injection is non-uniform across the C60 layer. The trend of the transfer curves revealsa typical hole trapping behavior indicating holes are injected frompentacene channel into C60 Layer through PVP by the application of

Figure 1 | (a) Schematic diagram depicting the basic fabrication process of the molecular floating gate memory device. (b) Chemical structure of the

molecules. (c) Tapping-mode AFM image of the C60 layer.

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the electric field. The trapped holes in C60 layer screened the channeland resulted in decreasing the effective gate electric field. In order toanalyze the charging effect of the dielectric system, we also fabricatedthe device without C60 layer (see supporting information Figure S2).Almost negligible charging and discharging is observed in PVP/Al2O3 stack layers, therefore the charge carriers should mostly betrapped in C60 Layer. The electrical characteristics of the memorydevices before and after applying the positive gate pulses (5 V for100 ms) are shown in Figure 2c. The results indicate that electrontrapping also occurs using C60 as the floating gate. In addition,pentacene has instrinsic electron mobility which makes themavailable to be trapped. This observation is interesting as most ofthe flash memory devices are based on single charge carrier trappingmechanism17,43. At the same electrical field, the amount of storedholes is more than the electrons according to the equation Q 5 C3 DVth where Q is the stored charges, C is the capacitance of thedielectrics and DVth is the threshold voltage shift. The Vth as a

function of bias time is summarized in Figure 2d. The Vth shiftincreases with increased programming operation time, both inhole and electron charging process. Furthermore, Vth reach certainsaturated values after long bias time, which is similar with metalnanoparticle floating gate memory21,44. During the chargingprocess, the charge carriers (holes or electrons) trapped in the C60

layer can increase the capacitive coupling effect thus limited amountof trapped charge carriers are available at certain gate bias. Inaddition, the saturation rate of hole trapping process is observed tobe quicker than electron trapping process. This may be attributed tothe high hole mobility than electron mobility in pentacene45.

With the property of trapping both holes and electrons, the mem-ory window of the pentacene devices could be further enhanced.Figure 3a and 3b show the electrical characteristics of the two states(The state after positive gate bias 5 V for 1 s is denoted as ON stateand the state after negative gate bias 25 V for 1 s is denoted as OFFstate). The memory window (Vth shift) can reach about 4 V and the

Figure 2 | (a) Energy band diagram of the pentacene based memory device. (b) Transfer characteristics of the memory transistor before and after negative

gate bias. (c) Transfer characteristics of the memory transistor before and after positive gate bias. Inset: Optical imgae of the flexible memory device. (d)

Threshold voltage with respect to the gate bias time.

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maximum ON/OFF current ratio is about 1.5 3 103. This result isbetter than previously reported low voltage memory with conven-tional charge trapping layers such as evaporated metal layer and self-assembled nanoparticles20,35. It should be noted that the memorywindow depends strongly on the applied gate bias and lager biascould lead to larger memory windows21. Here we kept the appliedvoltage not exceeding 5 V to ensure the low voltage operation of thememory. The operation mode of the memory transistor has beenreproducibly and reversely switched from one state to another state.The endurance properties of the pentacene device were studied byrepeated application of gate bias pulses of 65 V. Figure 3c illustratesthe pulse sequence in the test. The ON and OFF state is well main-tained for more than 500 cycles as shown in Figure 3d. In addition,we performed the data retention experiment on the devices andFigure 3e illustrates the test pulse sequence. In between the differentmeasurement points, the devices are kept without applying any gate

biases. The retention capability is shown in Figure 3f. The memorywindow is maintained at 82.1% for 104 s, which is comparable withpreviously reported low voltage organic memory devices3,20,35. In ourdevice, the high energy barrier height of C60 surrounded by PVPsuppresses the charge transport between each C60 island. At the sametime, charge leakage from C60 to the semiconductor channel is effec-tively prohibited by the PVP tunnelling layer46–48. Therefore, thecharge carriers (holes and electrons) are confined at the C60 floatinggate49. Overall, both the positive part and negative part of the mem-ory windows are suitable for the use as nonvolatile storage media.

Electrical performance of n-type memory device. We furtherexplore the trapping capability of C60 in n-type memory device, inwhich F16CuPc is selected as the semiconductor layer. Figure 4adepicts the energy band diagram of charge carrier tunnelling inF16CuPc based device. Figure 4b shows the electrical characteristics

Figure 3 | (a) Transfer curve (IDS 2 VGS) of the pentacene memory at ON and OFF state on log scale. (b) Transfer curve ( | IDS | 1/2 2 VGS) of the

pentacene memory at ON and OFF state on linear scale. (c) Test pulse sequence for the endurance test. (d) Endurance characteristics of the pentacene

device as a function of bias cycles. (e)Test pulse sequence for the retention test. (f) Data retention capability as a function of time.

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of F16CuPc memory device before and after applying a positive gatepulse (5 V for 100 ms). The electrons tunnelled from F16CuPcchannel into the C60 Layer through PVP, resulting in a decreasedeffective gate electrical field. Such a destructive electrical field leads toa reduced channel conductance, and the transfer curves shift towardsthe positive direction. The F16CuPc device without C60 layer is alsofabricated and almost no charging effect of the dielectric system isobserved (see supporting information Figure S3). The memorytransistors show an electron mobility of about 1.8 3 1023 cm2 V21

s21 and current on/off ratio of about 102 while the F16CuPctransistors without C60 show a mobility of about 3 3 1023 cm2 V21

s21. Further applying a negative gate pulse (25 V for 100 ms) do notinduce a negative shift of the transfer curves, which might beoriginated from the extremely low hole mobility of F16CuPc50. It isunderstood that available minority carrier (hole) density in F16CuPcis much lower than the minority carrier (electron) density inpentacene. Therefore, we found both electron and hole trapping inpentacene based devices where as only electrons are trapped in

F16CuPc based devices. The Vth with respect to the bias time issummarized in Figure 4d. The Vth shift towards more positivedirection with prolonged bias, suggesting that additional chargecarrier is brought to the molecular floating gate with increased biastime. The saturated level is also be observed here, demonstrating bothtrapped holes and electrons would cause capacitive coupling in theC60 floating gate.

Figure 5a and 5b show the electrical characteristics of the F16CuPcmemory device at two states (The high conductance state is denotedas ON state and the low conductance state is denoted as OFF state).The memory window is about 2 V and the maximum ON/OFFcurrent ratio is about 7 3 102. Continuous application of gate biaspulses of 65 V for 1 s is carried out to measure the enduranceproperties as illustrated in Figure 5c. The ON and OFF state has beenwell maintained for more than 500 cycles as shown in Figure 5d. Thetest pulse sequence for the data retention test in F16CuPc device isillustrated in Figure 5e. The ON state and OFF state is well separatedwith respect to the elapsed time as shown in Figure 5f. About 19.2%

Figure 4 | (a) Energy band diagram of the F16CuPc based memory device. (b) Transfer characteristics of the memory transistor before and after

positive gate bias. (c) Transfer characteristics of the memory transistor before and after negative gate bias. (d) Threshold voltage as a function of the gate

bias time.

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SCIENTIFIC REPORTS | 3 : 3093 | DOI: 10.1038/srep03093 5

of the memory window is lost after a retention time of 104 s. Thestorage ability of the memory is comparable to recently reportedmemory devices based on n-type semiconductors51,52.

Bending stability of the memory devices. In addition to the reliablememory operations, the bending stability is another importantparameter to examine the reliability of the flexible devices. Theorganic/inorganic bilayer dielectric structure used in our devicecan reduce the possibility of cracking or delamination duringrepetitive bending53. Flexibility tests using cyclic bending wereperformed both in tensile and compressive mode with a bendingradius of 10 mm. Figure 6a shows the schematic diagram of thebended device in a compressive state and Figure 6b illustrates thetensile state. The strain can be estimated from the equation D/2R,where D is the thickness of the substrate and R is the bendingradius54. The bending tests were done up to 500 times to confirm

the flexibility of both the pentacene and F16CuPc devices. Figure 6cand 6d show the memory window as a function of compressivebending cycles. Figure 6e and 6f show the memory window as afunction of tensile bending cycles. These results confirm that allthe devices exhibit stable programmable properties with goodmechanical flexibility.

DiscussionThe high mobility of C60 can guide fast charge distribution and assistthe charging process when the charge injection is non-uniformacross the C60 layer. For the pentancene based p-type semiconductordevices, the trend of the transfer curves shows a typical hole trappingbehavior indicating holes are injected from pentacene channel intoC60 Layer through PVP by the application of the electric field. Due tointrinsic electron mobility as minority carriers, electron trapping alsooccurs using C60 as the floating gate in pentacene based devices. In

Figure 5 | (a) Transfer curve (IDS 2 VGS) of the F16CuPc memory at ON and OFF state on log scale. (b) Transfer curve ( | IDS | 1/2 2 VGS) of the F16CuPc

memory at ON and OFF state on linear scale. (c) Test pulse sequence for the endurance test. (d) Endurance characteristics of the F16CuPc device

with respect to the number of bias operations. (e)Test pulse sequence for the retention test. (f) Data retention capability with respect to the elapsed time.

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SCIENTIFIC REPORTS | 3 : 3093 | DOI: 10.1038/srep03093 6

addition, due to the high intrinsic hole mobility of holes than elec-trons in pentacene, the saturation rate of hole trapping process isobserved to be quicker than electron trapping process. For the pen-tacene based devices, both the positive part and negative part of thememory windows are suitable for the use as nonvolatile storagemedia. On the other hand, for the devices based on n-type semi-conductor F16CuPc, available minority carrier (hole) density is muchlower than the minority carrier (electron) density in pentacene.Therefore, only electrons are trapped in F16CuPc based devices.The electrons tunnelled from F16CuPc channel into the C60 Layerthrough PVP, resulting in a decreased effective gate electrical fieldwhich leads to a reduced channel conductance, and the transfercurves shift towards the positive direction. During the charging pro-cess, due to the increased capacitive coupling between the trappedcharge carriers (holes or electrons) in the C60 layer limited amount oftrapped charge carriers are available at certain gate bias for bothpentacene and F16CuPc based devices.

Although metal nano-floating gate have been widely investigatedas the charge trapping layer in flash memories, they are still sufferingfrom poor processability to implement them in printing technology.The solution processed molecular materials should be a choice forlarge area printable electronics. On the other hand, unlike conven-tional metal or metal nanoparticle based memory device, the

trapping capability of C60 will be of great importance to realize func-tional nonvolatile memory. Since molecular materials can be func-tionlized to obtain multifunctional properties, it is important tounderstand the working mechanism of such molecular floating gatedevices. The C60 floating gates showed ambipolar trapping behaviorin the pentacene based memories and unipolar trapping behavior inthe F16CuPc based memories. The approach to trap both holes andelectrons in memory devices is an important to achieve large memorywindow and other electrically variable properties.

Our fabrication methods including the fabrication of C60 molecu-lar floating gate layer and PVP tunneling dielectric layer are solution-processed. The simplified fabrication steps and low temperatureprocessing method is quite promising for flexible electronics. Thesucessful adopting of this structure on flexible substrates demon-strates that this method is mass-producible to construct innovativelarge area electronics.

In conclusion, we have demonstrated that solution processed C60

could be an excellent candidate for molecular floating gate in flexibleflash memories. By adopting C60 as the charge trapping layer in bothpentacene and F16CuPc memory transistors, reliable p-type and n-type memory devices has been achieved. All these devices show largememory window, long retention time, good endurance propertiesand excellent mechanical flexibilities. More importantly, our results

Figure 6 | (a) Schematic illustration of the device at compressive state. (b) Schematic illustration of the device at tensile state. (c) Memory window of the

pentacene device with respect to compressive bending cycles. (d) Memory window of the F16CuPc device with respect to compressive bending cycles.

(e) Memory window of the pentacene device with respect to tensile bending cycles. (f) Memory window of the F16CuPc device with respect to

tensile bending cycles.

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show that the use of molecular floating gate for the realization of neworganic flash memory devices offers a promising route for the futuredevelopment of advanced organic electronics.

MethodsMaterials. PVP (average Mw ,25,000), C60 (99.5%), pentacene (sublimated grade)and F16CuPc (sublimated grade) were purchased from Aldrich. PET substrates werecut from commercially available PET films. All chemicals and solvents were usedwithout further purification in the experiment.

Device fabrication. PET substrate was cleaned in an ultrasonic bath with detergent,acetone, and isopropanol prior to processing. 20 nm Ag film was thermallyevaporated as the gate electrode. 40 nm Al2O3 layer was deposited using a Savannah100 ALD system at a substrate temperature of 80uC. C60 was dissolved in 1,2,4-trichlorobenzene (TCB) (10 mg ml21) and spin-coated at different speeds on theAl2O3 layer with subsequent annealing for 10 min at 120uC in a nitrogenenvironment. After that, the PVP film was fabricated by spin-coating the preparedsolution (5 mg ml21 in isopropanol). The resulted film was annealed at 100uC for 1hour in a vacuum oven and the thickness was about 20 nm. 40 nm pentacene or25 nm F16CuPc were thermally deposited as the semiconductor layer at a rate of 0.1 to0.2 A s21. The substrate temperature was always kept at room temperature whendepositing the p-type and n-type semiconductor films. Gold (Au) electrodes wereemployed as the source and drain contacts for both p-channel and n-channel memorytransistors. 40 nm Au films were thermally evaporated through a shadow mask at arate of 0.2 A s21, with a channel length to channel width ratio of 50 mm/1000 mm.

Characterization. The morphology of the C60 layer was investigated by AFM (VeecoMulti mode). The thicknesses of the deposited films were measured by anellipsometer. The electrical characteristics of the memory transistors were measuredusing a Keithley 2612 source meter. All measurements were conducted inatmospheric environment with a relative humidity of 60% and a temperature of 25uC.

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AcknowledgementsWe acknowledge grants from City University of Hong Kong’s Applied Research GrantProject no. 9667072.

Author contributionsY.Z. performed the experiments and wrote the paper. S.T.H., Y.Y., L.B.H., L.Z. and J.H.assisted with the experiments, discussed the results and commented on the manuscript.V.A.L.R. supervised the project and finalized the manuscript.

Additional informationSupplementary information accompanies this paper at http://www.nature.com/scientificreports

Competing financial interests: The authors declare no competing financial interests.

How to cite this article: Zhou, Y. et al. Solution processed molecular floating gate for flexibleflash memories. Sci. Rep. 3, 3093; DOI:10.1038/srep03093 (2013).

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