SEQUENTIAL LOGIC CIRCUIT DESIGN. 1 Sequential Circuits Combinational Circuit Memory Elements Inputs...

SEQUENTIAL LOGIC

CIRCUIT DESIGN

22

Sequential CircuitsSequential Circuits

CombinationalCircuit

MemoryElements

Inputs Outputs

Asynchronous

Synchronous

CombinationalCircuit

Flip-flops

Inputs Outputs

Clock

33

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0

0

1

0

0

0 1 Q = Q0

Initial Value

44

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1

1

0

0

0

1 0 Q = Q0

Q = Q0

55

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0

0

1

1

0

1 Q = 0

Q = Q0

66

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0 10 1 11

0

1

0

0 1Q = 0

Q = Q0

Q = 0

77

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0

0

1

0

1

1 0

Q = 0

Q = Q0

Q = 1

88

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1

1

0

0

1

1 0

Q = 0

Q = Q0

Q = 1

Q = 1

99

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1 1 01 1 0

0

1

1

1

0 0

Q = 0

Q = Q0

Q = 1

Q = Q’

0

1010

LatchesLatches

SR Latch

R

S

Q

Q

S R Q0 Q Q’

0 0 0 0 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1 1 01 1 0 0 01 1 1

1

0

1

1

0 0

Q = 0

Q = Q0

Q = 1

Q = Q’

0

Q = Q’

1111

LatchesLatches

SR Latch

R

S

Q

Q

S R Q

0 0 Q0

0 1 0

1 0 1

1 1 Q=Q’=0

No change

Reset

Set

Invalid

S

R

Q

Q

S R Q

0 0 Q=Q’=1

0 1 1

1 0 0

1 1 Q0

Invalid

Set

Reset

No change

1212

LatchesLatches

SR Latch

R

S

Q

Q

S R Q

0 0 Q0

0 1 0

1 0 1

1 1 Q=Q’=0

No change

Reset

Set

Invalid

S’ R’ Q

0 0 Q=Q’=1

0 1 1

1 0 0

1 1 Q0

Invalid

Set

Reset

No change

S

R

Q

Q

1313

Controlled LatchesControlled Latches

SR Latch with Control Input

C S R Q

0 x x Q0

1 0 0 Q0

1 0 1 0

1 1 0 1

1 1 1 Q=Q’

No change

No change

Reset

Set

Invalid

S

R

Q

Q

S

R

C

S

RQ

QS

R

C

1414


D Latch (D = Data)

C D Q

0 x Q0

1 0 0

1 1 1

No change

Reset

Set

S

R

Q

Q

D

C

C

Timing Diagram

D

Q

t

Output may change

1515


D Latch (D = Data)

C D Q

0 x Q0

1 0 0

1 1 1

No change

Reset

Set

C

Timing Diagram

D

Q

Output may change

S

R

Q

Q

D

C

1616

Flip-FlopsFlip-Flops

Controlled latches are level-triggered

Flip-Flops are edge-triggered

C

CLK Positive Edge

CLK Negative Edge

1717


Master-Slave D Flip-Flop

D Latch(Master)

D

C

QD Latch(Slave)

D

C

Q QD

CLK CLK

D

QMaster

QSlave

Looks like it is negative edge-triggered

Master Slave

1818


Edge-Triggered D Flip-Flop

D

CLK

Q

Q

D Q

Q

D Q

Q

Positive Edge

Negative Edge

1919


JK Flip-Flop

D Q

Q

Q

QCLK

J

K

J Q

QK

D = JQ’ + K’Q

2020


T Flip-Flop

D = TQ’ + T’Q = T Q

J Q

QK

T D Q

Q

T

D = JQ’ + K’QT Q

Q

2121

Flip-Flop Characteristic TablesFlip-Flop Characteristic Tables

D Q

Q

D Q(t+1)0 01 1

Reset

Set

J K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q’(t)

No change

Reset

Set

Toggle

J Q

QK

T Q

Q

T Q(t+1)0 Q(t)1 Q’(t)

No change

Toggle

2222

Flip-Flop Characteristic EquationsFlip-Flop Characteristic Equations

D Q

Q

D Q(t+1)0 01 1

Q(t+1) = D

J K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q’(t)

Q(t+1) = JQ’ + K’Q

J Q

QK

T Q

Q

T Q(t+1)0 Q(t)1 Q’(t)

Q(t+1) = T Q

2323


Analysis / Derivation

J Q

QK

J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 00 1 11 0 01 0 11 1 01 1 1

No change

Reset

Set

Toggle

2424



J Q

QK

J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 01 0 11 1 01 1 1

No change

Reset

Set

Toggle

2525



J Q

QK

J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 01 1 1

No change

Reset

Set

Toggle

2626



J Q

QK

J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

No change

Reset

Set

Toggle

2727



J Q

QK

J K Q(t) Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

K

0 1 0 0J 1 1 0 1

Q

Q(t+1) = JQ’ + K’Q

2828

Flip-Flops with Direct InputsFlip-Flops with Direct Inputs

Asynchronous Reset

D Q

Q

R

Reset

R’ D CLK Q(t+1)

0 x x 0

2929


Asynchronous Reset

D Q

Q

R

Reset

R’ D CLK Q(t+1)

0 x x 0

1 0 ↑ 0

1 1 ↑ 1

3030


Asynchronous Preset and Clear

PR’ CLR’ D CLK Q(t+1)

1 0 x x 0D Q

Q

CLR

Reset

PR

Preset

3131




1 0 x x 0

0 1 x x 1

D Q

Q

CLR

Reset

PR

Preset

3232




1 0 x x 0

0 1 x x 1

1 1 0 ↑ 0

1 1 1 ↑ 1

D Q

Q

CLR

Reset

PR

Preset

3333

Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits

The State

● State = Values of all Flip-Flops

Example

A B = 0 0

D Q

Q

CLK

D Q

Q

A

B

y

x

3434


State Equations

D Q

Q

CLK

D Q

Q

A

B

y

x

A(t+1) = DA

= A(t) x(t)+B(t) x(t)

= A x + B x

B(t+1) = DB

= A’(t) x(t)

= A’ x

y(t) = [A(t)+ B(t)] x’(t)

= (A + B) x’

3535


State Table (Transition Table)

D Q

Q

CLK

D Q

Q

A

B

y

x

A(t+1) = A x + B x

B(t+1) = A’ x

y(t) = (A + B) x’

Present State

InputNext State

Output

A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

t+1 tt

0 0 00 1 00 0 11 1 00 0 11 0 00 0 11 0 0

3636


State Table (Transition Table)

D Q

Q

CLK

D Q

Q

A

B

y

x

A(t+1) = A x + B x

B(t+1) = A’ x

y(t) = (A + B) x’

Present State

Next State Output

x = 0 x = 1 x = 0 x = 1

A B A B A B y y0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 01 1 0 0 1 0 1 0

t+1 tt

3737


State Diagram

D Q

Q

CLK

D Q

Q

A

B

y

x

0 0 1 0

0 1 1 1

0/0

0/1

1/0

1/0

1/0

1/0 0/10/1

AB input/output

Present State

Next State Output

x = 0 x = 1 x = 0 x = 1

A B A B A B y y

0 0 0 0 0 1 0 0

0 1 0 0 1 1 1 0

1 0 0 0 1 0 1 0

1 1 0 0 1 0 1 0

3838


D Flip-Flops

Example: D Q

Q

x

CLK

yA

Present State

InputNext State

A x y A0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

01101001

0 100,11 00,11

01,10

01,10

A(t+1) = DA = A x y

3939


JK Flip-Flops

Example:

J Q

QK

CLK

J Q

QK

x

A

B

JA = B KA = B x’

JB = x’ KB = A x

A(t+1) = JA Q’A + K’A QA

= A’B + AB’ + AxB(t+1) = JB Q’B + K’B QB

= B’x’ + ABx + A’Bx’

Present State

I/PNext State

Flip-FlopInputs

A B x A B JA KA JB KB

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1 0

0 0 0 1

1 1 1 0

1 0 0 1

0 0 1 1

0 0 0 0

1 1 1 1

1 0 0 0

0 1

0 0

1 1

1 0

1 1

1 0

0 0

1 1

4040


JK Flip-Flops

Example:

J Q

QK

CLK

J Q

QK

x

A

BPresent State

I/PNext State

Flip-FlopInputs


0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1 0

0 0 0 1

1 1 1 0

1 0 0 1

0 0 1 1

0 0 0 0

1 1 1 1

1 0 0 0

0 1

0 0

1 1

1 0

1 1

1 0

0 0

1 1

0 0 1 1

0 1 1 0

1 0 1

0

1

00

1

4141


T Flip-Flops

Example:

TA = B x TB = xy = A B

A(t+1) = TA Q’A + T’A QA

= AB’ + Ax’ + A’BxB(t+1) = TB Q’B + T’B QB

= x B

A

B

T Q

QR

T Q

QR

CLK Reset

xy

Present State

I/PNext State

F.FInputs

O/P

A B x A B TA TB y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0

0 1

0 0

1 1

0 0

0 1

0 0

1 1

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

0

0

0

0

0

0

1

1

4242


T Flip-Flops

Example:

A

B

T Q

QR

T Q

QR

CLK Reset

xy

Present State

I/PNext State

F.FInputs

O/P

A B x A B TA TB y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0

0 1

0 0

1 1

0 0

0 1

0 0

1 1

0 0

0 1

0 1

1 0

1 0

1 1

1 1

0 0

0

0

0

0

0

0

1

1

0 0 0 1

1 1 1 0

0/01/0

0/0

1/0

1/0

1/1

0/00/1

4343

Mealy and Moore ModelsMealy and Moore Models

The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15).

● The outputs may change if the inputs change during the clock pulse period.

♦ The outputs may have momentary false values unless the inputs are synchronized with the clocks.

The Moore model: the outputs are functions of the present state only (Fig. 5-20).

● The outputs are synchronous with the clocks.

4444


Fig. 5.21 Block diagram of Mealy and Moore state machine

4545


Present State

I/PNext State

O/P

A B x A B y0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0

MealyMealy

For the same statestate,the outputoutput changes with the inputinput

Present State

I/PNext State

O/P

A B x A B y0 0 0 0 0 00 0 1 0 1 00 1 0 0 1 00 1 1 1 0 01 0 0 1 0 01 0 1 1 1 01 1 0 1 1 11 1 1 0 0 1

MooreMoore

For the same statestate,the outputoutput does not change with the inputinput

4646

Moore State DiagramMoore State Diagram

State / Output

0 0 / 0 0 1 / 0

1 1 / 1 1 0 / 0

0

1

1

1

00

01

4747

State Reduction and AssignmentState Reduction and Assignment

State Reduction Reductions on the number of flip-flops and the number of gates.

● A reduction in the number of states may result in a reduction in the number of flip-flops.

● An example state diagram showing in Fig. 5.25.

Fig. 5.25 State diagram

4848

State ReductionState Reduction

● Only the input-output sequences are important.

● Two circuits are equivalent

♦ Have identical outputs for all input sequences;

♦ The number of states is not important.

Fig. 5.25 State diagram

State:a a b c d e f f g f g a

Input:0 1 0 1 0 1 1 0 1 0 0

Output:

0 0 0 0 0 1 1 0 1 0 0

4949

Equivalent states

● Two states are said to be equivalent

♦ For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.

♦ One of them can be removed.

5050

Reducing the state table

● e = g (remove g);

● d = f (remove f);

5151

● The reduced finite state machine

State:a a b c d e d d e d e a

Input:0 1 0 1 0 1 1 0 1 0 0

Output:

0 0 0 0 0 1 1 0 1 0 0

5252

● The unused states are treated as don't-care condition fewer combinational gates.

Fig. 5.26 Reduced State diagram

5353

State AssignmentState Assignment

State Assignment

To minimize the cost of the combinational circuits.

● Three possible binary state assignments. (m states need n-bits, where 2n > m)

5454

● Any binary number assignment is satisfactory as long as each state is assigned a unique number.

● Use binary assignment 1.

5555

Design Procedure Design Procedure

Design Procedure for sequential circuit

● The word description of the circuit behavior to get a state diagram;

● State reduction if necessary;

● Assign binary values to the states;

● Obtain the binary-coded state table;

● Choose the type of flip-flops;

● Derive the simplified flip-flop input equations and output equations;

● Draw the logic diagram;

5656

Design of Clocked Sequential CircuitsDesign of Clocked Sequential Circuits

Example:

Detect 3 or more consecutive 1’s

S0 / 0 S1 / 0

S3 / 1 S2 / 0

0

1

1

0 0

1

0

1

State A BS0 0 0

S1 0 1S2 1 0

S3 1 1

5757


Example:


Present State

InputNext State

Output

A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1

S0 / 0 S1 / 0

S3 / 1 S2 / 0

0

1

1

0 0

1

0

1

5858


Example:


Present State

InputNext State

Output

A B x A B y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1

A(t+1) = DA (A, B, x)

= ∑ (3, 5, 7)

B(t+1) = DB (A, B, x)

= ∑ (1, 5, 7)

y (A, B, x) = ∑ (6, 7)

Synthesis using DD Flip-Flops

5959

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F. F.F.

Example:


DA (A, B, x) = ∑ (3, 5, 7)

= A x + B x

DB (A, B, x) = ∑ (1, 5, 7)

= A x + B’ x

y (A, B, x) = ∑ (6, 7)

= A B


B

0 0 1 0

A 0 1 1 0x B

0 1 0 0

A 0 1 1 0xB

0 0 0 0

A 0 0 1 1x

6060

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F. F.F.

Example:


DA = A x + B x

DB = A x + B’ x

y = A B


D Q

Q

A

CLK

x

BD Q

Q

y

6161

Flip-Flop Excitation TablesFlip-Flop Excitation Tables

Present State

Next State

F.F.Input

Q(t) Q(t+1) D0 00 11 01 1

Present State

Next State

F.F.Input

Q(t) Q(t+1) J K0 00 11 01 1

0 0 (No change)0 1 (Reset)

0 x

1 x

x 1

x 0

0

1

0

1

1 0 (Set)1 1 (Toggle)0 1 (Reset)1 1 (Toggle)0 0 (No change)1 0 (Set)

Q(t) Q(t+1) T0 00 11 01 1

0

1

1

0

6262

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F. F.F.

Example:


Present State

InputNext State

Flip-FlopInputs


0 0 0 0 00 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 11 1 0 0 01 1 1 1 1

0 x0 x0 x1 xx 1x 0x 1x 0

JA (A, B, x) = ∑ (3)dJA (A, B, x) = ∑ (4,5,6,7)KA (A, B, x) = ∑ (4, 6)dKA (A, B, x) = ∑ (0,1,2,3)JB (A, B, x) = ∑ (1, 5)dJB (A, B, x) = ∑ (2,3,6,7)KB (A, B, x) = ∑ (2, 3, 6)dKB (A, B, x) = ∑ (0,1,4,5)

Synthesis using JKJK F.F.

0 x1 xx 1x 10 x1 xx 1x 0

6363

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F. F.F.

Example:


JA = B x KA = x’

JB = x KB = A’ + x’

Synthesis using JKJK Flip-Flops

B

0 0 1 0

A x x x xx

B

x x x x

A 1 0 0 1x

B

0 1 x x

A 0 1 x xx

B

x x 1 1

A x x 0 1x

CLK

J Q

QK

x

A

B

J Q

QK y

6464

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F. F.F.

Example:


Present State

InputNext State

F.F.Input

A B x A B TA TB

0 0 0 0 00 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 11 1 0 0 01 1 1 1 1

00011010

Synthesis using TT Flip-Flops01110110

TA (A, B, x) = ∑ (3, 4, 6)TB (A, B, x) = ∑ (1, 2, 3, 5, 6)

6565

Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F. F.F.

Example:


TA = A x’ + A’ B x

TB = A’ B + B x

Synthesis using TT Flip-Flops

B

0 0 1 0

A 1 0 0 1x

B

0 1 1 1

A 0 1 0 1x

A

B

y

T Q

Q

x

CLK

T Q

Q

SEQUENTIAL LOGIC CIRCUIT DESIGN. 1 Sequential Circuits Combinational Circuit Memory Elements Inputs...

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Transcript of SEQUENTIAL LOGIC CIRCUIT DESIGN. 1 Sequential Circuits Combinational Circuit Memory Elements Inputs...