September 22 nd, 2006 MOS-AK Workshop Montreux ETH Swiss federal Institute of Technology Zurich TCAD...

September 22nd, 2006

MOS-AK Workshop

Montreux

ETHSwiss federal Institute of TechnologyZurich

TCAD for compact modeling

Luca Sponton, Paul Pfaeffli and Lars Bomholt

2Luca SpontonETHSwiss federal Institute of TechnologyZurich

Outline

Introduction Bringing process information to design PCM example Process-aware SPICE compact models Challenges for TCAD-generated models Summary


Motivation

The impact of variation on product performance and yield grows Increasing difficulty in keeping strict statistical control on a

process

Be able to design robustness against process variation into the product

Be able to optimize manufacturing for product performance

Bring process variations to circuit simulation and design


Parametric yield loss is caused by variations:• Increasing margins would

substantially diminish the advantages of technology scaling.

Corner models could bring to a too conservative design

Corner models do not allow any understanding of the process variation impact on a design

Both design and process may contribute to the deviations.

Variations Lead to Yield Loss


Outline



Traditional flow: data from measurements

E-TEST DATA

SPICE PARAMETER EXTRACTION

CORRELATION ANALYSIS

PRINCIPAL COMPONENT ANALYSIS

GENERATE EQUATIONS

MONTECARLO SIMULATION

PROS:

• Well established methodology• Automatic procedure• Captures most of variability

CONS:

• Components are not correlated with underlying process variations

• Overestimates• Parameters can assume unphysical values

• Stable process flow


Advantages of TCAD extracted models

TCAD is the ideal tool to characterize process variations

TCAD simulations are accurate, do not drift during time and are available in an early stage of technology development

It is possible to access process parameters and device characteristics that are not controlled or measured accurately in manufacturing

It is cheaper than running large design of experiments on silicon

How do we bring process information into design?


Bringing process to circuit simulation with TCAD

Process variability

Device characteristics

Compact models

Full circuit

-Process simulation

- DOE of process variations

- Device simulations


Process compact models (PCM)

PCM creates a link between the space of process variables and device characteristics through a response surface model

Device Characteristic = f(Process Characteristics) Let us try to do the same for SPICE parameters:

Vth0=f1(Tox, Ch_Dose, Ha_dose, Spike_T, …)

u0=f2(Tox, Ch_Dose, Ha_dose, Spike_T, …)

…

Physically meaningful parameters, that vary smoothly with process variations, allow for a better quality of PCM


Process compact model for SPICE parameters

Process variables {Pi}

DOE, n experiments

Process simulation n devices

Device simulations

SPICE parameters extraction

N SPICE model cards

PCM generation PCM

Set of Process variables {P}

SPICE model card


Consistent extraction from TCAD

Nominal SPICE model obtained from nominal process Small subset of parameters extracted to take into account

process variability Automatic BSIM3 SPICE parameters extraction for every

device in the DOE Accurate models obtained by a combined local optimization +

global refinement Use of bounded optimization to ensure physical meaning of

extracted parameters

Parameters extraction

for whole DOE

Extraction of Nominal

device

PCMextraction

Selection of Parameters

subset

Use Local Optimization


Outline



PCM Example

Full factorial DOE on gate length, gate oxide thickness, Halo implant dose & tilt and channel dose

Nominal device extracted, then a subset of 16 SPICE parameters is used to account for process variations: vth0, Ua, Uc, k1, k2, Voff, Nfactor, eta0,Delta, Vsat, a0, Pclm, pdiblc1, Keta

Computational time is ~ 3h for each process variation. Experiments can be parallelized on a cluster of computers


Consistent extraction

Extracted parameters follow process variations thanks to the local optimization and bounded extraction algorithm


Consistent extraction

Physical meaning of parameters is maintained by the extraction strategy chosen, accuracy may suffer compared to global optimization due to the limited set of parameters chosen

From the full set of SPICE cards a PCM is generated


PCM generation

PCM generated SPICE model accuracy is good using neural networks as response surfaces. Simple polynomial response surface models do not give a good accuracy.


PCM generated SPICE parameters

Predicted models show some error when compared to TCAD simulations: we trade some accuracy for getting the process-design link


Consistent extraction from TCAD

PROS:

• Early availability of models • Physically meaningful SPICE parameters • Consistent extraction and PCM allow linking directly SPICE parameters to process variations

CONS:

• Nominal device extraction time consuming • Automated extraction flow has to be optimized on the process• Accuracy worse than with global ‘unbounded’ optimization• Model prediction introduces additional error


Outline

Introduction Process variations to circuit variations PCM example Process-aware SPICE compact models Challenges for TCAD-generated models Summary


Process-aware SPICE models: PARAMOS

Different approach: embedding process parameters directly into the SPICE model

Extraction of SPICE parameters including PCM parameters through extraction from an entire DOE reflecting the process conditions

Parameter definition:

With Mi SPICE parameter, Pi process parameter Extraction tool: Paramos

σ0

0

~

~

jjj

j n

njijnii

PPP

PaMM

−=

+= ∑∑


Process-Aware SPICE Model: PARAMOS

TCAD simulations• Generate I-V / C-V database

for each process parameter set {Pi}

Global SPICE extraction• Create a compact model

with process parameters as SPICE library parameters.

• Polynomial fitting

• Vth = Vth0 + ai(n)Pi

n

• Voff = Voff0 + bi(n)Pi

n

All curves and coefficients are extracted in a single optimization step

Manufacturing

TCAD (process & device)

Calibration

{ Pi }

I-V, C-V database {Pi}

Process-Aware Compact SPICE Model {Pi}

SPICE Extraction

{Pi} accessible for circuit simulations!

Courtesy of S. Tirumala, Synopsys


Case Study

Typical 90 nm Technology• Tox = 16 A, Lg = 65 nm,

Vdd = 1.0 V

Normalized variation pi:

pi = (Pi - Pi0)/(Pimax - Pi0)

Range of pi : from -100% to +100% Device

Idsat(A/m)

Vt-Lin(V)

Ioff(nA/m)

NMOS 640 0.36 2.35

PMOS 241 0.32 0.67


Process ParametersVariation

Range

PoxGate oxidation temperature

±10oC

Phn,p Halo implant dose ±1e12 cm-2

Pst Spike temperature ±10oC

PvtVt Adjust implant dose

±1e12 cm-2

PlgGate length deviation (L)

±5 nm


Quality of Compact Model Extraction

Excellent fit for I-V curves (rms error < 5%) Excellent fit for Vt-Lin and Idsat ( <4%) Acceptable fit for Ioff (<40%)

-40

-30

-20

-10

0

10

20

30

40

50

Vt-Lin Idsat

Ioff

difference between TCAD and Spice Simulations (%)

1.24%

-1.43%

1.77%

-3.44%

30.88%

-35.7%-40

-30

-20

-10

0

10

20

30

40

50

Vt-Lin Idsat

Ioff

difference between TCAD and Spice Simulations (%)

1.24%

-1.43%

1.77%

-3.44%

30.88%

-35.7%

Id-Vd Curves Model Vs TCAD

0.E+00

1.E-04

2.E-04

3.E-04

4.E-04

5.E-04

6.E-04

7.E-04

Drain Bias (V)

Drain Current (A)

TCADModel

5.E-16

6.E-16

7.E-16

8.E-16

9.E-16

1.E-15

1.E-15

1.E-15

-2.00 -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00

Gate Bias

Total Gate Cap (F)

C-V

TCAD simModel



Delay Variation and Sensitivity

Delay is most sensitive to Tox variation .• Varies from -10% to +24% as pox changes -100% to +100%

The response to gate length variation (L) is relatively weak• - 5% to +5% across the full range of L variation.

Variation around nominal process is non-symmetrical• -10 % vs 24% for min and max variation.

-20%

-10%

0%

10%

20%

30%

-100%-50%

0% 50% 100%

Delay Variation

Normalized process variation

Gate oxidation temperature (P ox)

n-Halo implant (Phn)

? (L P lg)

-20%

-10%

0%

10%

20%

30%

-100% -50%0% 50% 100%

Delay Variation

Normalized process variation

(Gate oxidation temperature Pox)

n- (Halo implantPhn)

? (L P lg)

Input rise



Outline

Introduction Process variations to circuit variations Extraction techniques for variability Process-aware SPICE compact models Challenges for TCAD-generated models Summary


Challenges for TCAD-generated models

There are historically some missing links between TCAD and compact model extraction [1]:

• Lithography effects on gate shape• Isolation formation (STI or LOCOS)• Outdiffusion of implanted dopant• …

All these effects are 3D effects not easily accountable for with 2D simulations

[1] C.C. McAndrews, “Predictive technology characterization, missing links between TCAD and compact modeling”, Proc. of SISPAD, 2000


Bridging the gap: lithography

Lithography effects on gate shape:

L.Sponton et al., “A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology”, Proc. Of SISPAD, Sept. 2006


Bridging the gap: INWE

Narrow width effect on the transistor characteristics


Summary

There is a growing need to understand the effect of process variation on circuit performance

Using calibrated TCAD simulations it is possible to study the effects of slight process variation on device characteristics

Process-aware SPICE models offer a way to bring process variation information to the design sphere

With standard BSIM models it is necessary to trade some accuracy for being able to properly and consistently consider these variations


Acknowledgements

The authors would like to thank people at Synopsys and ETH Zurich for their contribution to the work, in particular Dipankar Pramanik, Shridhar Tirumala, Sathya Krishnamurthy, Yuri Mahotin

Part of this work was financed through the KTI Project “Parametric Design and Analysis for Semiconductor Technology Computer Aided Design (PARA-TCAD)”

September 22nd, 2006

MOS-AK Workshop

Montreux

ETHSwiss federal Institute of TechnologyZurich

Thanks for your attention

Luca SpontonSwiss Federal Institute of Technology (ETH)Integrated Systems Laboratory

Phone: +41 44 632 7786 (ETH)Phone: +41 44 567 1555 (SYNOPSYS) Email: [email protected]

September 22 nd, 2006 MOS-AK Workshop Montreux ETH Swiss federal Institute of Technology Zurich TCAD...

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