Security C – TSMC Secret 1 Semiconductor Technology and Application 吳振銘...
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Transcript of Security C – TSMC Secret 1 Semiconductor Technology and Application 吳振銘...
Security C –TSMC Secret
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Semiconductor
Technology and Application
吳振銘台積電六廠製程整合部經理
2010/03/24
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Semiconductor Brings Fun to Your Life- History, Application and Market
What is Transistor How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution
What the Semiconductor Fabs Care- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
A Day’s Work in tsmc
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Semiconductor Brings Fun to Your Life- History, Application and Market
What is Transistor How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution
What the Semiconductor Fabs Care- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
A Day’s Work in tsmc
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Biggest Semiconductor Players
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Semiconductor Brings Fun to Your Life- History, Application and Market
What is Transistor How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution
What the Semiconductor Fabs Care- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
A Day’s Work in tsmc
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Wet etch
Physical dry etch
Chemical dry etch
Chemical + Physical
4 Types of Etch
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Technology Evolution
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Te
ch
no
log
y G
en
era
tio
n (
nm
)
130
90
65
45
32
‘00 ‘02 ‘04 ‘06 ‘08 ‘10 ‘12
00 ITRS
01 ITRS
05 ITRS
TSMC
ITRS: International Technology Roadmap for Semiconductors
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Semiconductor Brings Fun to Your Life- History, Application and Market
What is Transistor How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution
What the Semiconductor Fabs Care- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
A Day’s Work in tsmc
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Imperfect Fabrication Process
• Mask making dust, focusing
• Growing oxide warping in furnace, uneven reactions
• Resist over exposure, not hardened enough
• Etching overetch of resist and/or oxide
• Lateral diffusion affects transistor channel lengths
• Multiple layers mask alignment
• Packaging bonding wires to pins of package
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Yield Improvement
• Defect reduction
• Process window characterization
• Process weakness
• Sweet spot
• Hardware control / PM / Lifetime
• Design improvement
• Innovation
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Manufacturing
DL Daily Management
DL Performance Enhancement
DL Efficiency Improvement
Improve Tool Productivity
Manage Shop Floor Scheduling & Dispatching
6 Manufacturing Operation Module
Manage/Predict WIP Profile
Capacity Management
DL & IDL Recruiting, Training, Retaining & Inspiring
Quality System Management & Logistic Support
Computer Integration Manufacturing
Automation Material Handling System
Integrated Factory Automation
Wafer Production Planning
On Time Delivery
Production Cycle Time ControlPlanning
Tps
MFG CIMModule
DL Daily Management
DL Performance Enhancement
DL Efficiency Improvement
Improve Tool Productivity
Manage Shop Floor Scheduling & Dispatching
6 Manufacturing Operation Module
Manage/Predict WIP Profile
Capacity Management
DL & IDL Recruiting, Training, Retaining & Inspiring
Quality System Management & Logistic Support
Computer Integration Manufacturing
Automation Material Handling System
Integrated Factory Automation
Wafer Production Planning
On Time Delivery
Production Cycle Time ControlPlanning
Tps
MFG CIMModule
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Process Integration Engineer
Process Related and Modules
Process Related and Modules
FEOLBEOL
Q-time, Rework, KLAProcess control CD, overlay, thicknessDevice/ Product characteristic
PhotoEtchThin FilmDiffusionIon ImplantationCMPClean
Multilevel InterconnectSTI, SalicideContact/ Via, MetalPassivationAlignment mark
Technology readiness
New technology development
New product & experiment
Process parameters/SPEC setting
Product and Process qualification
Quality Guarantee
PCM (Process Control Monitor)
Cpk improvement
Defect inspection and reduction
Cp/FT yield improvement
Customer satisfaction
Customer satisfaction index
Engineering notice and lot handling
WAT & QC outgoing inspection
Customer satisfaction
Wafer In-Process
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How We Work on Fast Time-to-Market
Business Engagement Development
Qualification
RD/Fab Joint Technology Meetings
(Yield, Defect, Major issues..) Joint Task Forces for Critical Modules Enlarge Manufacturing Window Joint Effort for Defect Reduction
One Ramp Team: RD and Fab 1st Si Success of Customer NTOs Continuous Yield Improvement Capacity Build-up and Release
Ramp Up
Joint Review for Process Frozen
Process/Product Qualification Process Characterization Process Control Review
Manufacturing Readiness
Customized request MKT/RD/Fab Joint discussion New Tech/tool selection Fab’s Super Highway Service
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Semiconductor Brings Fun to Your Life- History, Application and Market
What is Transistor How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution
What the Semiconductor Fabs Care- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
A Day’s Work in tsmc
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Starting/Ending on Daily Hand over
上班時間08:30 19:30
0810
下班時間Goal
~09:00完成交接
17:00
下午交接17:30
完成交接12:00休息
長官關心Urgent casehandling
Daily work
PIEPIE• Hold lot review and key lots status
• Production yield status
• WAT/Line scrap wafer review
• M1/IM/Final WAT or special module trend chart review
• Customer response
• Urgent case status update
• Trouble tool review & recovery plan
• PM arrangement
• RTM chart review
• SPC trend chart review
• On-duty follow up
• Hold lot review
• Inline, defect case and tool alarm review
• Tool alarm lot or CD/THK OOC lot handling
• Tool release status and WPH improvement
• SPC trend chart review -- CD, THK, E/R, Rs
• Low yield (dog tool) finding
• OCAP follow up
• Daily Move
• Efficiency index
• T/R and Cycle time
• Tool total capacity for WIP
• Make up delay WIP
• Hold lots arrangement
• Special lots support
PEPE
EEEE
MFGMFGPCPCMPEMPE
QCQCCSVCSV
PIEPIE• Hold lot review and key lots status
• Production yield status
• WAT/Line scrap wafer review
• M1/IM/Final WAT or special module trend chart review
• Customer response
• Urgent case status update
• Trouble tool review & recovery plan
• PM arrangement
• RTM chart review
• SPC trend chart review
• On-duty follow up
• Hold lot review
• Inline, defect case and tool alarm review
• Tool alarm lot or CD/THK OOC lot handling
• Tool release status and WPH improvement
• SPC trend chart review -- CD, THK, E/R, Rs
• Low yield (dog tool) finding
• OCAP follow up
• Daily Move
• Efficiency index
• T/R and Cycle time
• Tool total capacity for WIP
• Make up delay WIP
• Hold lots arrangement
• Special lots support
PEPE
EEEE
MFGMFGPCPCMPEMPE
QCQCCSVCSV
PCPCMPEMPE
QCQCCSVCSV
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TSMC Job Function Job
FunctionMajor Job Description &
Career Development適合系所 適合原因
PIE(Process
Integration Engineer)
量產產品製程整合,出貨規格,良率分析及客戶服務。研發新產品製程,規格,品質可靠度及客戶服務。工作須與 Module , RD , QR , CSV.. 互相溝通配合,多方面學習。
電機 , 電子,材料,物理,化工 .. 等理工科系。
半導體電性 , 物性及工程分析背景。
PE (Process Engineer)
研製機台的製程條件 , 符合產品的品質要求。建立製程條件的監控方法 , 管制製程穩定性。開發、研究、改善生產流程。
材料,化工,物理, 化學,... 等理工相關科系。
半導體製程的工作大量應用材料、物理、化學、機械性質的知識與使用最先進的分析儀器。
EE (Equipment Engineers)
研發改造機台,符合先進製程需求。 持續研究開發機台生產力。追求成本下降的機會。 維護機台穩定性。
機械,電子, 電機等理工相關科系。
高度精密的半導體設備需要有清晰的邏輯概念與機構、設計、控制等相關知識,才能發揮最大效果。
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One Vital Day in Fab - Engineer’s Daily Life -
Hand over meeting
Hand over meeting
Hand over meeting
Hand over meeting
Production meeting
Production meeting
EN & LHexecution
EN & LHexecution
Customer response
Customer response
customermeeting
customermeeting
Yield improvement
Yield improvement
PIEMFGPE/EE
DailyTrend chart
DailyTrend chart
Hold lots handling
Hold lots handling
SPC improvement
SPC improvement
Line excursion
Line excursion
FCCBFCCB
X-Deptmeeting
X-Deptmeeting
EKM & Suggestion
EKM & Suggestion
Technique Board
Technique Board
New project& CIT
New project& CIT
Trouble shooting
Trouble shooting
Costreduction
Costreduction
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The TSMC Value Proposition: Our Trinity of Strengths
客戶的成功客戶的成功
先進技術 卓越製造 客戶夥伴關係
• 先進技術• 主流製程
• 產能領導者• 立即性與彈性• 最佳的良率與生產週期
• 快速量產
• 專業晶圓製造模式
• 全面性解決方案• 客戶服務導向提供最大整體利益
• 長期、雙贏、信賴
產能與財務優勢
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專業的晶圓製造與服務,改變半導體業專業垂直分工的商業模式
台積公司改變世界半導體業遊戲規則台積公司改變世界半導體業遊戲規則
System/IC Design
Before Before 19861986
System/IC Design
System/IC Design
晶圓製造(Foundry)
封裝 , 測試
1990s1990s After 2000After 2000
System/IC Design
System Design / IC Design
晶圓製造
設計服務
IP 供應商
封裝 , 測試
台積電台積電
台積電台積電
晶圓製造(Fab)
封裝 , 測試
晶圓製造(Fab)
封裝 , 測試
晶圓製造(Fab)
封裝 , 測試
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台積公司價值鏈台積公司價值鏈客戶客戶
核心能力核心能力
系統
產品
設計
光罩
晶圓測試
總測試
台積公司台積公司核心能力核心能力
設計服務設計服務
後端服務後端服務
智財權 (IP)/ 資料庫 (Library)
電子設計自動化 (EDA)設計執行
技術製造
錫鉛凸塊 (Bumping)覆晶 (Flip Chip)
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Thank You