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1201/159.233 ScMANInternal

MASSEY UNIVERSITYMANAWATU CAMPUS

EXAMINATION FOR159.233 COMPUTER SYSTEMS

Semester One - 2012

Time allowed: THREE (3) hours

THIS IS A CLOSED BOOK EXAMINATION

ANSWER ALL QUESTIONS

SECTION AFourteen multi-choice questions – each worth 2 marks 28 marks

Record your answers to the questions in Section A on the Scantron Card provided.

SECTION BThree questions – each worth 24 marks 72 marks

Write your answers to the questions in Section B in the Blue Answer Booklet provided.

Total: 100 marks

Marks for each question are shown in brackets after the question, like this [8 marks]

An appendix of useful information is attached.

Note that in some of the questions in this exam, the abbreviations hi and lo may have been used to signify logic high (usually 5V) and logic low (0V) signals respectively.

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SECTION AANSWER ALL 14 QUESTIONS IN THIS SECTION

Each question is worth 2 marks

Some of the multi-choice questions are in the format of a table. In each case, there is an introductory clause at the top left corner of the table, One of

the two clauses beside it is correct, and one of the two clauses below it is correct. On your Scantron card, mark the letter (A-D) that is in the correct row AND the

correct column

QUESTION 1

The term abstraction

refers to a modularisation technique that is used to simplify the design of computer systems

is a (negative) term that describes the difficulty of computer systems

refers to a design technique that results in users being able to read and write files without having to know about sectors and tracks on hard disks

A B

refers to a design technique that requires users to know about sectors and tracks on hard disks when they (or their software) perform a read or write operation

C D

[2 marks]

QUESTION 2

Benchmarks

are generally very short pieces of code that are run millions of times to get reliable statistical data

are standard tasks whose execution time is measured and are used for comparing the performance of computers

are used because design is so complex that it is difficult to predict system behaviour from first principles

A B

are sophisticated mathematical models of computers, whose parameters can be changed so to predict the performance without the need to actually build the computer

C D

[2 marks]

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QUESTION 3

In the IEEE 754 standard for floating-point numbers

a 32-but number has a mantissa of 23 bits and an exponent of 8 bits

a 32-bit number has an exponent of 23 bits and a mantissa of 8 bits

the mantissa is normalised so that the most significant bit in the mantissa field is 1

A B

the mantissa is normalised, and the most significant bit is not stored

C D

[2 marks]

QUESTION 4

In an Algorithmic State Machine

roundtangles (round-ended rectangles) contain a list of outputs that are only set to TRUE if an immediately preceding test returns the value TRUE

roundtangles (round-ended rectangles) contain a list of outputs that are only set to TRUE if an immediately preceding conditional test is fulfilled (which may mean that the test is TRUE, or it may mean that the test if FALSE)

a state may be empty (specify no output) to indicate the passing of time

A B

at least one rectangle (sharp-cornered or round-ended) states must have at least one output

C D

[2 marks]

QUESTION 5

In a computer architecture based on a datapath

there are often registers between stages in the datapath so that data transfer between stages can be synchronised

there are often registers between stages in the datapath so that results of calculations can be stored for use by later instructions

all the operations in an instruction occur on a single clock period

A B

the operations in an instruction occur in sequence, on a number of clock periods

C D

[2 marks]

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QUESTION 6

The controller for a computer processor

generates control signals for the I/O devices, as specified by the elements of the datapath

generates control signals that control the elements of the datapath according to the requirements of the current instruction

is usually a (highly complex) combinatorial circuit A B

is often based on the concept of an ASM C D

[2 marks]

QUESTION 7

Hazards cannot occur in pipeline architectures

have to be guarded against in computers with a pipeline architecture

can always be handled by a feedback path that “pipes” the result of a calculation back to the input of the ALU so that it is available to the next instruction on the next clock cycle, even though the current instruction has not yet terminated

A B

can be prevented by inserting stalls into the datpath C D

[2 marks]

QUESTION 8

In cache systemstotal CPU time = (useful execution cycles + stall cycles) x cycle time

total CPU time = (useful execution cycles + cycle time) x stall cycles

memory stall cycles = (memory accesses / program) x miss rate x miss penalty

A B

memory stall cycles = (memory accesses / program) x miss rate / miss penalty

C D

[2 marks]

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QUESTION 9

In virtual memory systems virtual pages can go anywhere in memory

virtual pages go in regions of memory that share the first n bits of address (where n is typically between 10 and 20 bits)

a single page table is shared by all the currently active processes

A B

each process has its own page table C D

[2 marks]

QUESTION 10

After the following program has executed, what is the value in the accumulator?

start mov r7,#10 mov a,r7 add a,#7 anl a,#$7 orl a,#4 mov pcon,#2

(A) 1(B) 5(C) $17(D) $23

[2 marks]

QUESTION 11

The OV bit is used for checking:

(A) interrupt overflow(B) unsigned arithmetic overflow(C) stack overflow(D) signed arithmetic overflow

[2 marks]

QUESTION 12

The method of repeated checking the state of a variable is known as:

(A) using interrupts(B) using polling(C) using indirection(D) using register-based addressing

[2 marks]

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QUESTION 13Interrupt handlers are different from ordinary subroutines because …

(A) when they’re called is unpredictable(B) which instructions will be used is only known at run-time, not assembly time(C) the hardware can disable interrupt handlers if the CPU is busy(D) repeated arithmetic operations can result in stack overflow

[2 marks]

QUESTION 14

If zero is represents False and 1 represents True, which relational operator does the following subroutine calculate?

xxx clr c subb A,B jz L1 jc L1 mov a,#0 sjmp doneL1 mov a,#1done ret

(A) A < B(B) A <= B(C) A >= B(D) A > B

[2 marks]

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SECTION BANSWER ALL THREE (3) QUESTIONS IN THIS SECTION

Each question is worth 24 marks.

QUESTION 15

(a) Explain the meaning of the term three address architecture and draw the layout of the MIPS R-type instruction, labelling each of the fields, and explaining its function.

[6 marks]

(b) A computer with a clock rate of 1GHz has two compilers, X and Y, and three classes of instruction, A, B, and C.

Instructions of type A take 1 clock cycle. Instructions of type B take 2 clock cycles.Instructions of type C take 3 clock cycles.

For a given program in a High-Level Language, the machine code produced by compiler X requires

4 billion instructions of type A2 billion instructions of type B1 billion instructions of type C.

whereas the machine code produced by compiler B requires6 billion instructions of type A1 billion instructions of type B1/3 billion instructions of type C

(where a billion = 109)

Calculate the execution time for the program when it is compiled by compiler A and the execution time for the program when it is compiled by compiler B.

[6 marks]

(c) Calculate the number of instructions required to execute the program when it is compiled by compiler A and the number of instructions required to execute it when it is compiled by compiler B.

[6 marks] (d) In an architecture that clocks data through a path, what formula would you use to

determine whether it was worth cutting a slow stage in two? Illustrate your answer by considering two architectures. Machine A has 5 stages (before any stages are cut in two) and machine B has 6 stages (before any stages are cut in two).

For both machines, the slowest stage takes 6ns, and after that stage has been cut in two, the slowest stage takes 5ns.

[6 marks]

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QUESTION 16

(a)

Is the datapath shown above suitable for implementation as a single-cycle architecture or as a pipelined architecture? What feature(s) of the diagram led you to this conclusions, and why?

[6 marks]

(b) What happens during the first clock period of the MIPS instruction cycle? How does this differ from one instruction to another, and why?

[6 marks]

(c) You are the chief architect in a computer design company, responsible for the design of a new computer. Two of your engineers have produced alternative designs. One has a restricted number of instructions and a set of instructions that have all been squeezed into one 32-bit word. The other has a large instruction set, with many instructions designed for complex functions; some of the instructions are spread over more than one 32-bit word. What argument would you use to explain to your engineers why you prefer one of the architectures over the other?

[6 marks]

(d) Explain how the Least Recently Used algorithm is used as a Block Replacement Policy in caching. What simpler approach does it improve upon?

[6 marks]

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QUESTION 17

(a) Write fragments of 8051 assembler code that have the same effect as the following lines of code. If they’re needed, you can assume the libraries SerialIO.51 and prtCodeM.51 are available.

(i) x = 10y = 3 - x

(ii) x = 0sum = 0while (x < 10) { sum = sum + x x = x + 1}

(iii) if A == y or x != y then print(‘mismatch’)

[8 marks]

(b) ORG and EQU are pseudo-operations that do not generate code but are instructions to the assembler. Explain what they do and provide examples of their use.

[2 marks]

(c) The getch() subroutine has the following definition:

getch: jnb ri,getch mov a,sbuf clr ri ret

Explain what each line does and the function of ri and sbuf.[4 marks]

(d) The following program uses the prtMsg subroutine, which should print a zero-terminated string that starts at $50 in data memory .

Start mov sp,#0 ; Setup stack ljmp prtMsg ; print the message mov pcon,#2 ; and halt

prtMsg: mov r0,$50 mov a,r0 jz done lcall putch inc r0 sjmp next done ret

The code contains several errors. Identify them and write a corrected version.[5 marks]

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(e) Write an isDigit(ch) function that, when passed a byte as a parameter, returns zero

if the byte is NOT a digit character (‘0’ – ‘9’) and a non-zero value otherwise. The byte being tested should not be altered by the function call. Be sure to define

how the parameter is passed to the function, how the result of the function is returned. The returned value can be either a

bit or a byte, but be sure to define which.[5 marks]

+ + + + + + + +

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APPENDIX: 8051 ARCHITECTURE REFERENCE

Program Counter: 16 bit register restricted to 0000H -> 07FFFH

Special Function Registers (SFR) Space:Byte

addressName Description Bits

("---" NOT bit addressable)80H P0 Port 0 bit addressable: P0.7 -> P0.081H SP Stack Pointer ---82H DPL Low byte of DPTR ---83H DPH High byte of DPTR ---87H PCON Power control -88H TCON Timer control TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT089H TMOD Timer mode control ---8AH TL0 Timer 0 low byte ---8BH TL1 Timer 1 low byte ---8CH TH0 Timer 0 high byte ---8DH TH1 Timer 1 high byte ---90H P1 Parallel port 1 Bit Addressable P1.7 -> P1.098H SCON Serial control SM0-SM1-SM2-REN-TB8-RB8-TI -RI99H SBUF Serial buffer ---A0H P2 Port 2 Bit addressable: P2.7-P2.0A8H IE Interrupt Enable EA- - -ES-ET1-EX1-ET0-EX0B0H P3 Parallel port 3 Bit addressable: P3.7 -> P3.0B8H IP Interrupt priority - - -PS -PT1-PX1-PT0-PX0D0H PSW Program Status Word CY-AC-F0-RS1-RS0-OV -F1 -PE0H ACC Accumulator ACC.7 -> ACC.0F0H B B register B.7 -> B.0

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Special Function

Registers*

I/O registers accessed via

memory locations

<-8 bits wide ->D7............D0

$FFSFR ---- $80

Working space for user programs


Interrupt control registerIE: EA Global bit to enable interrupts

ES Serial interrupt (either RI or TI)ETx Clock interrupt on overflow of timer x

Timer control and mode registers - 2 timers 0 and 1TCON: TF0/TF1 Timer overflow flag timers 0/1

TR0/TR1 Timer run control bit. Set by software to switch timer ON

TMOD: mode0-mode1 2 x 4-bit nibbles. Timer 1 = high order nibble, Timer 0 = low order.mode = 0 13 bit timermode = 1 16 bit timermode = 2 8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial

I/O as bit rate (*32). 0FDH in Thx gives 9600bps for 11.059Mhz clock

Serial control registerSCON: SM0-SM1-SM2-REN should be set to 0111 for normal operation

TI set when the character has been transmittedRI set when a character is received

Power control registerPCON: set to 2 will stop the processor

Addressing Modes:Rn Register R0 - R7 of the currently selected register bank.

direct 8-bit internal data location's address. This could be an internal Data RAM location (0-127) or a SFR.

@Ri 8-bit internal Data RAM location addressed indirectly via register R0 or R1

#data 8-bit constant included in instruction.

#data16 16-bit constant included in instruction.

addr11 11-bit destination address. Used by ACALL and AJMP.The branch will be within the same 2K byte page of Program Memory as the first byte of the following instruction.

addr16 16-bit destination address. Used by LCALL and LJMP.A branch can be anywhere within the 2K byte Program Memory address space.

rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the next instruction.

bit Direct addressed bit in internal Data RAM or SFR.

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Arithmetic operations: Byte Cycle C OV ACADD A,Rn Add register to Accumulator 1 1 X X XADD A,direct Add direct byte to Accumulator 2 1 X X XADD A,@Ri Add indirect RAM to Accumulator 1 1 X X XADD A,#data Add immediate data to Accumulator 2 1 X X XADDC A,Rn Add register to Acc. with Carry 1 1 X X XADDC A,direct Add direct byte to Acc. with Carry 2 1 X X XADDC A,@Ri Add indirect RAM to Acc. with Carry 1 1 X X XADDC A,#data Add immediate data to Acc. / Carry 2 1 X X XSUBB A,Rn Subtract reg. from Acc. with borrow 1 1 X X XSUBB A,direct Sub. direct byte from Acc. / borrow 2 1 X X XSUBB A,@Ri Sub. indirect RAM from Acc./ borrow 1 1 X X XSUBB A,#data Sub. immed. data from Acc. / borrow 2 1 X X XINC A Increment Accumulator 1 1INC Rn Increment register 1 1INC direct Increment direct byte 2 1INC @Ri Increment indirect RAM 1 1DEC A Decrement Accumulator 1 1DEC Rn Decrement register 1 1DEC direct Decrement direct byte 2 1DEC @Ri Decrement indirect RAM 1 1INC DPTR Increment Data Pointer 1 2MUL AB Multiply A and B 1 4 0 XDIV AB Divide A by B 1 4 0 XDA A Decimal adjust Accumulator 1 1 X

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Logical operations: Byte Cycle C OV AC

ANL A,Rn AND register to Accumulator 1 1ANL A,direct AND direct byte to Accumulator 2 1ANL A,@Ri AND indirect RAM to Accumulator 1 1ANL A,#data AND immediate data to Accumulator 2 1ANL direct,A AND Accumulator to direct byte 2 1ANL direct,#data AND immediate data to direct byte 3 2ORL A,Rn OR register to Accumulator 1 1ORL A,direct OR direct byte to Accumulator 2 1ORL A,@Ri OR indirect RAM to Accumulator 1 1ORL A,#data OR immediate data to Accumulator 2 1ORL direct,A OR Accumulator to direct byte 2 1ORL direct,#data OR immediate data to direct byte 3 2XRL A,Rn Exc-OR register to Accumulator 1 1XRL A,direct Exc-OR direct byte to Accumulator 2 2XRL A,@Ri Exc-OR indirect RAM to Accumulator 1 1XRL A,#data Exc-OR immediate data to Acc. 2 1XRL direct,A Exc-OR Accumulator to direct byte 2 1XRL direct,#data Exc-OR imm. data to direct byte 3 2CLR A Clear Accumulator 1 1CPL A Complement Accumulator 1 1RL A Rotate Accumulator left 1 1RLC A Rotate Acc. left through Carry 1 1 XRR A Rotate Accumulator right 1 1RRC A Rotate Acc. right through Carry 1 1 XSWAP A Swap nibbles within the Accumulator 1 1

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Data transfer: Byte Cycle C OV ACMOV A,Rn Move register to Accumulator 1 1MOV A,direct Move direct byte to Accumulator 2 1MOV A,@Ri Move indirect RAM to Accumulator 1 1MOV A,#data Move immediate data to Accumulator 2 1MOV Rn,A Move Accumulator to register 1 1MOV Rn,direct Move direct byte to register 2 2MOV Rn,#data Move immediate data to register 2 1MOV direct,A Move Accumulator to direct byte 2 1MOV direct,Rn Move register to direct byte 2 2MOV direct,direct Move direct byte to direct byte 3 2MOV direct,@Ri Move indirect RAM to direct byte 2 2MOV direct,#data Move immediate data to direct byte 3 2MOV @Ri,A Move Accumulator to indirect RAM 1 1MOV @Ri,direct Move direct byte to indirect RAM 2 2MOV @Ri,#data Move immediate data to indirect RAM 2 1MOV DPTR,#data16 Load Data Pointer with 16-bit const 3 2MOVC A,@A+DPTR Move Code byte rel. to DPTR to Acc. 1 2MOVC A,@A+PC Move Code byte rel. to PC to Acc. 1 2PUSH direct Push direct byte onto stack 2 2POP direct Pop direct byte from stack 2 2XCH A,Rn Exchange register with Accumulator 1 1XCH A,direct Exchange direct byte with Acc. 2 1XCH A,@Ri Exchange indirect RAM with Acc. 1 1XCHD A,@Ri Exchange low order digit indirect

RAM with Accumulator 1 1

Number and String Formats:Numbers : Decimal - 34

Binary - 01110101BHexadecimal - a leading $ or a trailing h or H.

e.g. $7F, 7Fh, 0FFH, $FF 0A8H

Note: if not preceded by "$", hex constants must start with 0-9. eg 0C7h

Characters: 'A' - 'Abc' - ‘A’,00DH,00AH (mixed mode), "T"

Strings : Only with DB directive for putting strings into CODE memory'abc' or "abc"

Operators : () + - / * MOD SHR SHL NOT AND OR XOR

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Boolean variable manipulation: Byte Cycle C OV ACCLR C Clear Carry 1 1 0CLR bit Clear direct bit 2 1SETB C Set Carry 1 1 1SETB bit Set direct bit 2 1CPL C Complement Carry 1 1 XCPL bit Complement direct bit 2 1ANL C,bit AND direct bit to Carry 2 2 XANL C,/bit AND complement of dir. bit to Carry 2 2 XORL C,bit OR direct bit to Carry 2 2 XORL C,/bit OR complement of dir. bit to Carry 2 2 XMOV C,bit Move direct bit to Carry 2 1 XMOV bit,C Move Carry to direct bit 2 2JC rel Jump if Carry is set 2 2JNC rel Jump if Carry not set 2 2JB bit,rel Jump if direct bit is set 3 2JNB bit,rel Jump if direct bit is not set 3 2JBC bit,rel Jump if dir. bit is set & clear bit 3 2

Program Branching: Byte Cycle C OV ACACALL addr11 Absolute subroutine call 2 2LCALL addr16 Long subroutine call 3 2RET Return from subroutine 1 2RETI Return from interrupt 1 2AJMP addr11 Absolute jump 2 2LJMP addr16 Long jump 3 2SJMP rel Short jump (relative address) 2 2JMP @A+DPTR Jump indirect relative to the DPTR 1 2JZ rel Jump if Accumulator is zero 2 2JNZ rel Jump if Accumulator is not zero 2 2CJNE A,direct,rel Compare direct byte to Accumulator

and jump if not equal3 2 X

CJNE A,#data,rel Compare immediate data to Accumulator and jump if not equal

3 2 X

CJNE Rn,#data,rel Compare immediate data to register and jump if not equal

3 2 X

CJNE @Ri,#data,rel Compare immediate data to indirect RAM and jump if not equal

3 2 X

DJNZ Rn,rel Decr. register and jump if not zero 2 2DJNZ direct,rel Decrement direct byte and jump if

not zero3 2

NOP No operation 1 1

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Assembler Directives and Controls; Everything after a semicolon (;) on the same line

is a comment

Label: Labels must start in column 1 – Defines a new Label - the colon is optional.

Controlling Memory Spaces and Code locationORG 56H Specify a value for the current segment's location

counter.USE IRAM Makes the data space the currently selected segmentUSE ROM Makes the code space the currently selected segment

Defining Byte and Bit valuesTEN EQU 10 EQUates 10 to symbol TEN,

like #define in C, CONST in DelphiON_FLAG BIT 6 Assigns BIT 6 (in data or SFR space) to the symbol

ON_FLAG

Allocating MemorySP_BUFFER: RMB 6 Reserves Memory Byte – reserves 6 bytes of storage

in current memory space (affected by most recent USE IRAM/ROM).

Message: DB "Hi" Define Byte(s): Store byte constants in code space.

The following three DB definitions are equivalent – the string hello followed by a newline and a null.

DB "H","E","L","L","O",13,0DB "Hello",13,0DB "Hello",newline,0

newline EQU 13

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