Seamless, Risk-Free FPGA-to- Structured ASIC Migration Flo · FPGA Fitter System Verification...

Seamless, Risk-Free FPGA-to-Structured ASIC Migration Flow

© 2006 Altera Corporation 2

Increasing Development Cost To

tal D

evelo

pm

en

t C

ost

(M$)

45

20

40

35

30

25

15

0 0.18 µ 0.15 µ 0.13 µ 90 nm 65 nm 45 nm

Masks & Wafers

Test and Product Engineering

Software

Design /

Verification

& Layout

$200K Per Engineer


Constant Increase in Mask Charges

Costs increase exponentially as process geometry

decreases

New mask making technologies required

Drawn geometries are smaller than wavelength of light used

to expose masks

Optical proximity correction (OPC) used to pre-distort shapes

Tighter geometry decreases mask yields

Mask costs for structured ASICs substantially lower than

standard cell ASICs

Vendor amortizes pre-fab base costs over many designs

Customer pays only for customization of specific layers

2 – 5 masks vs. 40+ masks for standard

cell ASICs


Risks in Digital Designs

Design implementation risks

67% first-spin failure rate for 130-nm designs in 2003*

40% failure rate after three design spins*

Product feature risks

Uncertainties during initial product definition

Field trials are necessary

Market adoption risks

Predicting volumes

How much should a company risk to introduce new products?

*Source: Collett and Associates


Value Proposition for Prototyping

Faster time-to-silicon

Faster and more comprehensive verification

Earlier software development

Costly ASIC re-spins prevented

Field trials and test marketing

Over 40% of ASIC Designers

Prototype Today


Historical Obstacles to ASIC Prototyping

Before: FPGAs and ASICs used different design flows

Today: Altera’s FPGAs and HardCopy structured ASICs support ASIC tools Synthesis: Design Compiler FPGA

Simulation: VCS, Incisive, and ModelSim®

Formal Verification: Formality and Encounter Conformal

Static Timing Analysis: Primetime

Before: FPGAs were too small

Today: 78% of ASIC designs can fit on a single Stratix® II FPGA

Stratix II FPGAs and HardCopy II structured ASICs

2.2 million useable ASIC gates

9 Mbits of configurable SRAM

1.6 million additional gates for digital signal processing (DSP) functional blocks


Flexible HardCopy Design Methodology

Synthesis

Verification

Physical

Design

Traditional ASIC

Design Tools

Design Compiler

VCS Incisive Formality ModelSim PrimeTime

Place & Route Design Rule Checker (DRC) Automatic Test Pattern Generation (ATPG)

Traditional FPGA

Design Tools

Synplify Pro Precision Quartus II

ModelSim Quartus II Program FPGA

Quartus II

VCS Incisive

ModelSim Formality Conformal Quartus II

Programmed FPGA

HardCopy Design

Flow

Design Compiler FPGA

Synplify Pro

Precision Quartus® II

Quartus II Fitter Astro

TetraMAX PrimeTime SI

Walking Through the Design Process


Comparing ASIC vs. HardCopy Design Process

Apple-to-apple comparison of design implemented in structured or standard cell ASICs vs. HardCopy structured ASICs

Basic assumptions: Moderate gate count: 1M-2M gates

Moderate performance: 100-200 MHz

Skipping ASIC prototyping for the non-HardCopy implementation

Comparing Time to market (TTM)

Time to mass production (TTP)

Tool, non-recurring engineering (NRE), major last-minute design change support (ECO support) costs are not factored in


ASIC and HardCopy code generation are very similar.

Customer Customer Design Center Design Center

Coding (RTL) Coding (RTL)

RTL Coding

Standard Cell ASIC HardCopy II

Total Weeks

15 15


ASIC and HardCopy behavior simulation are very similar.


Coding (RTL)

Simulation

Coding (RTL)

Simulation

Behavior Simulation


Total Weeks

22 22


ASIC synthesis: Design Compiler (also requires Design Center Support for timing extraction)

HardCopy synthesis: DC FPGA, Synplify, Precision, and Quartus II software


Coding (RTL)

Simulation

Synthesis

Coding (RTL)

Simulation

Synthesis

Synthesis


Total Weeks

26 22

Floorplanning


ASIC requires post-synthesis verification with simulation or formal verification.

HardCopy designs do not require post-synthesis verification.


Coding (RTL)

Simulation

Synthesis

Simulation/Func-

tional Verification

(FV)

Coding (RTL)

Simulation

Synthesis

Post-Synthesis Design Verification


Total Weeks

30 26

Floorplanning


Place and route for ASICs requires extensive Design Center involvement.

HardCopy placement is done by design engineer with Quartus II software.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

HardCopy Place.

Physical Design and Timing Closure


Total Weeks

38 28

Floorplanning


ASIC require post place-and-route verification before tape-out.

HardCopy FPGA companion is used for system verification.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

System Verification

(FPGA)

HardCopy Place.

Design Verification vs. System Verification


Total Weeks

42 34

Floorplanning


Sign-off based on simulation results.

Sign-off based on comprehensive in-system verification.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

System Verification

(FPGA)

HardCopy Place.

Design Sign-off

Design Sign-off


Total Weeks

43 35

Floorplanning


Tape-out and build prototypes.

Single place and route, tape-out, and build prototypes.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape-out (GDSII)

Build Prototype

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

Design for Test

Tape-Out (GDSII)

System Verification

(FPGA)

HardCopy Place.

Place and Route Design Sign-off

Build Prototype

Tape-out and Prototype Build


Total Weeks

50 44

Floorplanning


Wait for prototypes. Everything on standby Support early production with FPGA after sign-off while

prototypes are being built


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

System Verification

(FPGA)

HardCopy Place.

Design Sign-off

Early

Prod.

With

FPGA

Tape Out (GDSII)

Design Sign-off

Design for Test

Tape Out (GDSII)

Place and Route

Build Prototype

Build Prototype

Early Production with FPGA


Total Weeks

50 44

Floorplanning


System verification begins with ASIC prototypes.

System verification for HardCopy devices already complete.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape Out (GDSII)

Build Prototype

System

Verification

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

System Verification

(FPGA)

HardCopy Place.

Design Sign-off

Design for Test

Tape Out (GDSII)

Place and Route

Build Prototype

Early

Prod.

With

FPGA

ASIC Prototypes Are Back for System Verification


Total Weeks

56 44

Floorplanning


Final prototype sign-off is the same for ASIC

and HardCopy devices.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape Out (GDSII)

Build Prototype

System

Verification

Prototype Sign-off

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

Design for Test

Tape Out (GDSII)

System Verification

(FPGA)

Prototype Sign-off

HardCopy Place.


Early

Prod.

With

FPGA Build Prototype

Final Prototype Signoff


Total Weeks

57 45

Floorplanning


HardCopy II devices have 23-week time-to-market

advantage and 12-week time-to-production advantage.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape Out (GDSII)

Build Prototype

System

Verification

Prototype Sign-off

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

Design for Test

Tape Out (GDSII)

System Verification

(FPGA)

Prototype Sign-off

HardCopy Place.


Build Prototype

Early

Prod.

With

FPGA

Production Production

Ready for Production


Total Weeks

67 55

Floorplanning


Failed system verification requires an ASIC respin.

Failed system verification requires reprogramming the FPGA


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape Out (GDSII)

Build Prototype

System

Verification

Prototype Sign-off

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

Design for Test

Tape Out (GDSII)

System Verification

(FPGA)

Prototype Sign-off

HardCopy Place.


Build Prototype

Early

Prod.

With

FPGA


Impact of an ECO during System Verification


Total Weeks

83 59

Floorplanning


HardCopy design flow provides the most comprehensive verification process and the fastest time to market.


Coding (RTL)

Simulation

Synthesis

Place and Route

Design for Test

Sim./FV

Design Sign-off

Tape Out (GDSII)

Build Prototype

System

Verification

Prototype Sign-off

Sim./FV

Coding (RTL)

Simulation

Synthesis

FPGA Fitter

Design for Test

Tape Out (GDSII)

System Verification

(FPGA)

Prototype Sign-off

HardCopy Place.


Build Prototype

Early

Prod.

With

FPGA


Design Methodology Comparison


Total Weeks

83 59

Floorplanning


ASIC vs. HardCopy Comparison

Based on one respin

83 weeks to reach ASIC production

59 weeks to reach HardCopy production

44 weeks for early production with FPGA

Significant time-to-market advantage

Altera supports traditional ASIC and FPGA

design tools

Most comprehensive pre-tape-out system

verification methodology

Highest first-time success rate

in the industry


The Wave of the Future

Get Low Development Costs and Maximum Flexibility

With FPGAs

Convert to HardCopy Structured ASICs When Justified and Needed

FPGA Prototype

Design Tool

Structured ASIC


Designed for Seamless Migration

Process technology Same

Soft intellectual

property (IP) Proven & embedded in design database

Hard IP functionality Identical

User I/O

characteristics Equivalent

Design methodology Unified for prototype FPGA & HardCopy II

device

Pin-to-pin compatibility Yes1

Package Equivalent

Design revalidation Not required

Quartus II Software Guides Designs

for Seamless Migration

Comparison of Stratix II FPGA and HardCopy II Structured ASIC

1 HardCopy II devices have fewer available I/O pins.


HardCopy II Family

Feature HC210W HC210 HC220W HC220 HC230 HC240

ASIC Gates 1M 1M 1.6M 1.6M 2.2M 2.2M

Additional Gates for DSP Blocks

0 0 0.3M 0.3M 0.7M 1.4M

Total RAM (Millions of Bits)

0.88 0.88 3 3 6.3 8.8

Phase-Locked Loops (PLLs)

4 4 4 4 8 12

Maximum User I/O

308 334 494 494 698 951

Package F484

Wire Bond F484

F672 F780

F672 F780

F1020 F1020 F1508

FPGA Prototype Options

EP2S30 EP2S60 EP2S90



EP2S130

EP2S60 EP2S90

EP2S130


EP2S180


Pro

du

cti

on

Vo

lum

e

Time

10K

1K

100K

1M

HardCopy

#1 Insurance Policy

FPGA

FPGA

• Production is planned with FPGA

• HardCopy devices are an insurance

policy in case quantity exceeds

expectations or price pressure increases

#2 Plan of Record

HardCopy

• HardCopy devices planned from inception as

production vehicle

• FPGA may be used for initial production

#3 Accelerated Time to Production HardCopy

Standard Cell ASIC

• Forecast quantity justify an ASIC development

• HardCopy devices provide a fast and low-risk path to production and an insurance policy in case forecast does not materialize

HardCopy Usage Models


Summary

HardCopy II structured ASICs are low-cost, drop-in

replacements for Altera high-performance Stratix II

FPGAs

HardCopy II structured ASIC power and performance

are comparable to standard-cell ASICs

Quartus II software enables seamless migration from

Stratix II FPGAs to HardCopy II structured ASICs

HardCopy II structured ASICs are true alternatives to

the standard-cell ASICs


The Only Structured ASIC Company

With a Programmable Logic Front-End

The Only FPGA Company With a

Structured ASIC Solution

Altera Offers

Technical Backup

Front-End Design Flow


Approv

e

Design? HardCopy II

Physical Optimization

Design

HardCopy II Design Flow

Customer Handoff to HardCopy Design Center

Validate Design In-System with Stratix II FPGA

HardCopy II

Target HardCopy II

Device


Front-End Design Flow in Quartus II Software

module FPGAchip_top {…}

………………….

…………............

endmodule

RTL Design

module FPGAchip_top {…}

ALM0 ALM_logic(a,b,clk)

ALM1 ALM_reg(l,m,n,o)

----------------------------

endmodule

FPGA Netlist

module HCchip_top {…}

HCM5 HCM_L0(a,b,clk)

HCM15 HCM_R5(l,m,n,o)

-----------------------------

endmodule

HardCopy Netlist

Functionally

Equivalent

Netlists

Optional

Third-Party

Synthesis


Select Companion Pair

Chooses Stratix II FPGA and HardCopy II device

Reports Stratix II FPGA vertical migration devices

Guides pin-out compatibility between Stratix II and HardCopy II devices

Constrains I/O standards, PLLs, and delay-locked loops (DLLs)

Filters FPGA prototyping options

Recompile the design after

choosing the HardCopy II device

Device Settings Box


HardCopy II Advisor Step-by-step guides to prepare

design for a successful netlist handoff to HardCopy Design Center

Use the advisor to review design settings in Quartus II software

Reviews

Timing constraints

Project settings

HardCopy II development tasks

Alerts any unresolved tasks


HardCopy II Advisor Checks

Chosen Stratix II/ HardCopy II devices

Design Assistant enabled

Assembler enabled

Timing settings enabled

Incompatible assignments

Current revision compiled

Companion revision created

Companion revision compiled

Comparison of revisions completed

Handoff report created

Archive created

Back-End Design Flow


HardCopy II Back-End Design Flow

Formal Verification

Quartus II Constraints ● Timing Constraints ● Placement Constraints ● Routing Constraints

HardCopy II Design Libraries ● Physical and Timing Models ● Base Layout Database

Design Database Contents:

Physical Verification

Parasitic Extraction

Crosstalk, Signal Integrity (SI),

Static Timing Analysis

Timing ECO

Post P&R Netlist

Layout GDS2

Netlist Sign-off Design Tape-Out Timing Sign-off

Processed Netlist

Design Database

Formal Verification

Timing & SI-Driven Place & Route

Clock Insertion 1 DFT Insertion Global Signal Insertion Other Tasks

Quartus II Netlist

Layout Sign-off Quartus II

SOF

SOF2NET


Altera Responsible for Testing

Scan Chain

Insertion

Route optimization

Manage scan flop timing overhead in Quartus II

software

ATPG 97-98% stuck at fault coverage

Memory Built-in

Self Test (BIST) Includes fuse-based repair

PLL/DLL and

SERDES BIST Lock at speed

JTAG I/O Connections

Parametric measurements

Speed Paths Speed path and scribe line structure (ET)

for determination of process factor


Chronology of HardCopy II Design Activities

HardCopy II

Back-end

Flow in

HardCopy

Design Center

Custom Masks

Prototype

Fabrication

Assembly & Test

Customer

Qualify

System

Using

Prototype

Production

10 Samples

Up to 250 Risk

Units Possible

at 1.5x

Cost

Production

Units Available Design Handoff Tapeout

Design Development

System bring-up

using FPGA

Prepare design for

final handoff

Activities in color indicate Altera controls schedule

4-6 weeks 6-8 weeks 8-10 weeks

Time

Design

Review 1

Design

Review 2

Prototype

Delivery

Prototype

Approval Production Design

Kick-off

Design

Review 3


The HardCopy II Family Structured ASIC technology

Uses same base array across multiple designs for a given density with five customizable masks

Offers true alternative to standard cell ASIC Up to 2X performance improvement over FPGA

50%+ power reduction vs. FPGA prototype

$10 volume price for 1M-gate device (HC21W)

Eliminates high risk and cost of standard cell ASIC Unified FPGA-like front-end design flow in Quartus II software

Full in-system design verification using Stratix II FPGA

Seamless migration to HardCopy II structured ASIC Altera performs turn-key, back-end design flow

Drop-in replacement between Stratix II FPGAs and HardCopy II structured ASICs


Foundation for Low Cost and Seamless Migration First: defined base

family members I/O count

Packages

Result: Low-Cost Structured ASIC

With Stratix II FPGA Prototype

PLL

I/O buffers

Memory blocks

Clock network

Embedded equivalent Stratix II

FPGA structures

Remaining area filled with logic

© 2006 Altera Corporation 44 © 2006 Altera Corporation 44

Interconnect

ALM

Innovative Logic Architecture

Delivers High Density and

Low Cost per Gate

Adaptive Logic Module (ALM)-Based

Array of Fine-Grained HCells

II

85% Reduction

~60% Reduction

Interconnect

ALM

Same Architecture With Programmability Removed


Achieving Seamless Migration

ALM

8-LUT

+ LUT

LUT

+ LUT

LUT

ALM

Many Different ALM Configurations


Implementing Seamless Migration

II

Stratix II ALM

ALM

8-LUT

+ LUT

LUT

+ LUT

LUT

HCell macro: collection of HCells implementing unique ALM configuration

> 20K predefined, preverified, precharacterized macros


Quartus II Software Performs the Mapping

Utilizes HCell macro library

Predefined, precharacterized, preverified

Maps ALM-by-ALM

Maps only logic used within each ALM

HardCopy II Advisor makes the process easy

Library of HCell Macros

Combinatorial Macros

Adder Macros Register Macros

DSP Macros


EP2S130

EP2S90

HC230

HC210

The World’s Biggest and Fastest FPGAs

The World’s Only Seamless Migration From FPGA

HardCopy II Structured ASICs

Linking the FPGA and ASIC Worlds

• Low unit cost

• 70% lower core

power

• Up to 2X the FPGA

performance 11:1 Die Size

Reduction

5:1 Die Size

Reduction

Guaranteed First-Silicon Success


HardCopy II Device Architecture

Sample representation only. Not to scale

PLL PLL PLL

M-RAM M-RAM

PLL

M-RAM M-RAM

PLL

M-RAM M-RAM

PLL PLL PLL

Ba

nk 1

B

an

k 2

Ba

nk 6

B

an

k 5

Bank 8 Bank 7

Bank 3 Bank 4

M4K

MRAM

I/O PLL

Logic

Designed for Low Cost,

High Performance, and Low Power


Understanding HardCopy II Metal Layers

Stratix II FPGA HardCopy II Structured ASIC

Customer Layers: V3 + V4/M5/V5/M6

AP (Al bump

redistribution)

90-nm Thick Cu

90-nm Thin Cu

(V3 is Custom Layer)

90-nm Thin Cu

(130-nm rules)

Custom Layers

Architecture: Performance


HardCopy II Performance

Actual design performance in HardCopy II devices can

be significantly better than in Stratix II FPGAs

Faster routing

Fewer logic levels

Flexibility in HCell macro placement

Design performance depends on critical path

Core (other than DSP and memory)

Up to 100% faster than Stratix II FPGAs

IO path, DSP, and memory

Minimal performance improvement over Stratix II


HCell Macros: Designed for High Performance

Fewer levels of logic for the same combinatorial function Test example: 6-input LUT translates to 6-logic levels in FPGA

HardCopy II implementation: 2 to 5 logic levels, design dependent

Programmable interconnect multiplexers removed

Much shorter routing delay between HCells

ALM Stratix II FPGA

More Gates per mm2, Fewer Logic Levels

HardCopy II Structured ASIC

HCell

Macro

Out1

HCell

Macro


Logic Placement Flexibility Section of Stratix II Device Floorplan Section of HardCopy II Floorplan

HCell Macro Implementations of ALMs

M4K Block

Facilitates Timing Closure

Logic ALMs


DSP Function Placement Flexibility HardCopy II Floorplan Stratix II Floorplan

(Only DSP Blocks Shown)

Timing-driven compilation in Quartus II software

User-driven with LogicLock™ incremental design

Facilitates timing closure

Architecture: Power and IP


Optimized for Power Efficiency

Unused logic, memory blocks not connected to power rail

Unused clock trees, PLLs not powered

Quartus II PowerPlay

power analyzer tool

Calculates dynamic power

Based on simulation file

Test Case Details:

FPGA: EP2S60, 85º C, 90% utilized, 200 MHz HardCopy II: HC210 / HC220

0

1

2

3

4

5

6

7

8

9

1010

8

6

4

2

0 Stratix II FPGA HardCopy II

~ 50%

~ 50 - 70%

Watt

s

I/O

Core (Dynamic)

Leakage


IP Support

IP cores for the Stratix II FPGAs map into

HardCopy II structured ASICs

Except IP with dependency on pre-initialized RAMs

HardCopy II family does support ROMs

Altera Megafunction Partners Program

(AMPPSM) IP

IP suppliers may require additional license fee


Nios II Support for HardCopy II Devices

Set appropriate initialization settings for RAM

Turn on HardCopy Compatible check box in SOPC

Builder on the system contents page


Choose the Right HardCopy II Device

Use HardCopy II Device Resource Guide in

Quartus II software

Device Resource Guide reports

Compiled Stratix II device resources

Design’s required resources

Resource utilization in HardCopy II devices

Device Resource Guide helps select correct

HardCopy II device

Vertical package migration support

Report Stratix II and HardCopy II

devices


Device Resource Guide HardCopy II HC230 Structured ASIC Stratix II EP2S90 FPGA

HardCopy II Floorplan


HardCopy II Floorplan View



9x9 DSP MAC

M4K RAM


HardCopy II HCell Fabric

HCell Register Macro

(4 HCells Used) HCell Combinational Macro

(1 HCell Used)


Stratix II Pin Planner View

Stratix II FPGA view without migration shows all pins are available


Stratix II Device With HardCopy II

Migration

With HardCopy II

migration device enabled,

unusable pins are hidden

Still will show Stratix II

required pins, Vcc pins,

and Vss pins

Rule checker assures

simultaneous switching

noise (SSN) rule

compliance for both

Stratix II and HardCopy II

devices

Back Up Business Slides


Yesterday’s Dilemma:

Increasing Development Cost To

tal D

evelo

pm

en

t C

ost

(M$)

45

20

40

35

30

25

15

0 0.18 µ 0.15 µ 0.13 µ 90 nm 65 nm 45 nm

Masks & Wafers

Test & Product Engineering

Software

Design /

Verification

& Layout

$200K Per Engineer


What If Companies Could…

Introduce product 6-9 months earlier?

Implement customer feedback in silicon in

real time

Create multiple design variations?

Optimize the function and timing of each

React to competitive threats and market

changes instantaneously?

Reduce development time?


Proposed Solution

Get Low Development Costs & Maximum Flexibility

With FPGAs

Convert to HardCopy Structured ASICs

When Justified and Needed

FPGA Prototype

Design Tool

Structured ASIC


Customers design with Altera Stratix series FPGAs

In-house migration to a lower cost HardCopy device for higher volume

applications with:

Same function/operation as the FPGA design

Same pin-out

Lower power

Higher performance

How to make a lower cost HardCopy structured ASIC

Remove FPGA configuration circuitry

Remove FPGA programmable routing

Remove FPGA programmability for logic and memory

Add embedded testability

Customize with two metal layers

The Idea Behind HardCopy Structured

ASICs


Standard Cell vs. Structured ASIC

Structured ASICs Deliver Low NRE

Costs and Quick Turnaround Times

Full Set of Masks

for Standard Cell ASIC

All Layers are Custom

Top Layers Customize

Structured ASIC

Pre-Fabricated Common Layers

Base Layer


Unique HardCopy Value

Only Altera offers FPGAs AND structured ASICs

Leverage FPGA technology to build structured ASIC

FPGA front-end design process

Design with Quartus II software

Test design in-system with FPGAs

Turnkey migration to drop-in replacement

Significant benefits

Much lower risk of ASIC re-spin

Lower initial investment than standard cell

Use FPGA in early production

Smooth transition to HardCopy device

Transition back to FPGA at end of system life


Additional Benefit: One Vendor

Common tool flow: FPGA and HardCopy Devices

Consistent technical support

Transition logistics managed

Clear accountability throughout

FPGA use always an option

Only With HardCopy

Structured ASICS


SOURCE: COLLETT INTERNATIONAL RESEARCH INC.

ONLY 39% of Designs Were Bug-Free in First Silicon

Solving The ASIC Re-Spin Problem

Aart de Geus, Chairman & CEO of Synopsys,

Boston SNUG Keynote Address, Sept. 2003

18% 37%

39%

% of Designs

0

1 2

3 + Nu

mb

er

of

S

ilico

n R

e-s

pin

s

6%

Func. Logic Error 43%

Analog 20%

SI 17%

Clock Scheme 14%

Reliability 12%

Mixed Signal 11%

Too Much Power 11%

Slow Paths 10%

Fast Paths 10%

IR Drop 7%

Firmware 4%

Other 3%

Prototyping With FPGAs Removes

Functional Logic Errors


Facing Multiple Challenges R&D budgets under

pressure

Design complexity increasing

Companies react with minor product improvements (creeping incrementalism)

Challenge

Developing

Breakthrough

Products

Cost and

Risk of

Innovation

Increasing

ASIC designs take 18-24 months

Market can shift faster than planning and development

New product may not impact market (but R&D already spent!)

End users demand products aligned to their specific needs

New competitors entering to support market fragments

Greatest

Vulnerabili

ty

Market

Fragmentation


Use FPGA for

Design Updates,

Avoid Obsolete

Inventory

Seamlessly Adapt

to Increased Demand

Using a Structured ASIC

Be First

to Market Using

an FPGA

Solution for the Entire Product Life V

olu

me

Time


Altera: Ideas-to-Production Partner Altera

Did I build the right product?

Design flexibility enables rapid

changes and efficient test

marketing

Did I build the product right? In-system, at-speed testing

throughout design cycle

Did I build the market demand? Test market and build market plan

during development

Can I build enough product to

meet demand?

Use FPGAs or structured ASICs

depending on volume and bill of

materials (BOM) budget

Enabling Vision, Creativity, and Production

Seamless, Risk-Free FPGA-to- Structured ASIC Migration Flo · FPGA Fitter System Verification...

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Transcript of Seamless, Risk-Free FPGA-to- Structured ASIC Migration Flo · FPGA Fitter System Verification...