Schedule Performance Design SpecificationSchedule 22 Feb. 2001@CERN ATLAS MDT Electronics...
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ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 1 ATLAS ATLAS Muon TDC (AMT) Yasuo Arai (KEK) [email protected] http://atlas.kek.jp/~araiy/ • Specification • Design • Performance • Schedule 22 Feb. 2001@CERN ATLAS MDT Electronics Preliminary Design Review
Transcript of Schedule Performance Design SpecificationSchedule 22 Feb. 2001@CERN ATLAS MDT Electronics...
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 1
ATLAS
ATLAS Muon TDC (AMT)
Yasuo Arai (KEK)[email protected]
http://atlas.kek.jp/~araiy/
• Specification• Design• Performance• Schedule
22 Feb. 2001@CERNATLAS MDT ElectronicsPreliminary Design Review
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 2
ATLAS
Specifications of ATLAS MDT TDC (AMT)
• ~370 k channels (16,000 chips)• ~0.5 ns timing resolution• 400 kHz input rate, 100 kHz trigger rate• Leading and Trailing edge (width) time measurement• Trigger Latency > 3 µs• Low-cost, Low-power (~10 mW) & High-density (24 ch/chip)• LVDS interface for active signals during measurement• Serial output (40 Mbps)• Radiation Tolerant (~11 krad, 1.2x1013 n/cm2 @10year LHC)• JTAG I/F, BIST, Serial control• 144 pins plastic QFP
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 3
ATLAS
Short History
Design study (Y.Arai & J.Christiansen).(CERN) AMT-0
(KEK)AMT-TEG
AMT-1
(AMT-2)
1996
2001
2000
1999
1998
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 4
ATLAS
Block Diagram of the AMT
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 5
ATLAS
AMT-1 chip (0.3µm Toshiba CMOS Gate-Array, 6 mm x 6mm)
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ATLAS
PLL Stability
300
200
100
0
σ jitter[p
s]
12080400
PLL Osc Freq [MHz]
3.73.32.92.5
Vdd[V]
vs. Freq
vs. Vdd
(b)
σjitter(a)
Input Clock(40 MHz)
PLL OSC output(80MHz)
trigger
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ATLAS
Double Pulse Resolution
An example of pulse which recorded successfully
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 8
ATLAS
400
300
200
100
0
Cou
nts
-2 -1 0 1 2
∆t[ns]
RMS=305 ps
0.4
0.2
0.0
-0.2
INL[
ns]
151050TDC count
Max=+/-0.13ns, RMS=0.07ns(b)
0.4
0.2
0.0
-0.2
DN
L[ns
]
Max=+/-0.14ns, RMS=0.06ns(a)
Time Resolution
Differential & IntegralNon-Linearity
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ATLAS
Serial Output
LVDS outputwaveform at 40 Mbps
Data
Strobe
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 10
ATLAS
Power Consumption
• Power consumption of the AMT-1 is ~500 mW/chip(~20mW/chan)
• Factor two larger than the target value• Main source of the power consumption is LVDS receiver
(~16 mW).• A new LVDS receiver is under development which
consumes only 1/4 of the present receiver
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 11
ATLAS
Radiation Tolerance
• Source : 60Co (~90 rad(Si)/sec)• Follow MIL-STD method.• 1 week ann �ealing at 100 C• Estimated level is <11 krad/10 year
(@Endcap, Safety factor=4)
150
100Osc
. Fre
q.[M
Hz]
Chip 1 Chip 2
1.0
0.5
0.0
Idd[
A]
1 10 100
Dose[krad]before irradiation
Chip 1+2
0.8
0.6
0.4
Vth[V]
(a) NMOS
-1.0
-0.8
-0.6
Vth[V]
Dose[krad]
10 100
before Irrad. after anneal.
(b) PMOS
10-12
10-11
10-10
Id[A]
Dose[krad]
10 100
before Irrad. after anneal.
(b) PMOS
10-11
10-10
10-9
10-8
10-7
10-6
10-5
Id[A]
(a) NMOS
Total Ionizing Dose ( γ )
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 12
ATLAS
Radiation Tolerance (cont.)Displacement Damage (neutron)
• Irradiated at the PROSPERO reactor• 8 chips :1.0 x 1013 n/cm2, 4 chips : 1.6 x 1013 n/cm2
• Expected neutron flux is <1.2 x 1013 n/cm2/10 years• Any damage was not observed
Single Event Effect (hadrons)
• No Measurment yet for Single Event Effect (SEE)• Estimated fluence is <1010 h/cm2/10years.• Assume a SEU cross section of 10-13/cm2/bit,
=> 1.5 SEU/day/MDT for the contents of CSR.• AMT can detect 1 bit SEU and report by an error word• Even AMT is stacked, the effect is only for 24 ch• SEE test will be done in Japan
ATLAS MDT Electronics PDR, 22-Feb 2001 Yasuo Arai, page 13
ATLAS
Schedule
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ATLAS
Summary
❏ A prototype TDC chip (AMT-1) was successfully developed.
❏ AMT-1 fulfils most of requirements.
❏ ~400 AMT-1 chips will be used in the 10 kch test.
❏ New LVDS receiver has been developed to reduce powerconsumption.
❏ SEE test is planned in Japan.
❏ AMT-2 is now under development, and will be submitted inMarch.
❏ Mass production wiil be finished early next year.
