Schedule - ntut.edu.tw

VLSI Design : Chapter 5-1 1

Schedule

09. 04/22/22 Exam review , Chapter 6 (Multiplier)

10. 04/29/22 入學測驗

11. 05/06/22 Chapter 7 (Placement & Routing)

12. 05/13/22 Chapter 7 (Special nets, b4TO)

13. 05/20/22 Chapter 8 (Architecture)

14. 05/27/22 (QZ2) Chapter 8 (Architecture)

15. 06/03/22 端午節

16. 06/10/22 Chapter 9 (Examples)

VLSI Design: Chapter 7-1 2

RTL, NetlistDFT: JTAG,

m-BIST, 1149.1,

Scan Insertion,

…(Spare)

RC Extraction

(3D)

Floor Planning

Macro/Power/Std

Placement

Global/Local

Routing

WLM, Set load,

EDIF, HDL (gate),

SDC, GPF/UPF

Physical

compiler

Signal Integrity *

Delay *

Calculation

Buffer insertion,

CTS, (Spares)

Scan Reordering

Power Analysis

IR/EM *

IPs: Analog, PLL,

Std, IOs , MEM…

Optional, ( )

Data format

Standard Flow

Notes

Formality *

SDF, Set load, SPF

RC extraction (2.5D)

Back Annotation

Post Simulation *

Synthesis

Chip RTL,

Constrains, GPF

STA *

Test Pattern

Generation

Tapeout

DRC/ERC/LVS

Antenna Check *

GDSII


Chapter 7: Floorplanning

Floorplan (data preparation, global wiring)

Placement

Placement.

Simulation annealing

Routing

Local routing.Switchbox routing

Channel routing

Global routing.

Special Nets

Things Before Tapeout (ESD and more)


Floorplanning strategies

Floorplanning is an art more than techniques, must consider function, timing, size, shape for different conditions.

Including:

space allocation (place);

signal routing;

power supply routing;

clock distribution.


Floorplan

blocks


Floorplan-2

From VIA’s

VLSI Design

VLSI Design : Package 7

Double bound

GndGnd Vdd

Digital + Analog Chip


Digital Camera Chip Floor Plan


Wireless Power Chip Floor Plan

DC2DCCSM

OSC

Mixer

Digital

LDOs

NVM

1.8PWR

ACTDCT

LVL

SNS


Another Floor Plan


More Floorplans from real world


Purposes of Floorplanning

Early in design:Prepare a floorplan to budget area (cost estimation).

Wire area/delay. Tradeoffs between blocks can be

negotiated.

Pin out for frame fitting.

Late in design:Make sure the pieces fit together as planned.

Implement the global layout.


Basic Ideas for Floorplanning

Put the timing critical blocks as close as

possible.

Put the combination logics in a convex shape

if possible.

Put RAM or any other sensitive device at the

far side of the noise sources.


Floorplanning tips

Develop a wiring plan. Think about how layers will be used to distribute important signals.

Sweep small components into larger blocks. A floorplan with several glue gates in the middle will be hard to work with.

Design wiring plan that looks simple. If it looks complicated, it is complicated.

KISS, Keep It Simple and Stupid


Floorplanning tips, cont’d.

Design planar wiring. Planarity is the essence

of simplicity. It’s not always possible, but

do it where feasible (and where it doesn’t

introduce unacceptable delay).

If possible, draw separate wiring plans for

power and clocking. These are important

design tasks which should be tackled early.


Layout

Two critical phases of layout design:

placement of components on the chip;

routing of wires between components.

Placement and routing interact, but separating

layout design into phases helps us

understand the problem and find good

solutions.


Placement metrics

Quality metrics for layout:

Area, power, and delay.

(price, power, and performance)

Area and delay determined by wiring.

How do we judge a placement without

wiring? Estimate wire length without

actually performing routing. (Manhattan distance)


Wire length measures

Estimate wire length by distance between

components.

Possible distance measures:

Euclidean distance (sqrt(x2 + y2));

Manhattan distance (x + y).

Multi-point nets must be broken up into trees

for good estimates.


Logics vs. Physics

Physical View

Logical View


Wire length as a quality metric

A placement A better placement


How to evaluate a placement

Almost the same way for the floorplan

Calculate the total Manhattan distances from

gate to gate

Using simulation annealing, zone

refinement….

Two-ways (multi-ways) partitioning or

clustering can be used too.


How to Evaluate a Floorplan?

Using: Cost Function

Estimate the Manhattan Distance estimate the

total wire length.

Penalize the critical nets.

Calculate the “total cost”

The lower cost is the better solution.


Placement techniques

Can construct an initial solution, improve an

existing solution.

Pair-wise (Zone refinement) interchange is a

simple improvement metric:

Interchange a pair, keep the swap if it helps wire

length.

Heuristic determines which two components to

swap.


Placement by partitioning

Works well for components of fairly uniform

size.

Partition netlist to minimize total wire length

using min-cut criterion.

Partitioning may be interpreted as 1-D or 2-D

layout.


Block placement

Blocks have:

area;

aspect ratio (length : width).

Blocks may be placed at different rotations

and reflections.

Uniform size blocks are easier to interchange.


Min-cut bisecting partitioning


Min-cut bisecting partitioning,

cont’d

Swapping A and B:

B drags 1 net;

A drags 3 nets;

total cut increase: 4 nets.

Conclusion: probably not a good swap, but

must be compared with other pairs.


Kernighan-Lin algorithm

Compute min cut criterion:

count total net cut change.

Algorithm exchanges sets of nodes to perform

hill-climbing—finding improvements where

no single swap will improve the cut.

Recursively subdivide to determine placement

detail.


Simulated annealing

Powerful but CPU-intensive optimization

technique.

Analogy to annealing of metals:

temperature determines probability of a

component jumping position;

probabilistically accept moves.

start at high temperature, cool to lower

temperature to try to reach good placement.


Simulation Annealing

From VIA’s

VLSI Design



Simulated annealing (SA) is a probabilistic technique for

approximating the global optimum of a given function.

Specifically, it is a meta-heuristic to approximate global

optimization in a large search space. It is often used

when the search space is discrete (e.g., all tours that visit

a given set of cities). For problems where finding an

approximate global optimum is more important than

finding a precise local optimum in a fixed amount of

time, simulated annealing may be preferable to

alternatives such as gradient descent. -- wiki


Machine Learning

Mitchell, T. (1997). Machine Learning. McGraw

Hill. p. 2. ISBN 0-07-042807-7.

"A computer program is said to learn from experience E with

respect to some class of tasks T and performance measure P if its

performance at tasks in T, as measured by P, improves with

experience E."

Where:

E: placement rules

T: placement

P: cost function

https://en.wikipedia.org/wiki/International_Standard_Book_Number

https://en.wikipedia.org/wiki/Special:BookSources/0-07-042807-7


Buffer Insertion

How many ?

Where?

What’s size?


Placement

Wire length

Hook

Crystallization (Hard seeds)

Min-cut

Kernighan-Lin

Zone refinement


Machine Learning


Routing


Sliceable floorplan

用來決定哪個channel先來做繞線的順序


Sliceability property

A sliceable floorplan can be recursively cut in

two without cutting any blocks.

A sliceable floorplan is guaranteed to have no

windmills, therefore guaranteed to have a

feasible order of routing for the channels.

Sliceability is a property for floorplans.


Windmills

Can create an un-routable combination of

channels with circular constraints:


Blocks and Wiring

Cannot ignore wiring during block placement—large wiring areas may force rearrangement (re-placement) of blocks.

Wiring plan must consider area and delay of critical signals.

Blocks divide wiring area into routing channels.

Plan the critical routing


Placement & Routing

Placement will affect routing. We need to well

plan for the placement….

So a good floorplan is the key for the better

routing solutions.


Channel definition

Channels end at block boundaries.

Several alternate channel definitions are

possible:


Channel definition changes with

block spacing

Changing spacing changes relationship

between block edges:


Channel graph


Channel graph usage

Nodes are channels, edges placed between

two channels that touch.

Channel graph shows paths between channels.

Channel graph can be used to guide global

routing.


Channels must be routed in order

Wire out of end of one channel creates pin on

side of next channel:channel B

channel A

constraint


Routing

Global Routing

Local Routing (Detail routing)

Channel Routing

Switch Box routing


Global routing

Goal: assign wires to paths through channels.

Don’t worry about exact routing of wires

within channel.

Estimate channel height from global routing

finding congestion.


Types of Local Routing

Channel routing:

channel may grow in one dimension to

accommodate wires.

Switchbox routing:

cannot grow in any dimension;

pins are on all four sides, fixing dimensions of the

box.


Channels and switchboxes


Line probe routing

Heuristic method for finding a short route.

Works with arbitrary combination of

obstacles.

Does not explore all possible paths—not

optimal.


Line probe example

A

Aline 1

line 2


Channel utilization

Want to keep all channel utilization to be

balanced --- minimize wasted area.

Important: route timing critical signals first.

Shortest path may not be best for global

wiring.

In general, may need to rip-up wires and

reroute to improve the global routing.


Switchbox routing

Can’t expand a switchbox to make room for

more wiring.

Switchbox may be defined by intersection of

channels.


Routing order and switchboxes

Switchboxes frequently need more

experimentation with wiring order because

nets may block other nets:


Routing

Major phases in routing:

global routing assigns nets to routing areas;

detailed routing designs the routing areas.

Net ordering is a major problem. Order in

which nets are routed determines quality of

result. Net ordering is a heuristic problem.


Maze routing

Will find shortest path for a single wire, if

such a path exists.

Two phases:

Label nodes with distance, radiating from source.

Use distances to trace from sink to source,

choosing a path that always decreases distance

to source.


Detailed routing

Dogleg router breaks net into multiple

segments as needed.

Try to minimize number of dogleg segments

per net to minimize congestion for future

nets.

One good heuristic—use left-edge criterion on

each dogleg segment to fill up the channel.


Tries to minimize number of vias as well as

number of tracks.

Temporarily satisfies vertical constraints by

adding blank space between pins.

May route in both directions on same layer.


Over-Cell Routing

channel A


Maze routing example


Sibling routing

Mentor/Siemens’ toolReduce R/C

Increased Reliability


Sibling routing (2)

Mentor/Siemens’ tool



m-BIST, 1149.1,

Scan Insertion,

…(Spare)

RC Extraction

(3D)

Floor Planning

Macro/Power/Std

Placement

Global/Local

Routing

WLM, Set load,

EDIF, HDL (gate),

SDC

Physical

compiler

Signal Integrity *

Delay *

Calculation

Buffer insertion,

CTS, (Spares)

Scan Reordering

Power Analysis

IR/EM *

IPs: Analog, PLL,

Std, IOs , MEM, …

Optional, ( )

Data format

Standard Flow

Notes

Formality *

SDF, Set load, SPF


Back Annotation

Post Simulation *

Synthesis

Chip RTL,

Constrains

STA *

Test Pattern

Generation

Tapeout

DRC/ERC/LVS

Antenna Check *

GDSII



m-BIST, 1149.1,

Scan Insertion,

…(Spare)

RC Extraction

(3D)

Floor Planning

Macro/Power/Std

Placement

Global/Local

Routing

WLM, Set load,

EDIF, HDL (gate),

SDC, GPF/UPF

Physical

compiler

Signal Integrity *

Delay *

Calculation

Buffer insertion,

CTS, (Spares)

Scan Reordering

Power Analysis

IR/EM *

IPs: Analog, PLL,

Std, IOs , MEM…

Optional, ( )

Data format

Standard Flow

Notes

Formality *

SDF, Set load, SPF


Back Annotation

Post Simulation *

Synthesis

Chip RTL,

Constrains, GPF

STA *

Test Pattern

Generation

Tapeout

DRC/ERC/LVS

Antenna Check *

GDSII


Schedule

11. 05/06/22 Chapter 7 (Routing)

12. 05/13/22 Chapter 7 (Special nets, b4TO)

13. 05/20/22 Chapter 8 (Architecture)

14. 05/27/22 (QZ2) Chapter 8 (Architecture)

15. 06/03/22 端午節

16. 06/10/22 Chapter 9 (Examples)

17. 06/17/22 Final Examination

18. 06/24/22 Exam review, What’s Next?


Special Nets

Special Nets

Power/ground routing.

Clock routing.

Off-chip connections.

Boundary Scan


Power and Ground


Power distribution

Must size wires to be able to handle current

— Avoid electro-migration

requires designing topology of VDD/VSS

networks.

Keep power network in metal

— requires designing planar wiring.


Low-resistance jumper

Avoid this:


Power and ground lines

VDD

VSS


Power tree design

Each branch must be able to supply required

current to all of its subsidiary branches:

Ix = S b e x Ib


Planar power/ground routing

theorem

Draw a dividing line through each cell such

that all VDD terminals are on one side and

all VSS terminals on the other.

If floorplan places all cells with VDD on same

side, there exists a routing for both VDD and

VSS which does not require them to cross.

cellVDD

VDD

VSS

VSS


Planar routing theorem example


Power supply noise

Variations in power supply manifest

themselves as noise into the logic gates.

Power supply wiring resistance creates

voltage variations with current surges.

Voltage drops on power lines depend on

dynamic behavior of circuit.

Ground bounce!!

Power bounce!!


Tackling power supply noise

Must measure current required by each block

at varying times.

May need to redesign power/ground networks

to reduce resistance at high current loads.

Worst case, may have to move some activity

to another clock cycle to reduce peak

current.


IR Drop on the Power Routing


IR Drop


Static Estimation

Temp and Voltage

Freq and Voltage


Power Estimation

P = C V2 fVdd

Vh

Vl

Gnd

Vdd’


Dynamic Power


MV and Level Shifters


Clock


Clock Networks

For synchronized designs, data transfer between

functional elements are synchronized by clock

signals

Clock signal are generated externally (e.g., by PLL)

Clock period equation

Clock period >= td + tskew + tsu


Clock Skew

Clock skew is the maximum difference in the

arrival time of a clock signal at two different

components.

Clock skew forces designers to use a large time

period between clock pulses. This makes the

system slower.

So, in addition to other objectives, clock skew

should be minimized during clock routing.


Clock distribution

Goals:

deliver clock to all memory elements with

acceptable skew;

balanced rising and falling edges;

deliver clock edges with acceptable sharpness.

Clocking network design is one of the greatest

challenges in the design of a high speed

large chip.


Clock Issues

SkewThe Most concern of clock networks

For increased clock frequency, skew may contribute over 10% of the system cycle time

Powervery important, as clock is a major power consumer

It switches at every clock cycle

NoiseClock is often a very strong aggressor

May need shielding

DelayNot really important

But slew rate is important (sharp transition)


Clock delay varies with position


H-tree


X-tree


Clock distribution tree

Clocks are generally distributed via wiring trees.

Want to use low-resistance interconnect to minimize delay.

Use multiple drivers to distribute driver requirements—use optimal sizing principles to design buffers.

Clock lines can create significant crosstalk.


Clock Tree


Clock trees

Clock Source

FF FF FF FF FFFF FF FFFF FF

root

leaf / sink


Clock trees

Clock Source

FF FF FF FF FFFF FF FFFF FF


Clock Sources

Generated clocks might be optimized by synthesizer. We might not be able to find the root.

RST1n

CLK1

CLK_sys1

CLK_sys2

CLK2

CLK3RST2n


Clock Mesh

Clocks are generally distributed via wiring

mesh.

Want to use multiple clock driver minimize

skew.

Clock drivers fighting can create significant

power consumption.


Clock routing for the power

Clock Tree Synthesis


Clock and Multiple Voltages

The problem is: Clock

domains might not be

coherent with the

power domains!!



m-BIST, 1149.1,

Scan Insertion,

…(Spare)

RC Extraction

(3D)

Floor Planning

Macro/Power/Std

Placement

Global/Local

Routing

WLM, Set load,

EDIF, HDL (gate),

SDC, GPF/UPF

Physical

compiler

Signal Integrity *

Delay *

Calculation

Buffer insertion,

CTS, (Spares)

Scan Reordering

Power Analysis

IR/EM *

IPs: Analog, PLL,

Std, IOs , MEM…

Optional, ( )

Data format

Standard Flow

Notes

Formality *

SDF, Set load, SPF


Back Annotation

Post Simulation *

Synthesis

Chip RTL,

Constrains, GPF

STA *

Test Pattern

Generation

Tapeout

DRC/ERC/LVS

Antenna Check *

GDSII


Wire load models are not enough

Mentor /Siemens


Why Needs Antenna Rules

Charging in semiconductor processing

– many process steps use plasmas, charged particles

– charge collects on conducting poly, metal surfaces

– capacitive coupling: large electrical fields over

gate oxides

– stresses cause damage, or complete breakdown or

– induced Vt shifts affect device matching


Antenna Effect by Plasma process

Field Ox. Field Ox.

GateSource Drain

p-Si substrate

n+ n+n- n-

Met1

Met2

damage

Plasma


Using protection diodes to drain the charging from the dielectric of

the floating MIM capacitor

Plasma Charging Damage of Floating

Metal-Insulator-Metal Capacitors


Off-chip connections

The package holds the die. Packages can

introduce significant inductance.

Pads on the chip allow the wires on chip to be

connected to the package. Pads are library

components which require carefully design.


IC package

From VIA’s

VLSI Design


Structure of a typical package

lead frame


Package structure

Package body is physical/thermal support for

chip.

Cavity holds chip.

Leads in package connect to pads, provide

substrate connection to chip.


Pin inductance

Package pins have non-trivial inductance.

Power and ground nets typically require many

pins to supply required current through the

packaging inductance.


Pin inductance example

Power circuit including pin inductance:


Pin inductance example, cont’d

Voltage across pin inductance:

vL = L diL / dt

Current surge into chip causes inductive

voltage drop:

L = 0.5 nH;

iL = 1A;

vL = 0.5 V.


I/Os

Pads are placed on top-layer metal to provide

a place to bond to the package.

Pads are typically placed around periphery of

chip.

Some advanced packaging systems bond

directly to package without bonding wire;

some allow pads across entire chip surface.


Pad frame architecture

V’dd


Pad frame design

Must supply power/ground to each pad as well as chip core.

Positions of pads around frame may be determined by pinout requirements on package.

Want to distribute power/ground pins as evenly as possible to minimize power distribution problems.


Input pads

Main purpose is to provide Electro Static

Discharge (ESD) protection.

Gate oxide is very sensitive—can be

permanently damaged by high voltage.

Static electricity in room is sufficient to

damage CMOS ICs.


Input pad circuits

Resistor is used in series with pad to limit

current caused by voltage spike.

May use parasitic bipolar transistors to drain

away high / low voltages:

one for positive pulses;

another for negative pulses.

Must design layout to avoid latch-up.


Introduction to ESD

靜電(Static Charge)

物質表面經由某種過程(如摩擦和感應)而失去電子或得到電子,使帶靜止的電荷.

靜電放電(Electrostatic Discharge,ESD)

電位不同之物體間的電荷移轉,不一定伴隨有電弧或火花產生.

高電流(~Amps),短時間(~ns)的現象


Why need ESD Protection?

靜電放電(Electrostatic Discharge, ESD)是造成大多數的電子元件或電子系統受到過度電性應力(Electrical Overstress,EOS)破壞的主要因素.這種破壞會導致半導體元件以及電腦系統等,形成一種永久性的毀壞，因而影響積體電路的電路功能,而使得電子產品工作不正常.

而靜電放電破壞的產生,多是由於人為因素所形成,但又很難避免.電子元件或系統在製造,生產,組裝,測試,存放,搬運等的過程中,靜電會累積在人體,儀器,儲放設備等之中,甚至在電子元件本身也會累積靜電，而人們在不知情的情況下，使這些物體相互接觸,因而形了一放電路徑,使得電子元件或系統遭到靜電放電的肆虐。

如何才能避免靜電放電的危害呢？除了加強工作場所對靜電累積的控制之外，必須在電子產品中加入具有防患靜電放電破壞的裝置.首先必需考量這額外裝置的效能,如何處理才能達到有效防護的功用.而這裝置應放在何處?以及在工業上的大量應用中,如何才是最省成本的設計方式？這些問題都應一一處理及考慮.

在防護裝置的設計上,從加強積體電路本身對靜電放電的耐受能力上著手,可以解決晶片包裝後,組裝,測試,存放,搬運等所遭遇到大多數靜電放電的問題.


Model of ESD Events

人體放電模式 HBM Human-Body Model

機器放電模式 MM Machine Model

元件放電模式 CDM Charged-Device Model


Human-Body Model

模擬人體放電

⊕⊕ ⊕⊕ ⊕⊕ ⊕ ⊕

⊕ ⊕ ⊕⊕ ⊕

⊕⊕


Human-Body Model Standards

MIL-STD-883H Method 3015.7 美國軍標883

ESDA STM5.1-2007 美國靜電協會

JEDEC EIA/JESD22-A114-F 電子工業協會(2008.12)

AEC-Q100-002-REV-C 汽車電子協會

JS-001-2011 Joint ESDA/JEDEC


Machine Model


Machine Model Standards

ESDA STM5.2-1999 美國靜電協會

JEDEC EIA/JESD22-A114 電子工業協會

AEC-Q100-003-REV-E 汽車電子協會


Charged Device Model


Charged Device Model Standards

ESDA STM5.3.1-1999 美國靜電協會

JEDEC EIA/JESD22-C101-C 電子工業協會(將受到更加重視)

AEC-Q100-011-B 汽車電子協會(強制執行項目)


Comparison of 1KV HBM,MM,CDM

The CDM discharge is 100X faster than HBM and MM.

The peak current can be 40X HBM pulse.


System ESD Test

IEC 61000-4-2

Level 4 & Class B

Sharp tip:

Contact mode

Round tip:

Air mode


ESD Tests

Machine Mode; Human Body Mode, and CDM


Damnage


Basic Idea for Protection


Basic Idea for Protection

a.由製程端處理，需挑選有isolation 的元件

b.加適當的 guard ring 防護，並避免寄生的 PNP 或 NPN

turn on

c.設計 detection circuit/clamp 來bypass

晶焱


Testing Equipments


Output pad circuits

Must be able to drive capacitive load of pad +

outside world.

May need voltage level shifting, etc. to be

compatible with other logic families.


Output pad circuit, cont’d.

Pad open


Three-state pad

Combination input/output, controlled by mode

input on chip.

Pad includes logic to disconnect output driver

when pad is used as input.

Must be protected against ESD.


Three-state pad circuit

0 1

10


Pads


M3(VIA array) M2(VIA array)

PL(None) SUB(None)

A Real case

M4

M1(None)


Moisture Isolation

141

Seal Ring


Boundary scan

Boundary scan is a technique for testing chips on boards. Pads on chips are arranged into a scan chain that can be used to observe and control pins of all chips.

Requires some control circuitry on pads along with an on-chip controller and boundary-scan-mode control pins. (XOR, NAND tree)

IEEE 1149.1 (boundary scan) and scan insertion might solve partial of the problem.


Sequential testing

Much harder than combinational testing—

can’t set memory element values directly.

Must apply sequences to put machine in

proper state for test, be able to observe

value of test.



m-BIST, 1149.1,

Scan Insertion,

…(Spare)

RC Extraction

(3D)

Floor Planning

Macro/Power/Std

Placement

Global/Local

Routing

WLM, Set load,

EDIF, HDL (gate),

SDC , GPF/UPF

Physical

compiler

Signal Integrity *

Delay *

Calculation

Buffer insertion,

CTS, (Spares)

Scan Reordering

Power Analysis

IR/EM *

IPs: Analog, PLL,

Std, IOs , MEM, …

Optional, ( )

Data format

Standard Flow

Notes

Formality *

SDF, Set load, SPF


Back Annotation

Post Simulation *

Synthesis

Chip RTL,

Constrains

STA *

Test Pattern

Generation

Tapeout

DRC/ERC/LVS/ESD

Antenna Check *

GDSII

CKT been changed!!Why??!!

Why we need these two checks??!!

C = A*B;


Homework

Homework:

Chapter 7: 7-3, 7-4

Please Check on internet what’s “simulation

annealing”

Schedule - ntut.edu.tw

Documents

Transcript of Schedule - ntut.edu.tw