scaling of mos parameters

106 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-18, NO. 1, FEBRUARY 1983

Impact of Scaling on MOS Analog Performance

STEPHEN WONG AND C. ANDRE T. SALAMA, MEMBER, IEEE

Abstract–A first-order analysis of the impact of scaling on MOS ana-log performance under moderate scrding conditions is presented in thispaper. Aasumirtg a polysilicon gate iort-implanted MOS techitology,quasi-constant voltage (QCV) scaling is shown to be the optimal scalinglaw, offering the best overall analog performance and resulting in an in-crease in functional density, gain-bandwidth product with a moderatedegradatiotr in gain, and signal-t~noise ratio. The first-order anafysisagrees fairly well with computer simulation. A typicaf case study showsthat under moderate scaling conditions, CMOS can generally offer ahigher voltage gain when compared to depletion load NMOS and is thepreferred technology for scaJed analog implementations.

I. INTRODUCTION

w

ITH the ever increasing complexity of very large scale

integrated circuits, it has become highly desirable to

integrate analog and digital circuits on a single silicon chip.

The primary VLSI focus has been on those technologies whichpermit high density integration of analog and digital circuitson a single chip. The most useful MOS technologies in thiscontext are FJMOS and CMOS [ 1] .

The increasing complexity of digital MOS VLSI was spurredby the concept of device scaling [2]. The density of digital cir-cuits has increased continuously and the area consumed by theanalog portion of a digital-analog circuit has become relatively

larger. This fact has provided a strong impetus for scaling the

analog portion of the circuit as well as the digital one.

The scaling of analog circuits can benefit from the consider-

able amount of information available on the scaling of digitalMOS 1(2’s. Various scaling laws have been proposed and aresummarized in Table I [2] , [3] . The first of these is constantfield (CE) scaling [2] which was introduced as a means of al-leviating the difficulties arising from two-dimensional parasiticeffects associated with short channels in MOS transistors.Basically, CE scaling involves a reduction of voltages, currents,

and lateral and vertical dimensions by a factor A afid an in-crease in the substrate doping concentration by the same fac-tor A (k > 1). The linear reduction of voltage associated withCE scaling generally results in a sizeable deterioration of thesignal-t&noise ratio as well as a lack of TTL interface com-patibilityy. To avaid thi~ difficulty, the current trend is taward~nonconstant field scaling in the form of constant voltage (CV)or quasi-constant voltage (QCV) scaling [3]. Constant voltagescaling implies a fixed nonscaled power supply (compatiblewith TTL) and a slower than X (approximately fi) scaling ofgate-oxide thickness to reduce oxide field and improve reli-

Manuscript received December 4, 1981; revised April 23, 1982. Thiswork was supported by the Natural Sciencesand Engineering ResearchCouncif of Canada.

The authors are with the Department of Electrical Engineering, Uni-versity of Toronto, Toronto, Ont., Canada MSS 1A4.

TABLE ISCALINGLAWS

CE QCV Cv

Voltages ~-l ~-tp 1Lateral dimensions A k ~-l

Vertical dimensions k;: k~: ~-1/2

Doping concentration L A A

ability and yield. Quasi-constant voltage scaling, ini~hes a

slower than k (taken as m for convenience sake) decrease involtage while the other factors scale as in the CE case.

QCV scaling was found to provide optimum drive current

capability in digital VLSI MOS circuits [3]. Although this fac-

tor is an important criterion in digital applications, parameters

such as gain, bandwidth, and signal-to-noise ratio are more suit-

able criteria to evaluate the performance of analog circuits.One of the objectives of this paper is to investigate the im-

pact of the scaling laws discussed above on MOS analog com-ponent performance. Only moderate scaling factors are consid-

ered and no attempt is made to approach the ultimate scalinglimits being considered for digital circuits [4]. Present dayMOS analog circuits have minimum channel lengths of about

8 vm. The scaling factors considered here will be limited to

the range A = 1 to X =4. A scaling of h = 4 would reduce the

minimum channel length to 2 #m and the circuit area by ap-proximately a factor of 16 while still keeping second-order ef-fects within bounds [5] , [6]. Any further scaling would lead

(as will be seen from the following discussion) to unacceptabledegradation in analog performance. Another objective of thispaper is to establish the optimum technology for scaled ana-log MOS circuits and to evaluate the performance of a scaledMOS analog op amp as a typical example of analog circuitimplementation.

Many intricate technology related problems are expectedduring device scaling. Presently, innovative processing tech-

niques are being applied to reduce such problems as devicemismatch, junction depth control, and reliability of scaleddown oxide layers. It k neither the aim fior the ~cope of this

paper to suggest solutions to these related problems, but merelyto investigate the effects on analog performance when scalingis achieved.

II. MOSFET MODELING

MOS analog integrated circuitsl consist for the vast majority

of MOSFET’S used as drivers, active loads for analog switches,

lion-imp~nted silicon gate technology is assumed throughout thediscussion.

0018-9200/83/0200-0106$01 .00 @ 1983 IEEE

WONGAND SALAMA: SCALINCJAND MOS ANALOG PERFORMANCE 107

as well as MOS capacitors, resistors (diffused orpolysilicon),and interconnections.

Since the MOSFET’S are the most critical components inany analog implementation, the discussion will focus mainlyon those MOSFET parameters which have a direct influence

on analog performance.

A. I-V Characteristics

In order to account for second-order effects which may arise

due to scaling, a set of analytical equations must be used.Modeling of small geometry (short and narrow channel) de-vices have been treated extensively by many authors [7] - [10].These models generally include the following phenomena: 1)threshold dependence on two-dimensional charge sharing ef-fects [11 ], [12], 2) mobility-degradation due to increased

normal and lateral fields [13], and 3) velocity saturation ofcarriers causing premature saturation of current and lower out-put conductance [14], [15].

When moderate scaling effects are considered, two additionalfactors must be considered. These are 1) mobility degradationdue to impurity scattering when the effective substrate dopingexceeds 5 X 1016 cm”3 [16], and 2) gain reduction via feed-

back through the parasitic drain and source resistances.The saturation region of the MOSFET plays an important

role in determining analog performance parameters such as

transconductance, output resistance, and voltage gain. The

set of equations selected for the analysis are based on a semi-empirical model of the MOSFET operation in this particularregion of operation.

The threshold voltage VT of the device can be expressed as

v== VTO - AVT8+AVTN (1)

where VTO is the threshold voltage for a large geometry deviceand AVTsand A VTN are the corrections for short and narrow

channel effects, respectively [7] . VTOis given by

(2)

where r$&fSis the work function difference between gate and

bulk material, OF is the Fermi potential given by

(3)

where NB is the bulk doping concentration under the channel

and Qss, QB are the oxide and bulk charges, respectively. Thelast term in (2) represents the effect of the ion implant used to

adjust the threshold voltage. NiD is the effective implant dose

and D is the implant depth which is assumed to be very shallow.Mobile carriers in the channel of a scaled MOST normally

experience scattering effects due to the electric fields and in-

creased impurity levels. This leads to a significant degradationof the channel mobility p which is usually expressed as

(4)

where P. is the zero field mobility and 6 ~, 8 ~ are second-order

parameters describing the degradating effects of high field and

high doping concentration on mobility, respectively. Above

saturation, the parameter 81 is defined as

‘D sat&=l+&~-VT)+~

c

(5)

where O is a constant (typically 3 X 10-7 cm/V), EC is the crit-ical field for velocity saturation (2 X 104 V/cm for NMOS and

2 X 105 V/cm for PMOS), VD,~atis the saturation voltage andis taken as (VG- VT)for a first-order analysis. The parameter8 ~ accounts for impurity scattering effects and is defined as

‘2=(’+:10J”2The gain constant ~ of the transistor is defined as

(6)

(7)

where Z is the channel width and 8 ~ accounts for the feedback

degradation due to the source resistance R~

?i3 = 1 +~~,(v~ - VT). (8)

R~ is proportional to the length but inversely proportional to

the width, depth, and doping of the source junction. The ef-fects of the inversion layer capacitance and contact resistance

on /3 are neglected here. These effects are only relevant for

channel lengths below 1.5 pm [6].The saturation current of the device can be expressed as

(9)

where 8~ is a second-order parameter which takes into accountthe body effect on the channel. ti4 is defined as

aq=l+ ‘-Y

2(2@ - v~)l/2

where

(lo)

(11)

where es is the dielectric constant of silicon.The transconductance in the saturation region can be ex-

pressed as

(12)

B.Output Conductance

The output conductance of the device in the saturation re-

gion is critical in determining the voltage gain of inverters aswell as the output impedance of current source. Three impor-tant phenomena affect the channel conductance of the satu-rated enhancement mode MOSFET. These are 1) classicalpinchoff [17], 2) velocity saturation [14], [15], and 3) feed-back caused by drain induced barrier lowering [18], [19].

For moderate channel lengths, the first two phenomenadominate. The current in the device beyond saturation is


increased by channel length modulation and is given by

LID = ID, sat ~ (13)

For long channel lengths, AL is the reverse bias depletion

width formed between the drain and the channel and is de-fined as

AL ‘~1 [~D - ~D,~~~]l/2 (14)

where

K, = [2eJqN~]112. (15)

As the internal field in a scaled device increases as a result of

nonconstant field scaling, velocity saturation of mobile carriers,and the deterioration of the gradual channel approximation

make it necessary to modify the drain depletion length AL asfollows [14] , [15]:

[( )EPK~ 2 11/2

EPK;AL= — +K~(VD - VD,Sat) - —

2 2(16)

where EP is the lateral field at the drain during channel pinch-off. Out of convenience, EP is usually equated to the critical

field for velocity saturation EC [20] . A more realistic valueof EP has been derived by Rossel [15] to ensure the con-tinuity of current and conductance in the triode and satura-tion regions. His expression for EP can be approximated by

(17)

For moderate Ep, (16) can be rewritten as (see Appendix I)

AL = K1(VD - VD,,~~)112&5 (18)

where 6 ~ is a correction factor for channel shortening given by

EPKI85=1-

2(VD - v~,,aJ1/2 “(19)

Differentiating (13), using the value of AL given by (18),

yields the output conductance

dID ID,satKlgd~ . —dVD = ‘2L(VD - vD,m)

112fi6

where 8 ~ is defined as

()AL 266. l. —..—L“

(20)

(21)

From (20), gd~ is proportional to ID,,at, as observed experi-mentally in moderately scaled devices.

For very short channel lengths, extensive drain induced bar-rier lowering (DIBL) occurs resulting in a large dependence ofthreshold voltage on VD as observed by Masuda [21] . As a

direct consequence of this effect, gd. will be directly propor-tional to ( VG - VT) and inversely proportional to L 3 (asshown in Appendix II). This strong dependence of gd~ on Lcannot be tolerated in analog applications and in general theDIBL regime must be avoided.

C. Subthreshold Current

The exponential dependence of the subthreshold current

plays an important role in analog applications. For VG< VT~nd VD>>-kT/q,as 2

the weak inversion current can be expressed

(22)

where VOn is the turn on voltage at a surface potential @~=

1.5 OF, Cd is the surface depletion region capacitance defined

as

(23)

and n is given by

~=l+g

co -(24)

Due to the exponential nature of the subthreshold current, it

does not scale linearly with A. A commonly used figure ofmerit to describe subthreshold behavior is the slope S~ of thelog ID versus VG curve. S~ can be expressed as

d log lD,~at qs.= .—

dVG 2.3 nkT”(25)

In an analog switch, for instance, S~ is a significant factor in

determining the on-off current ratio of the device.

D.Noise

The noise in MOS devices, working at low frequencies, is

high due to the dominant contribution of l/~ noise [22].The rms equivalent gate noise voltage, in this case, can beexpressed as

‘..=($$%1’2 (26)

where an is a constant dependent on the interface trap den-

sity at the Si-Si02 interface, Af is the bandwidth and f is

the frequency.

HI. EFFECT OF SCALING ON MOS PARAMETERS

In this section, the effect of scaling on the MOS deviceparameters previously discussed in first investigated. Theeffect of scaling on MOS circuit components is then dis-cussed. The fact that scaling will limit the accuracy and theability to match components is not considered in detail heresince it is technology dependent.

A. Subthreshold Current

In order to avoid large subthreshold currents (and the onsetof substantial DIBL), the long channel index M suggested by

zAS~~~i~g the surface state density at the Si-SiC)2interface to benegligible.

WONGAND SALAMA: SCALING AND MOS ANALOG PERFORMANCE 109

Brews etal. [23] can be used. Thisindex isdefinedas

A[(xjto) (WS + w~y] 1/3M.

L(27)

where A is a constant and W8, WD are the widths of sourceand drain depletion regions, respectively, and are given by

[ 11/2

w~= # (2@~- v’)

[ 11/2

WD . * (21#~- v’+ v~) .

(28)

(29)

For xi, W~, WD, and L inmicrons and toin& the value of Ais 0.41(A)l/3for n-channel devices. Upon scaling, a value ofM < I will guarantee that long channel subthreshold behavior

is maintained. When M >1 undesirable short channel effectsare expected.

B. Threshold Voltage

For successful scaling, the threshold voltage must scale with

the other voltages. However, due to the nonsalable term

(@mrs+ 2@F) in (2), it is unlikely that VT can be scaled prop-erly without compensation. In general, scaling of this term

produces a VTwhich is too large for CE scaling and too smallfor QCV scaling. The problem is more critical in the PMOScase (assuming an n+ polysilicon gate technology), where

(@MS+ 2@F) is more significant. While some adjustment canbe made by varying VB in NMOS technology, this is not pos-

sible in CMOS.Fortunately, ion implantation can be used in both NMOS

and CMOS to adjust the threshold voltage. In a typical de-vice which uses a shallow implant as a threshold adjust, it iscommon to obtain cancellation between the implant termand (@MS+ 2@F), whenever necessary3, so that VT becomesapproximately

(30)

(positive sign applies for NMOS while the negative sign appliesfor PMOS). If QSS << QB, the above equation will generally

yield the desired threshold voltages.With (30), proper scaling for VTis easily achieved under the

CV and QCV laws, resulting in a threshold voltage scaled by=1 and XA-li2, respectively. To ensure that (30) remainsvalid, one requires that the condition

(31)

holds under scaling. Since it is desirable that lVj scales with A,

this implies that the implant depth D must scale with A-1/2 inthe CV case, and remain f~ed for QCV and CE scaling. How-

ever, adjustment of D may be necessary to scale VTwith I/a(instead of l/@) under the CE law, and to compensate forthe second-order short channel and narrow width effects.

s For instance, in an n+ polysificon gate p-well CMOS Process, thePMOSthreshold voltage is adjusted in this manner.

TABLE 11DEVICESCALING

CE Qcv w Equation

‘D,sat~-1 1 ~1/2 9

gm 1 ~1/2 ~1/2 12gds(enh) 1 ~3/4 A 20{ds(dep) 1 ~1/4 ~1/2 34cd

Els;‘wM

1 ~-1/4 1 23

252627

Nevertheless, proper scaling of VTseems feasible using ion im-plantation and has been assumed in the following discussion.

C First-OrderParameter Scaling

In the model already described, the 8‘s represent second-

order effects which do not scale linearly with A. Their mag-nitudes are strong functions of the initial unscaled device andthe scaling laws. To obtain a first-order estimate of the effectof scaling on device parameters as well as to keep the analysisindependent of the unscaled conditions, the parameters 6 arefirst assumed to be unity. This implies an ideal long channelMOSFET as the unscaled device. Justification for this assump-tion, and a comparison of first-order scaling estimates with

computer simulated results on analog performance, taking into

consideration the effect of ti‘s, are given in Section V.The first-order scaling for some relevant device parameters

are listed in Table II. Limitations can be expected from the

parameters S$ and Vng,which do not scale-down as desired.

D. Capacitor Scaling

In MOS technology, capacitors are realized between metal

and heavily doped silicon or between two layers of heavilydoped polysilicon. Thermally grown silicon dioxide is used

as the dielectric. Scaling of capacitors is straightforward.

A direct scale down of the surface area and dielectric thick-ness lead to a reduction in total capacitance. However, diffi-culties arise in absolute accuracy and matching of componentvalues as the effects of misalignment and fringing become rela-tively more important. Electron quantization noise may also

become a problem as capacitors become smaller.

E.Resistor Scaling

In MOS technology, resistors are fabricated using either dif-fused layers or polysilicon layers deposited on oxide. The lat-ter alternative is preferred since it produces minimal parasitic

capacitance. Scaling, again, is relatively simple; however ac-curacy and matching as well as conduction mechanisms [24]in the polysilicon become serious limits as the resistors be-come smaller.

F.Interconnection Scaling

Three items are of prime concern in interconnection scaling.

These are electromigration, in the very thin, narrow aluminum


conductors, contact resistance in the very shallow junctions,

and polysilicon interconnection sheet resistance. For the scal-ing conditions under consideration here, the first two items do

not present serious constraints. As far as the third item isconcerned, refractory metal silicides, which offer low sheet re-sistance, are a good alternative to polysilicon. In addition, itis reasonable to expect that, at least some of the longest inter-

connections will not scale-down at ail, resulting in adverse ef-fects on parasitic capacitance and line driving capabilities.

IV. EFFECT OF SCALING ON ANALOG

BUILDING BLOCK PERFORMANCE

This section investigates the scaling tendencies of some basic

analog building blocks with the objective of determining theoptimal scaling law for analog applications. Two technologiesare considered: CMOS and NMOS with depletion load.

A. Gain Stage Performance

The most useful figure of merit in evaluating performance ofgain stages is the voltage gain. In a CMOS stage, this gain isgiven by

A ~,CMOS=- gin

kis,rs + gd.,p)(32)

where gd$ ~ and g&, ~ are the n- and p-channel device outputconductance respectively, as defined by (20). In NMOS tech-nology, where a depletion device is used as load, the bulkthreshold feedback effect normally dominates over channellength modulation effects in determining gal,, d~~ [X)] . The

voltage gain, in this case, is given by

17mAv, NMos =-— (33)gals, dep

where

gd~,dep = 1~T,dep I(&D’:V. + 4$7) (34)

where VT,d~p is the threshold voltage of the depletion modedevice, VOis the quiescent output voltage, and VDDis the sup-ply voltage.

B. Op Amp Performance

Since the operational amplifier is one of the basic buildingblocks in analog circuitry, an evaluation of its performancesubject to scaling would be useful, For such an analysis, thefollowing performance indices must be considered.

Voltage Gain Au–In a typical two-stage op amp which uses aMiller capacitor for compensation, the voltage gain is

(35)

Unity Gain Bandwidth (GB W)–The unity bandwidth is

mainly determined by the transconductance of the first stage

gm 1, and the compensation capacitor CC and can be expressedas

fJBw . ‘~cc “

(36)

TABLE IIISCALINGOFANALOGCIRCUITS

CE Qcv Cv Equation

Gain StagesA V,CMOS 1 ~-1/4 ~-1/2 32A V,NMOS 1 ~ 1/4 1 33

Ou Amu

The GBW is normally determined by the second parasitic poleof the amplifier which can be approximately expressed as

(37)

where gm2 is the effective transconductance of the secondstage, and Cl and C2 are the input (gate) and load capaci-tances associated with the second stage [25]. From (36) and

(37), it appears that CC will be proportional to (Cl + C2). If

one assumes C2 to be the input (gate) capacitance of the sub-sequent stage, and that the overlap gate capacitance is small,then (Cl + C2), and therefore CC, will be directly proportionalto xlCO, where A is the active gate area of an individual transis-tor. This implies that the area of CC will scale with A and that

the ratio of capacitor to op amp areas will remain constantunder scaling.

Signal-to-Noise Ratio (S/N) –From (26), the signal to noiseratio for low-frequency analog applications can be expressed as

v@/m-S/N=~a

w to(38)

where the input signal amplitude V~gis assumed to scale withother voltages. This implies that the signal-to-noise ratio isdependent on device geometry.

Slew Rate SR –The slew rate normalized to the supply volt-age VDD can be used to provide an indication of large signalop amp response

s~ lD sat—= _vj~ v~&~ “

(39)

Power DensiW–The power density is a useful figure of meritin determining the maximum packing density of op amps perunit area.

ID,~t VDDpower density a

ZL “(40)

C. Optimum Scaling Law

The three scaling laws presented in the introduction wereapplied to the first-order scaling of the basic gain stages andthe op amp parameters. The results are listed in Table III.

Other than an increase in speed resulting from reduction ofCC, the majority of the analog performance parameters remain

WONGAND SALAMA: SCALING AND MOS ANALOG PERFORMANCE Ili

*?w) CE b~)

6u? Caw

14

12

10

08 64

14

12 -

b

10

08 -

06 ~06~06~1 2

A3 A A

(a) (b) (c)

Fig.1. Effect ofscalingon8’s. (a)CE. (b) QCV. (c)CV.

invariant to the application of CE scaling. The exception be-ing that the signal-to-noise ratio is severely degraded,

Although both nonconstant field scaling laws offer improve-

ments in speed and frequency response, CV scaling appears un-

acceptable for analog applications because it results in thelargest voltage gain degradation, the highest power dissipationper unit area without a significant gain in signal-to-noise per-formance. In addition (referririg to (27) and Table II), theparameter M increases with CV scaling, resulting in short chan-nel subthreshold effects becoming dominant at low values of L

QCV scaling offers an acceptable compromise, yielding ini-

proved speed and signal-to-noise ratio over the CE case, whileexhibiting a higher gain and lower power dissipation than CVscaling.

V. CASE STUDY

The scaling amilysis perf~rmed in the previous sections ne-glected ail second-order effects by assuming an ideal long chan-

nel MOSFET as the unscaled device. This allows simple first-order scaling factors to be computed without involving thenonlinear 8 terms. In this section, computer simulation involv-

ing the 8’s is performed using 7 pm channel length MOSFET’Sas the initial unscaled devices. The simulation focuses mainlyon the QCV law in light of the results of the previous section.These results are compared with the first-order scaling theoryof Tables 11 and HI. Scaling simulation is achieved by manu-ally scaling all voltages, dimensions, and doping concentrationsin accordance with the QCV law and then inputing them intoa simulation program which accommodates our model. A rep-resentative case study of such a simulation is presented in thefollowing paragraphs.

A.Effect of Scaling on the 8 Parameters

As an example, consider a typical n-channel device havingthe following initial unscaled characteristics: Z = 70 Mm, L =7 Mm, to = 800 A,xj = 1.2Vm,NA = 5 X 1015 cm-3, EP =1.1 X 104 V/cm, V“=5V, (VG - VT)= 1.5V, VB=O, R~=20$2. In this case the value of M is 0.788, implying that thedevice is still in its long channel mode of operation. FromTable II and (27), it is seen that M does not increase for CE orQCV scaling, but becomes greater than 1 for X>2 ‘in the caseof CV scaling. Using the unscaled device characteristics de-

fined above, the 8 values for 1= 1 are 81(1)= 1.163, 6,(1)=1.049, 83(1)=1.008,84(1)= 1.590,85 (1)=0 .855, and66(l]=0.785. The effect of scaling on the 8(1) parameters were com-puted and are plotted in Fig. l(a), (b), and (c) for CE, QCV,

and CV scalings. The graphs show that in most cases theti(X)/6(1) ratio remains very near unity (i.e., the 8‘s do notchange drastically with scaling). For 83 and 8 ~, this is truefor all three scaling laws, implying that parasitic resistance andvelocity saturation effects are still negligible in the scaling

range under consideration. Under worst case conditions, the8(h)/8(1 ) factors do not deviate by more than 20 percent fromunity for CE and QCV scaling and by more than 40 percent

for CV scaling. If CV scaling is restricted to k <2 (which asdiscussed above is required to prevent the onset of DIBL), the

maximum deviation is 20 percent. These results imply thatthe second-order effects described by the 8 terms can be ig-nored in establishing the general trend of scaling on device pa-rameters as was done in Sections III and IV. The error causedby ignoring the 6‘s may sometimes be significant but notdominant.

B.Gain Stage Simulation

The performance of the NMOS and CMOS gain stages, shown

in Fig. 2, were investigated using computer simulation. To pro-vide a fair comparison, the two stages were designed to haveidentical operating conditions and Z/L ratios. To achieve azero quiescent output voltage in the NMOS stage with quiescentinput voltage Vh = VDD/2 (typical operating conditions in again stage), one requires the ratio (Z/L )tiver: (Z/L)lo,d to be2.8. In the CMOS stage, the same current and aspect ratiosare maintained if Vbti is Set at -0.9 VDD.

Scaling was carried out starting with a set of unscaled de-vices with characteristics listed in Table IV. The simulatedgain for both gain stages as a function of the scaling factor X,is shown in Fig. 3. Also shown in the figure are the corre-sponding gains observed from first-order scaling theory (TableIV). The maximum discrepancy between simulation and first-order theory is of the order of 20 percent. The unscaled gainof the CMOS stage remains higher than that of the NMOS

stage. However, the gain in the NMOS case increases with in-creasing A while the opposite is true in the CMOS case. Thetwo gains approach each other at 1 cx 4. The relative increase


i’LOADPALOAD[VT, enh 0.2 Vn.

VT,dep ‘0.7 V.rr

VIN 0.5 VDD

VBM -0.9 vm

( Z/L )DRIVER 2.8

( Z/L) LOAD 1

VDD(A=I) 5V

(a) (b) (c)

Fig. 2. Gain stages. (a) CMOS. (b) NMOS with depletion load. (c)Specifications.

TABLE IVNMOS AND CMOS UNSCALEDDEVICECHARACTERISTICS

NMOS Stage CMOS Stage

Driver Load Driver Load

Type Enhancement Depletion n-channel p-channelVT~) 1 -3.5a 1 -laNdcm-3) 5 x 1015 5 x 10*5 5 x 1015 1.5 x 1015&;m2/V’. s) 600 600 600 300EC(V/cm) 2 x 104 2 x 104 2 x 104Xj(/.lnl) 1.2

2 x 1051.2 2.2 1.2

L(pm) 7 7 ‘1 7

aThreshold voltages adjusted by means of shallow implants.

‘V(d’)i--- I24 CMOS

22

20

18

16

14

12

1

— COMPUTER SlhlULATION

10 ---- ls’ ORDER THEORY

s~ A

Fig. 3. lnverter voltage gain as a function of L

in the gain of the NMOS stage can be attributed to the factthat gd~,~eP due to body effect increases at a slower rate (A1/4)than that due to channel length modulation (X3/4). However,this cannot be regarded as an advantage, since the latter mecha-nism present in the depletion NMOS would eventually over-take that due to body effect. From the above results, it ap-

pears that in the low k (X < 4) range, the CMOS stage can of-fer a higher gain than that of its NMOS equivalent. This resultis not specific to the particular set of device parameterschosen, but was found to be true in the majority of the casesinvestigated.

v~,/&

‘d

rWr4

‘VDD

Ml

M2

M3

M4

M5

M6

rw17

M8

M9

%D

[BIAS

cc

(a)

z(w)

100

100

100

100

400

400

100

200

100

L(Pm)

7

7

7

7

7

5

7

7

7

5V

2V

10pF

. .

Fig. 4. CMOS operational amplifier. (a) Circuit diagram. (b) Unscaledspecifications.

C. OpAmp Simulation

In light of the conclusion that, in general, scaled CMOS of-fers a gain advantage over scaled NMOS gain stages, a CMOSop amp was selected for simulation. The unscaled op amp andits imuortant lavout characteristics are shown in Fig. 4. The

WONGAND SALAMA: SCALINGAND MOS ANALOG PERFORMANCE 113

TABLE VSCALINGRESULTSOFOP AMP

Voltage Gain Av GBW (MHz) Power Dissipation (mW) Rout (kQ)

First-Order First-Order First-Order First-OrderSimulation Theory Simulation Theory Simulation Theory Simulation Theory

1 903 903 5 5 16.1 16.1 28 282 589 639 12.6 14.1 11.3 11.4 15.7 16.64 357 452 31.6 40 8.3 8.2 8.7 9.9

ScalingFactor ~-1/2 ~3/2 ~-1/2 ~3/4

circuit configuration is typical of op amps presently used intelecommunication applications. It consists of two gain stageswith a total gain of about 60 dB. A buffer stage is used inthe feedback compensation loop to eliminate an undesirable

zero at gm /CC [25]. The op amp has a useful feature asso-

ciated with the fact that all the transistor channel lengths are

nearly equal which guarantees equal Jj. for all the transistors,

even under scaled conditions.

Table V lists the results of the simulation as a function of A.Also shown in the table are the results obtained from first-order scaling theory. Agreement between the simulation andfirst-order theory appears reasonable, confirming the validityof using the first-order theory to estimate trends in amilogscaling.

VI. CONCLUSION

A theoretical analysis of the impact of scaling on analog com-

ponent and circuit performance has been presented. Amongthe three scaling laws considered, QCV appears to be the opti-

mum for analog scaling. Its application results in small area,high speed and moderate degradation in gain, power density,and signal-to-noise ratio. The selection of QCV is compatiblewith Chatterjee’s [3] choice of the same scaling law for digi-tal applications. Thus it appears feasible to scale both theanalog and digital portions of a circuit using the same scalinglaw.

A typical case study comparing the performance of NMOSand CMOS gain stages under moderate scaling conditions showsthat CMOS offers the optimum gain configuration for scaledanalog implementations. A comparison between computersimulation (of gain stages and a CMOS op amp) and first-orderscaling theory shows that second-order effects produce signifi-cant but nondominant errors in ewduating the performance ofanalog components under scaled conditions. Thus, first-ordertheory can be used to estimate scaling tendencies in analog

applications.

APPENDIX I

Considering (16), if one lets

EPKI~.

2(VD- V&#’

this equation becomes

AL = KI(VD- vD@)lt2

(Al)

{(1 +x’) ’/2 - x}. (A2)

If x is small, implying a moderate EP,(A2) can be simplified to

X2

()AL =KI(VD - VD,at)l/21 ‘X+7 . (A3)

Differentiating (A3) yields

8AL _ ~ KItiv~ ()

l-x+x;2 (VD - v~mt)l/2

+Kl(~D - bsat)112(x- l)—6VD

1=—

‘1 112 l-x+~+x}2 (VD - J’--sat)

1 KI=_{}l-x; .

2 (VD - v~wt)liz

Substituting (A3) and (A4) into

‘D, sat _6ALgds =

()

AL 2 tiVDL1-7

(A4)

(A5)

and neglecting all X2 terms yields

ID,satK~

‘ds = 2L(VD- VDWt)li2[1 - KI (VD- VDWt)112(1 - x)] 2

(A6)

which is (20). Note also that by neglecting X2, (A3) becomesequivalent to (18).

APPENDIX II

Consider the ideal current equation

(Bl)

When DIBL is present, the threshold voltage VT is a functionof VD~,accotding to Masuda [21], the dependence is

VT= v~o - q(vDJ - +) (B2)

where

(B3)

J+., q., and @ are constants dependent on the technology.

By substituting VT into (Bl) and differentiating with respect

114 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-I 8, NO. 1, FEBRUARY 1983

to VDs, one obtains

(B4)

Therefore, as L becomes smaller, this effect will become adominant factor in determining gd$.

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Stephen L. Wong was born in Singapore onJune 25, 1957. He received the B.A.SC.degreein Engineering Science fiqm the University ofToronto, Toronto, Ont., Canada, in 1980, wherehe is now finishing the requirements for theM.A.SC. degree in electrical engineering.

Since 1979 he has been concerned with themodeling and design of CM(X3analog circuits,particularly the effects of scaling for VLSIapplications.

C. Andre T. Salama (S’60-M’66) received theB.A.SC., M.A.SC., and Ph.D. degrees, all in elec-trical engineering, from the Univemity of BritishColumbia, Vancouver, B.C., in 1961, 1962, and1966, respectively.

From 1962 to 1963, he served as a ResearchAssistant W the University of California, Berke-ley. From 1966 to 1967 he was employed atBell Northern Research, Ottawa, Ont., Canada,as a member of the scientific staff working inthe area of integrated circuit design. Since

1967 he has been on the staff of the Debarment of Electrical Engineer-ing, University of Toronto, Toronto, ‘Ont., Canada, where he ;S cur-rently a Professor. For the 1975-1975 term, he was a Visiting Professorat the Katholieke Universiteit, Leuven, Belgium. He has served as aConsultant in the integrated circuits industry. His research interestsinclude the design and fabrication of semiconductor devices and inte-grated circuits.

Dr. Salama is a member of the Association of Professional Engineersof Ontario and the Electrochemical Society.

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