Scalable Regulated Three Phase Power Rectifier

ECE 481 Senior Design Final Presentation

Tyler Budzianowski & Tao Nguyen

Dec 7, 2004

Instructor: Dr. Jim FrenzelTechnical Advisors: Dr. Herb Hess and Dr. Richard WallSponsors: Dr. Herb Hess and Dr. Richard Wall

Presentation Outline

n Introduction to projectn Project objectives and specifications

n Product applicationsn Design approachn Implementation details and features including testing

methods and summary of results

n Summary of overall project resultsn Summary of expendituresn Scheduling and milestones?

Introductionn Purpose of the project

To upgrade an original design for a microcontroller based three phase rectifier as outlined in a paper authored by Dr. Richard Wall and Dr. Herb Hess

n Product Applications- Any electrical application where a variable DC output

voltage must be obtained from a three phase AC power line

- DC motor drive applications based on a three phase AC source

Project Objectives

n Upgrade zero-crossing detection methodn Replace the system with a modern and less

expensive microcontrollern Implementation of closed-loop control for

voltage/current regulationn Upgrade the SCR gate firing architecturen Installation of snubbing and protection for SCRsn Generation of a MATLAB-based PLL model

Design Approach:

nUpgrade hardware components of entire system and apply more accurate hardware implementation methods that are available

nReplace the original processor with a new microcontroller

nUse commercially available components where applicable

n Increase usability for the customer

System Schematic

Inputs

PIC uController

KEYPAD LCD

CMOS

InterfaceCKT

Gate Firing Circuit BoardFC0-AUX60

Outputs

OutputLoad

mov

mov

mov

mov

mov

mov

ZeroCrossingDetector

24 VcdPowerSupply

7805

LM317

Implementation of modern, less expensive microcontroller

n A Microchip PIC16C74B microcontroller has the necessary functionality to accurately control the three phase rectification process

n At approximately $10 per unit, the system is inexpensive and widely available

Test:

n Using a function generator, a 5 V square pulse signal into the PIC16C74B PORTA should produce 6 individual firing pulses on the output PORTD (RD0-RD5)

n These output pulses can be analyzed with an oscilloscope to ensure that they are out of phase by the desired angle (ex: 60°) and compared with the 60 Hz input signal.

n To test closed loop operation, the phase error of the initial value into the phase locked loop should be zero when compared to the feedback value of the output.

Results:

n Initially, the microcontroller did produce six individual firing outputs running in an open loop process based entirely on the 60 Hz input signal pulse

n The open loop process does not compensate for any zero crossing detection errors.

n The closed loop implementation was not successful

n The application and implementation of a user friendly input structure and visual display was not achieved.

Closed loop control for voltage/current regulation

n A digital phase locked loop implemented within the microcontroller software is intended to accurately predict the next possible zero crossing time to compensate for any physical errors/inaccuracies in the zero crossing detection circuit

n MATLAB was used to model this behavior

(to be discussed later)

Zero-Crossing detectorn Converts the input AC line signal to a digital representation with

minimal errorn A dynamic hysteresis comparator circuit was designed to provide

a more accurate alternative to the original optoisolator device configuration

Test:

n Must interface a three phase AC sinusoidal line and produce a digital 5V logic level output signal that matches the detected zero crossings of the sinusoidal input

n Must detect the positive rising edge zero crossing and negative falling edge zero crossing points with minimal error

n Forward schottky diode voltage should be approximately 1 volt max for an input of 30 mA, and 0.3 volt max for an input of 1 mA

Results:

• Successfully produces a 5V logic output based on approximate input signal zero crossings

• Forward schottky diode voltage is approximately 1V for a 30 mA input

• There is a slight offset error present with the actual zero crossing of the input line signal and the output square pulse signal

Input (3V) & Output (5V) vs. Time

-2.00E+00

-1.00E+00

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

-3.00E-02 -2.00E-02 -1.00E-02 0.00E+00 1.00E-02 2.00E-02 3.00E-02

Time (s)

Vo

lts

(V)

Input

Output

Input & Output of Zero Crossing Detector vs. Time (R1 = 170kohm)

-1.00E+00

-5.00E-01

0.00E+00

5.00E-01

1.00E+00

1.50E+00

2.00E+00

2.50E+00

-8.00E-

04

-7.00E-

04

-6.00E-

04

-5.00E-

04

-4.00E-

04

-3.00E-

04

-2.00E-

04

-1.00E-04 0.00E+00 1.00E-04 2.00E-04

Time (Second)

Vo

lt (

V)

Vout

Vin

Input and Output of the Zero Crossing Detector(Without input resistance [R1 =0])

-5.00E-02

0.00E+00

5.00E-02

1.00E-01

1.50E-01

2.00E-01

2.50E-01

8.32E-03 8.33E-03 8.33E-03 8.33E-03 8.33E-03 8.33E-03 8.33E-03

Time (Sec)

Vo

lt (V

)

Output

Input

SCR gate firing architecture

n Amplifies a lower voltage logic level signal to a level that will consistently trigger the gate of an SCR

2 Key Components:- A commercially available Enerpro FCO-AUX60 gate

firing circuit was selected as the primary gate firing driver

- A MOSFET based amplifier was designed to amplify the 5 V logic PIC output to a 12V logic signal that is usable by the FCO-AUX60 board

Enerpro FCO-AUX60

Auxiliary Firing Board Schematic:

MOSFET 5V/12V interface circuit

n Consists of 2 N-Channel (BS170) FETs and a single P-Channel (BS250P) FET configuration, 3 resistors, and an LM317 variable supply voltage regulator (12 V)

Single Stage Schematic

Test:

n A 5 V logic “high” input should produce an identical but 12V magnitude “high” output

n A 0V logic “low” input should produce a 0V logic “low” output

n Switching times should be under 20 nS (physical limitation of transistors)

Results:Input (5V) and Output (12V) vs. Time

-8.00E+00

-6.00E+00

-4.00E+00

-2.00E+00

0.00E+00

2.00E+00

4.00E+00

6.00E+00

8.00E+00

1.00E+01

1.20E+01

1.40E+01

-3.00E-02 -2.00E-02 -1.00E-02 0.00E+00 1.00E-02 2.00E-02 3.00E-02

Time (s)

Vo

lt (V

)

Output Signal

Input Signal

• Does successfully amplify 5 V square pulses to 12 V square pulses as well as maintaining 0 V signal when the input is 0 V

• There may be a possible switching conflict due to excess charge buildup across the gates of the parallel transistor configuration

Input & Output of Interface Ckt. vs. Time

-1.00E+01

-5.00E+00

0.00E+00

5.00E+00

1.00E+01

1.50E+01

2.00E+01

2.50E+01

3.00E+01

3.50E+01

-6.00E-07 -4.00E-07 -2.00E-07 0.00E+00 2.00E-07 4.00E-07 6.00E-07

Time (s)

Vol

tage

(V)

Input

Output

• Some signal noise and ringing can be noticed trailing off upon close inspection

SCR and snubbing/protection circuit

Consists of six of each:¨ Teccor D4020L silicon-controlled rectifier diodes (SCRs)¨ Snubbing resistors and capacitors (standard values)¨ BC Components 2322-594 metal oxide varistors (MOVs)

162

162

162

Phase B

0.068 u

162

SCR Gate Trigger Inputs

0.068 u

Phase C

0.068 u0.068 u

162Phase A

0.068 u

LOAD

0.068 u

162

Snubbing and protection

n Snubber circuit is designed to reduce and eliminate any harmful voltage/current transients that occur at SCR turn-on and turn-off points

n Metal-Oxide varistor devices are designed to “absorb” any fatal high voltage/current spikes before they can destroy the SCR devices.

Test:n The SCR should turn on only when a positive forward voltage is

applied to the SCR’s gate, regardless of the voltage magnitude across the SCR (from anode to cathode)

n The device should turn off when there is no voltage signal applied to the gate

n The snubber configuration should absorb any signal transients atSCR turn on and turn off times/points

n The MOV should absorb (destroy itself) at voltage levels above 230 VAC

0.068 u

V20.7Vdc

MOV

15.5162

V1

Variable AC

+

Vo

-

23mA

Single SCR Schematic:

Results:

n The SCR turns on when a forward voltage is applied to the gate (and a voltage is applied across the anode and cathode)

n The SCR turns off when the power supply to the gate is removed

n It is difficult to determine whether signal transients are present within the system to verify snubber functionality

n Because a high enough voltage spike could not be applied to the system, the full functionality of the MOV could not be confirmed

MATLAB based phase locked loop modeln DPLL consists of three functional units:

n Phase Detector (PD)n Digital Loop Filter (DLF)n Voltage Controlled Oscillator (VCO)

z

1

Unit Delay1

z

1

Unit Delay

OutputPhase

To Workspace

Product1

Product

C1

1Constant

C2

Input-Ph

Parameters in DPLLn C1 and C2 are coefficients/parameters of the

digital filtern C is a constant value that determines the center

frequency (fc) of the DPLLn Behavior of the output is dependent on these

parametersn Some values of C1 and C2 can cause the error

to oscillate.n Values of C1 and C2 can be found if sampling

freq. (fs) greater than the center freq. (fc)n According to final theorem, phase error is zero

DPLL Analysis

n C2 = 2*n*wn*T Where T=1/fsn C1=(C2)2/(4*n2) Where wn=2*pi*fnn 2C2-4 < C2; C1>0

H s( )2 n⋅ ωn⋅ S⋅ ωn( )2

+

S2

2 n⋅ ωn⋅ S⋅+ ωn( )2+

:=ω

H z( )Φo Z( )

Φi Z( )=

C2 Z 1( ). C1

Z 1( ) 2 C2 Z 1( ). C1

Eqt (1)

Eqt (2)

Figure 1. Stable region of the output digital filter

Test:

n Filter output must be stabilized n Locking time duration must be small (< 0.5 Second)n Frequency and phase of input signal and output signal

must be lockedn Phase error must be small (approx. 0)

Results:

For n=17, Fs=8000Hz and Fc= 69Hz, c2 = 1.8425 c1 = 0.0029. Oscilation, Phase_err=0.04, Locking time = 0.4 Second

When n=4, Fs=8000Hz and Fc=69Hz c2 = 0.4335 c1 = 0.0029 Oscillation, Phase_err=0.08, Locking time = 0.12 Second

n Results

¨ Filter output is stable and oscillating

¨ Locking time is very small and dependent on the value of n

¨ Frequency of input and output signal is locked

¨ Small phase error is detected

¨ If n increases, locking time increases, and error decreases, just as error increases and locking time decreases if n decreases

Summary of project results

Designed and working:- MOSFET interface circuit- Single SCR circuit configuration- MATLAB simulation model- Zero crossing detector

Designed but not working:- Microcontroller system utilizing closed loop

control- Entire system as a whole (6 firing SCRs)

Project Budget Summary

$541.74Total Cost

$0.99$0.991 7805 Voltage Regulator

$1.10$1.101 Comparator circuit

$2.64$0.446 Schottky Diodes

$3.96$0.3312 BS170 N MOSFETs

$4.56$0.4610 MOVs

$10.00Approx.Resistors & Capacitors

$10.80$1.8010 x 4020L SCRs

$11.52$0.9612 BS250P P MOSFETs

$12.73$12.731 PIC16C74 processor

$14.91$14.911 LCD

$14.95$14.951 Key Pad

$14.95$14.951 12Vdc Power Supply

$41.80$41.801 Omron 24 Vdc Supply

$104.38$104.381 Demo Board for PIC

$292.45$292.451 Gate Firing Circuit Board

CostPrice/unitComponents

Schedule and Milestones

n Project Status Report 9/21n Lifecycle Report 10/5n Reliability Analysis Report 10/19n Test Plan Report 11/18n Final Demonstration 12/1n Final Presentation 12/7n Final Report 12/10

QUESTIONS and COMMENTS

Scalable Regulated Three Phase Power Rectifier

ECE480 Senior Design Final Presentation

Tyler Budzianowski & Tao Nguyen

Dec 7, 2004

Instructor: Dr. Jim FrenzelTechnical Advisors: Dr. Hess and Dr. WallSponsors: Dr. Hess and Dr. Wall