NCP43080 - Synchronous Rectifier ControllerSynchronous Rectifier Controller The NCP43080 is a...

© Semiconductor Components Industries, LLC, 2016

February, 2017 − Rev. 01 Publication Order Number:

NCP43080/D

NCP43080

Synchronous RectifierController

The NCP43080 is a synchronous rectifier controller for switchmode power supplies. The controller enables high efficiency designsfor flyback and quasi resonant flyback topologies.

Externally adjustable minimum off−time and on−time blankingperiods provides flexibility to drive various MOSFET package typesand PCB layout. A reliable and noise less operation of the SR system isinsured due to the Self Synchronization feature. The NCP43080 alsoutilizes Kelvin connection of the driver to the MOSFET to achieve highefficiency operation at full load and utilizes a light load detectionarchitecture to achieve high efficiency at light load.

The precise turn−off threshold, extremely low turn−off delay timeand high sink current capability of the driver allow the maximumsynchronous rectification MOSFET conduction time. The highaccuracy driver and 5 V gate clamp make it ideally suited for directlydriving GaN devices.

Features• Self−Contained Control of Synchronous Rectifier in CCM, DCM and

QR for Flyback, Forward or LLC Applications• Precise True Secondary Zero Current Detection

• Rugged Current Sense Pin (up to 150 V)

• Adjustable Minimum ON−Time

• Adjustable Minimum OFF-Time with Ringing Detection

• Adjustable Maximum ON−Time for CCM Controlling of PrimaryQR Controller

• Improved Robust Self Synchronization Capability

• 8 A / 4 A Peak Current Sink / Source Drive Capability

• Operating Voltage Range up to VCC = 35 V

• Automatic Light−load & Disable Mode

• Adaptive Gate Drive Clamp

• GaN Transistor Driving Capability (options A and C)

• Low Startup and Disable Current Consumption

• Maximum Operation Frequency up to 1 MHz

• SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages

• These are Pb−Free Devices

Typical Applications• Notebook Adapters

• High Power Density AC/DC Power Supplies (Cell Phone Chargers)

• LCD TVs

• All SMPS with High Efficiency Requirements

SOIC−8D SUFFIXCASE 751

MARKINGDIAGRAMS

43080x = Specific Device Codex = A, B, C, D or Q

Fx = Specific Device Codex = A or D

A = Assembly LocationL = Wafer LotY = YearW = Work WeekM = Date Code� = Pb−Free Package

1

8

43080xALYW �

�

1

8

(Note: Microdot may be in either location)

43080xALYW�

�

1

DFN8MN SUFFIX

CASE 488AF

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See detailed ordering and shipping information on page 33 ofthis data sheet.

ORDERING INFORMATION

FxM�

�

1

WDFN8MT SUFFIX

CASE 511AT

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NCP43080

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Figure 1. Typical Application Example − LLC Converter with Optional LLD

D1

OK1

RTN

MIN

_TO

N

MIN

_TO

FF

MIN

_TO

N

MIN

_TO

FF

Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter with optional LLD

+

+

+

Vbulk

FLYBACK

CONTROL

CIRCUITRY

+Vout

GND

OK1

R1

R2

R8

R4

C1C2

C3

C4

C5

D3

D4

D5

TR1

M1

M2

R5R6

C6

D6

R7

R3

C7

VCC

DRV

FB CS


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Figure 3. Typical Application Example − Primary Side Flyback Converter with optional LLD

+

++

Vbulk

FLYBACK

SIDE

CONTROLLER

+Vout

GND

R1

R2

R7

R6

C1C2

C3

C7

C10

D3

D4

TR1

M1

M2

R9R10

C8

D6

R11

PRIMARY

C4

C5

C6

R3

R4

R5

C9

R8

VCC

DRV

COMP CS

ZCD

Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under HeavyLoads utilizing MAX−TON

+

+

+Vbulk

QRCONTROLCIRCUITRY

+Vout

GND

OK1

R5

R6

R7

R9R10

C1

C4

C7

D3

D4

D5

TR1

TR2

M1

M3

NCP43080Q

R11

R12

R13

D6

D7

D1

R1

R14

R15

R16

M2

D8

R17

R18

R19

C2C8 C9

C5

C6

C3

VCC

DRV

FB CSZCD


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PIN FUNCTION DESCRIPTION

ver. A, B, C, D ver. Q Pin Name Description

1 1 VCC Supply voltage pin

2 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground.

3 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground.

4 4 LLD This input modulates the driver clamp level and/or turns the driver off during light loadconditions.

5 − NC Leave this pin opened or tie it to ground.

6 6 CS Current sense pin detects if the current flows through the SR MOSFET and/or its bodydiode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin candecrease the turn off threshold if needed.

7 7 GND Ground connection for the SR MOSFET driver, VCC decoupling capacitor and for mini-mum on and off time adjust resistors and LLD input.GND pin should be wired directly to the SR MOSFET source terminal/soldering pointusing Kelvin connection. DFN8 exposed flag should be connected to GND

8 8 DRV Driver output for the SR MOSFET

− 5 MAX_TON Adjust the maximum on time period by connecting resistor to ground.

Figure 5. Internal Circuit Architecture − NCP43080A, B, C, D

Minimum ON timegenerator

MIN_TON

CSdetection

100μA

CS

MIN_TOFF

NC

CS_ON

CS_OFF

DRV

VCC

GND

VCC managmentUVLO

DRV OutDRIVER

VDD

VDD

CS_RESET

LLDDisable detection

&V DRV clampmodulation

V_DRVcontrol

ADJ ELAPSED

EN

Minimum OFFtime generator

ADJ

RESET

ELAPSED

Control logic

EN

DISABLE

DISABLE


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Minimum ON timegenerator

MIN_TON

CSdetection

100�A

CS

MIN_TOFF

MAX_TON

CS_ON

CS_OFF

DRV

VCC

GND

VCC managmentUVLO

DRV OutDRIVER

VDD

VDD

CS_RESET

LLDDisable detection

&V DRV clampmodulation

V_DRVcontrol

ADJ

ELAPSED

EN

Minimum OFFtime generator

ADJ

RESET

ELAPSED

Control logic

EN

DISABLE

DISABLE

ELAPSED

Maximum ON timegenerator

EN

ADJ

Figure 6. Internal Circuit Architecture − NCP43080Q (CCM QR) with MAX_TON


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ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VCC −0.3 to 37.0 V

MIN_TON, MIN_TOFF, MAX_TON, LLD Input Voltage VMIN_TON,VMIN_TOFF,

VMAX_TON, VLLD

−0.3 to VCC V

Driver Output Voltage VDRV −0.3 to 17.0 V

Current Sense Input Voltage VCS −4 to 150 V

Current Sense Dynamic Input Voltage (tPW = 200 ns) VCS_DYN −10 to 150 V

MIN_TON, MIN_TOFF, MAX_TON, LLD Input Current IMIN_TON, IMIN_TOFF,IMAX_TON, ILLD

−10 to 10 mA

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 R�J−A_SOIC8 160 °C/W

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, DFN8 R�J−A_DFN8 80 °C/W

Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8 R�J−A_WDFN8 160 °C/W

Maximum Junction Temperature TJMAX 150 °C

Storage Temperature TSTG −60 to 150 °C

ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E ESDHBM 2000 V

ESD Capability, Human Body Model, Pin 6, per JESD22−A114E ESDHBM 1000 V

ESD Capability, Machine Model, per JESD22−A115−A ESDMM 200 V

ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F ESDCDM 750 V

ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F ESDCDM 250 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Maximum Operating Input Voltage VCC 35 V

Operating Junction Temperature TJ −40 125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 k�; VLLD = 0 V; VCS = −1 to +4 V; fCS = 100 kHz, DCCS =50%, unless otherwise noted. Typical values are at TJ = +25°C

Parameter Test Conditions Symbol Min Typ Max Unit

SUPPLY SECTION

VCC UVLO (ver. B & C) VCC rising VCCON 8.3 8.8 9.3 V

VCC falling VCCOFF 7.3 7.8 8.3

VCC UVLO Hysteresis (ver. B & C) VCCHYS 1.0 V

VCC UVLO (ver. A, D & Q) VCC rising VCCON 4.20 4.45 4.80 V

VCC falling VCCOFF 3.70 3.95 4.20

VCC UVLO Hysteresis (ver. A, D & Q)

VCCHYS 0.5 V

Start−up Delay VCC rising from 0 to VCCON + 1 V @ tr = 10 �s tSTART_DEL 75 125 �s


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Parameter UnitMaxTypMinSymbolTest Conditions

SUPPLY SECTION

Current Consumption,RMIN_TON = RMIN_TOFF = 0 k�

CDRV = 0 nF, fSW = 500 kHz A, C ICC 3.0 4.0 5.6 mA

B, D, Q 3.5 4.5 6.0

CDRV = 1 nF, fSW = 500 kHz A, C 4.5 6.0 7.5

B, D, Q 7.7 9.0 10.7

CDRV = 10 nF, fSW = 500 kHz A, C 20 25 30

B, D, Q 40 50 60

Current Consumption No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF= 0 k�

ICC 1.0 2.0 2.5 mA

Current Consumption below UVLO No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V ICC_UVLO 75 125 �A

Current Consumption in DisableMode

VLLD = VCC − 0.1 V, VCS = 0 V ICC_DIS 30 55 75 �A

DRIVER OUTPUT

Output Voltage Rise−Time CDRV = 10 nF, 10% to 90% VDRVMAX tr 40 55 ns

Output Voltage Fall−Time CDRV = 10 nF, 90% to 10% VDRVMAX tf 20 35 ns

Driver Source Resistance RDRV_SOURCE 1.2 �

Driver Sink Resistance RDRV_SINK 0.5 �

Output Peak Source Current IDRV_SOURCE 4 A

Output Peak Sink Current IDRV_SINK 8 A

Maximum Driver Output Voltage VCC = 35 V, CDRV > 1 nF, VLLD = 0 V, (ver. B, D and Q)

VDRVMAX 9.0 9.5 10.5 V

VCC = 35 V, CDRV > 1 nF, VLLD = 0 V, (ver. A, C) 4.3 4.7 5.5

Minimum Driver Output Voltage VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. B) VDRVMIN 7.2 7.8 8.5 V

VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. C) 4.2 4.7 5.3

VCC = VCCOFF + 200 mV, VLLD = 0 V 3.6 4.0 4.4

Minimum Driver Output Voltage VLLD = VCC − VLLDREC V VDRVLLDMIN 0.0 0.4 1.2 V

CS INPUT

Total Propagation Delay From CSto DRV Output On

VCS goes down from 4 to −1 V, tf_CS = 5 ns tPD_ON 35 60 ns

Total Propagation Delay From CSto DRV Output Off

VCS goes up from −1 to 4 V, tr_CS = 5 ns tPD_OFF 12 23 ns

CS Bias Current VCS = −20 mV ICS −105 −100 −95 �A

Turn On CS Threshold Voltage VTH_CS_ON −120 −75 −40 mV

Turn Off CS Threshold Voltage Guaranteed by Design VTH_CS_OFF −1 0 mV

Turn Off Timer Reset ThresholdVoltage

VTH_CS_RESET 0.4 0.5 0.6 V

CS Leakage Current VCS = 150 V ICS_LEAKAGE 0.4 �A

MINIMUM tON and tOFF ADJUST

Minimum tON time RMIN_TON = 0 � tON_MIN 25 56 75 ns

Minimum tOFF time RMIN_TOFF = 0 � tOFF_MIN 160 245 290 ns

Minimum tON time RMIN_TON = 10 k� tON_MIN 0.92 1.00 1.08 �s

Minimum tOFF time RMIN_TOFF = 10 k� tOFF_MIN 0.92 1.00 1.08 �s

Minimum tON time RMIN_TON = 50 k� tON_MIN 4.62 5.00 5.38 �s

Minimum tOFF time RMIN_TOFF = 50 k� tOFF_MIN 4.62 5.00 5.38 �s


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Parameter UnitMaxTypMinSymbolTest Conditions

MAXIMUM tON ADJUST

Maximum tON Time VMAX_TON = 3 V tON_MAX 4.3 4.8 5.3 �s

Maximum tON Time VMAX_TON = 0.3 V tON_MAX 41 48 55 �s

Maximum tON Output Current VMAX_TON = 0.3 V, VCS = 0 V IMAX_TON −105 −100 −95 �A

LLD INPUT

Disable Threshold VLLD_DIS = VCC − VLLD VLLD_DIS 0.8 0.9 1.0 V

Recovery Threshold VLLD_REC = VCC − VLLD VLLD_REC 0.9 1.0 1.1 V

Disable Hysteresis VLLD_DISH 0.1 V

Disable Time Hysteresis Disable to Normal, Normal to Disable tLLD_DISH 45 �s

Disable Recovery Time tLLD_DIS_REC 6.0 12.5 16.0 �s

Low Pass Filter Frequency fLPLLD 6 10 13 kHz

Driver Voltage Clamp Threshold VDRV = VDRVMAX, VLLDMAX = VCC − VLLD VLLDMAX 2.0 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.

TYPICAL CHARACTERISTICS

Figure 7. VCCON and VCCOFF Levels,ver. A, D, Q

Figure 8. VCCON and VCCOFF Levels,ver. B, C

TJ (°C) TJ (°C)100806040200−20−40

3.7

3.8

3.9

4.1

4.2

4.4

4.6

4.7

100806040200−20−407.3

7.5

7.7

8.1

8.3

8.7

8.9

9.3

VC

C (

V)

VC

C (

V)

120

4.0

4.3

4.5 VCCON

VCCOFF

VCCON

VCCOFF

120

7.9

8.5

9.1


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Figure 9. Current Consumption, CDRV = 0 nF,fCS = 500 kHz, ver. D

Figure 10. Current Consumption, VCC =VCCOFF − 0.1 V, VCS = 0 V, ver. D

VCC (V) TJ (°C)

3025 35201510500

1

2

3

4

5

6

1201006040200−20−400

20

40

60

80

100

120

Figure 11. Current Consumption, VCC = 12 V,VCS = −1 to 4 V, fCS = 500 kHz, ver. A

Figure 12. Current Consumption, VCC = 12 V,VCS = −1 to 4 V, fCS = 500 kHz, ver. D

TJ (°C) TJ (°C)

100806040200−20−400

5

10

15

20

25

30

100806040200−20−400

10

20

30

40

50

60

Figure 13. Current Consumption in Disable,VCC = 12 V, VCS = 0 V, VLLD = VCC − 0.1 V

TJ (°C)

100806040200−20−4040

45

50

55

60

65

70

I CC

(m

A)

I CC

_UV

LO (�A

)

I CC

(m

A)

I CC

(m

A)

I CC

_DIS

(�A

)

TJ = 85°CTJ = 55°CTJ = 125°CTJ = 25°C

TJ = 0°C

TJ = −20°C

TJ = −40°C

80

120

CDRV = 0 nF

CDRV = 1 nF

CDRV = 10 nF

CDRV = 0 nF

CDRV = 1 nF

CDRV = 10 nF

120

120


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Figure 14. CS Current, VCS = −20 mV Figure 15. CS Current, VCC = 12 V

TJ (°C) VCS (V)

100806040200−20−40−110

−106

−104

−100

−98

−96

−94

−90

0.80.60.20−0.2−0.4−0.8−1.0−1.4

−1.2

−1.0

−0.8

−0.6

−0.4

−0.2

0

Figure 16. Supply Current vs. CS Voltage,VCC = 12 V

Figure 17. CS Turn−on Threshold

VCS (V) TJ (°C)

3210−1−2−3−40

0.5

1.0

1.5

2.0

2.5

3.0

100806040200−20−40−150

−130

−110

−90

−70

−50

−30

Figure 18. CS Turn−off Threshold Figure 19. CS Reset Threshold

TJ (°C) TJ (°C)

100806040200−20−40−2.0

−1.5

−1.0

−0.5

0

0.5

1.0

0.40

0.45

0.50

0.55

0.60

I CS (�A

)

I CS (

mA

)

I CC

(m

A)

VT

H_C

S_O

N (

mV

)

VT

H_C

S_O

FF (

mV

)

VT

H_C

S_R

ES

ET (

V)

120

−92

−102

−108

−0.6 0.4 1.0

4

TJ = 125°CTJ = 85°CTJ = 55°CTJ = 25°CTJ = 0°CTJ = −20°CTJ = −40°C

TJ = 125°CTJ = 85°CTJ = 55°CTJ = 25°CTJ = 0°CTJ = −20°CTJ = −40°C

120

120 100806040200−20−40 120


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Figure 20. CS Reset Threshold Figure 21. CS Leakage, VCS = 150 V

VCC (V)

302520 351510500.30

0.35

0.45

0.50

0.60

0.65

0.70

0.80

Figure 22. Propagation Delay from CS to DRVOutput On

Figure 23. Propagation Delay from CS to DRVOutput Off

TJ (°C) TJ (°C)

100806040200−20−4020

25

30

35

40

50

55

60

100806040200−20−404

6

10

12

16

18

22

24

VT

H_C

S_R

ES

ET (

V)

t PD

_ON

(ns

)

t PD

_OF

F (

ns)

0.40

0.55

0.75

120

45

120

8

14

20

TJ (°C)

100 1206040200−20−400

20

60

80

120

140

180

200

I CS

_LE

AK

AG

E (

nA)

80

40

100

160

Figure 24. Minimum On−time RMIN_TON = 0 � Figure 25. Minimum On−time RMIN_TON = 10 k�

TJ (°C) TJ (°C)

100806040200−20−4035

40

45

50

55

60

70

75

100806040200−20−400.92

0.94

0.96

0.98

1.00

1.04

1.06

1.08

t MIN

_TO

N (

ns)

t MIN

_TO

N (�s)

120

65

120

1.02


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Figure 26. Minimum On−time RMIN_TON = 50 k� Figure 27. Minimum Off−time RMIN_TOFF = 0 �

TJ (°C) TJ (°C)

100806040200−20−404.6

4.7

4.8

4.9

5.0

5.2

5.3

5.4

100806040200−20−40190

200

220

230

240

260

270

290

Figure 28. Minimum Off−time RMIN_TOFF =10 k�

Figure 29. Minimum Off−time RMIN_TOFF =50 k�

TJ (°C) TJ (°C)

100806040200−20−400.92

0.94

0.96

1.00

1.02

1.04

1.06

1.08

100806040200−20−404.6

4.7

4.8

4.9

5.0

5.1

5.3

5.4

Figure 30. Minimum On−time RMIN_TON = 10 k� Figure 31. Minimum Off−time RMIN_TOFF =10 k�

VCC (V) VCC (V)

302520 351510500.92

0.94

0.96

0.98

1.00

1.02

1.03

1.04

35302520151050092

0.94

0.96

0.98

1.00

1.02

1.06

1.08

t MIN

_TO

N (�s)

t MIN

_TO

FF (

ns)

t MIN

_TO

FF (�s)

t MIN

_TO

FF (�s)

t MIN

_TO

N (�s)

t MIN

_TO

FF (�s)

120

5.1

120

210

250

280

120

0.98

120

5.2

1.01

1.04


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Figure 32. Driver and Output Voltage, ver. B, Dand Q

Figure 33. Driver Output Voltage, ver. A and C

TJ (°C) TJ (°C)

100806040200−20−409.0

9.2

9.4

9.6

9.8

10.0

10.2

10.4

100806040200−20−404.3

4.5

4.7

4.9

5.1

5.3

5.5

Figure 34. Maximum On−time, ver. Q Figure 35. Maximum On−time, VMAX_TON = 3 V,ver. Q

VMAX_TON (V) TJ (°C)

3.02.52.01.51.00.5005

15

20

25

35

45

50

100806040200−20−404.3

4.4

4.6

4.7

4.8

5.0

5.1

5.3

Figure 36. Maximum On−time, VMAX_TON =0.3 V, ver. Q

TJ (°C)

100806040200−20−4041

43

45

47

49

51

53

55

VD

RV (

V)

VD

RV (

V)

t MA

X_T

ON

(�s)

t MA

X_T

ON

(�s)

t MA

X_T

ON

(�s)

120

VCC = 12 V, CDRV = 0 nFVCC = 12 V, CDRV = 1 nFVCC = 12 V, CDRV = 10 nFVCC = 35 V, CDRV = 0 nFVCC = 35 V, CDRV = 1 nFVCC = 35 V, CDRV = 10 nF

VCC = 12 V, CDRV = 0 nFVCC = 12 V, CDRV = 1 nFVCC = 12 V, CDRV = 10 nFVCC = 35 V, CDRV = 0 nFVCC = 35 V, CDRV = 1 nFVCC = 35 V, CDRV = 10 nF

120

TJ = 125°CTJ = 85°CTJ = 55°CTJ = 25°C

TJ = 0°CTJ = −20°CTJ = −40°C

10

30

40

120

4.5

4.9

5.2

120


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APPLICATION INFORMATION

General descriptionThe NCP43080 is designed to operate either as a

standalone IC or as a companion IC to a primary sidecontroller to help achieve efficient synchronousrectification in switch mode power supplies. This controllerfeatures a high current gate driver along with high−speedlogic circuitry to provide appropriately timed drive signalsto a synchronous rectification MOSFET. With its novelarchitecture, the NCP43080 has enough versatility to keepthe synchronous rectification system efficient under anyoperating mode.

The NCP43080 works from an available voltage withrange from 4 V (A, D & Q options) or 8 V (B & C options)to 35 V (typical). The wide VCC range allows directconnection to the SMPS output voltage of most adapterssuch as notebooks, cell phone chargers and LCD TVadapters.

Precise turn-off threshold of the current sense comparatortogether with an accurate offset current source allows theuser to adjust for any required turn-off current threshold ofthe SR MOSFET switch using a single resistor. Comparedto other SR controllers that provide turn-off thresholds in therange of −10 mV to −5 mV, the NCP43080 offers a turn-offthreshold of 0 mV. When using a low RDS(on) SR (1 m�)MOSFET our competition, with a −10 mV turn off, will turnoff with 10 A still flowing through the SR FET, while our0 mV turn off turns off the FET at 0 A; significantlyreducing the turn-off current threshold and improvingefficiency. Many of the competitor parts maintain a drainsource voltage across the MOSFET causing the SRMOSFET to operate in the linear region to reduce turn−offtime. Thanks to the 8 A sink current of the NCP43080significantly reduces turn off time allowing for a minimaldrain source voltage to be utilized and efficiencymaximized.

To overcome false triggering issues after turn-on andturn−off events, the NCP43080 provides adjustableminimum on-time and off-time blanking periods. Blankingtimes can be adjusted independently of IC VCC usingexternal resistors connected to GND. If needed, blankingperiods can be modulated using additional components.

An extremely fast turn−off comparator, implemented onthe current sense pin, allows for NCP43080 implementationin CCM applications without any additional components orexternal triggering.

An output driver features capability to keep SR transistorclosed even when there is no supply voltage for NCP43080.SR transistor drain voltage goes up and down during SMPSoperation and this is transferred through drain gatecapacitance to gate and may turn on transistor. NCP43080uses this pulsing voltage at SR transistor gate (DRV pin) anduses it internally to provide enough supply to activateinternal driver sink transistor. DRV voltage is pulled low(not to zero) thanks to this feature and eliminate the risk ofturned on SR transistor before enough VCC is applied toNCP43080.

Some IC versions include a MAX_TON circuit that helpsa quasi resonant (QR) controller to work in CCM modewhen a heavy load is present like in the example of aprinter’s motor starting up.

Finally, the NCP43080 features a special pin (LLD) thatcan be used to reduce gate driver voltage clamp accordingto application load conditions. This feature helps to reduceissues with transition from disabled driver to full driveroutput voltage and back. Disable state can be also activatedthrough this pin to decrease power consumption in no loadconditions. If the LLD feature is not wanted then the LLDpin can be tied to GND.

Current Sense InputFigure 37 shows the internal connection of the CS

circuitry on the current sense input. When the voltage on thesecondary winding of the SMPS reverses, the body diode ofM1 starts to conduct current and the voltage of M1’s draindrops approximately to −1 V. The CS pin sources current of100 �A that creates a voltage drop on the RSHIFT_CS resistor(resistor is optional, we recommend shorting this resistor).Once the voltage on the CS pin is lower than VTH_CS_ONthreshold, M1 is turned−on. Because of parasiticimpedances, significant ringing can occur in the application.To overcome false sudden turn−off due to mentionedringing, the minimum conduction time of the SR MOSFETis activated. Minimum conduction time can be adjustedusing the RMIN_TON resistor.


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Figure 37. Current Sensing Circuitry Functionality

The SR MOSFET is turned-off as soon as the voltage onthe CS pin is higher than VTH_CS_OFF (typically −0.5 mVminus any voltage dropped on the optional RSHIFT_CS). Forthe same ringing reason, a minimum off-time timer isasserted once the VCS goes above VTH_CS_RESET. Theminimum off-time can be externally adjusted usingRMIN_TOFF resistor. The minimum off−time generator canbe re−triggered by MIN_TOFF reset comparator if somespurious ringing occurs on the CS input after SR MOSFETturn−off event. This feature significantly simplifies SRsystem implementation in flyback converters.

In an LLC converter the SR MOSFET M1 channelconducts while secondary side current is decreasing (refer to

Figure 38). Therefore the turn−off current depends onMOSFET RDSON. The −0.5 mV threshold provides anoptimum switching period usage while keeping enough timemargin for the gate turn-off. The RSHIFT_CS resistorprovides the designer with the possibility to modify(increase) the actual turn−on and turn−off secondary currentthresholds. To ensure proper switching, the min_tOFF timeris reset, when the VDS of the MOSFET rings and falls downpast the VTH_CS_RESET. The minimum off−time needs toexpire before another drive pulse can be initiated. Minimumoff−time timer is started again when VDS rises aboveVTH_CS_RESET.


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VDS = VCS

VTH_CS_RESET – (RSHIFT_CS*ICS)

VTH_CS_OFF– (RSHIFT_CS*ICS)

VTH_CS_ON– (RSHIFT_CS*ICS)

VDRV

Min ON−time

t

Min OFF−time

Min tOFF timer wasstopped here because

of VCS<VTH_CS_RESET

tMIN_TON

tMIN_TOFF

ISEC

The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors

Turn−on delay Turn −off delay

Figure 38. CS Input Comparators Thresholds and Blanking Periods Timing in LLC

VDS = VCS

VTH_CS_RESET – (RSHIFT_CS*ICS)

VTH_CS_OFF– (RSHIFT_CS*ICS)

VTH_CS_ON– (RSHIFT_CS*ICS)

VDRV

Min ON−time

t

Min OFF−time

tMIN_TON

tMIN_TOFF

ISEC

The tMIN_TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors

Turn−on delay Turn−off delay

Min tOFF timer wasstopped here because

of VCS<VTH_CS_RESET

Figure 39. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback


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If no RSHIFT_CS resistor is used, the turn-on, turn-off andVTH_CS_RESET thresholds are fully given by the CS inputspecification (please refer to electrical characteristics table).The CS pin offset current causes a voltage drop that is equalto:

VRSHIFT_CS � RSHIFT_CS * ICS (eq. 1)

Final turn−on and turn off thresholds can be then calculatedas:

VCS_TURN_ON � VTH_CS_ON � �RSHIFT_CS * ICS� (eq. 2)

VCS_TURN_OFF � VTH_CS_OFF � �RSHIFT_CS * ICS� (eq. 3)

VCS_RESET � VTH_CS_RESET � �RSHIFT_CS * ICS� (eq. 4)

Note that RSHIFT_CS impact on turn-on and VTH_CS_RESETthresholds is less critical than its effect on the turn−offthreshold.

It should be noted that when using a SR MOSFET in athrough hole package the parasitic inductance of theMOSFET package leads (refer to Figure 40) causes aturn−off current threshold increase. The current that flowsthrough the SR MOSFET experiences a high �i(t)/�t thatinduces an error voltage on the SR MOSFET leads due totheir parasitic inductance. This error voltage is proportionalto the derivative of the SR MOSFET current; and shifts theCS input voltage to zero when significant current still flowsthrough the MOSFET channel. As a result, the SR MOSFETis turned−off prematurely and the efficiency of the SMPS isnot optimized − refer to Figure 41 for a better understanding.

Figure 40. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application


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Figure 41. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 PackageWith Long Leads − SR MOSFET channel Conduction Time is Reduced

Note that the efficiency impact caused by the error voltagedue to the parasitic inductance increases with lowerMOSFETs RDS(on) and/or higher operating frequency.

It is thus beneficial to minimize SR MOSFET packageleads length in order to maximize application efficiency. Theoptimum solution for applications with high secondary

current �i/�t and high operating frequency is to uselead−less SR MOSFET i.e. SR MOSFET in SMT package.The parasitic inductance of a SMT package is negligiblecausing insignificant CS turn−off threshold shift and thusminimum impact to efficiency (refer to Figure 42).


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Figure 42. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package withMinimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized

It can be deduced from the above paragraphs on theinduced error voltage and parameter tables that turn−offthreshold precision is quite critical. If we consider a SRMOSFET with RDS(on) of 1 m�, the 1 mV error voltage onthe CS pin results in a 1 A turn-off current thresholddifference; thus the PCB layout is very critical whenimplementing the SR system. Note that the CS turn-offcomparator is referred to the GND pin. Any parasiticimpedance (resistive or inductive − even on the magnitudeof m� and nH values) can cause a high error voltage that isthen evaluated by the CS comparator. Ideally the CSturn−off comparator should detect voltage that is caused bysecondary current directly on the SR MOSFET channelresistance. In reality there will be small parasitic impedanceon the CS path due to the bonding wires, leads and soldering.To assure the best efficiency results, a Kelvin connection of

the SR controller to the power circuitry should beimplemented. The GND pin should be connected to the SRMOSFET source soldering point and current sense pinshould be connected to the SR MOSFET drain solderingpoint − refer to Figure 40. Using a Kelvin connection willavoid any impact of PCB layout parasitic elements on the SRcontroller functionality; SR MOSFET parasitic elementswill still play a role in attaining an error voltage. Figure 44and Figure 43 show examples of SR system layouts usingMOSFETs in TO220 and SMT packages. It is evident thatthe MOSFET leads should be as short as possible tominimize parasitic inductances when using packages withleads (like TO220). Figure 43 shows how to layout designwith two SR MOSFETs in parallel. It has to be noted that itis not easy task and designer has to paid lot of attention to dosymmetric Kelvin connection.

Figure 43. Recommended Layout When Using SRMOSFET in SMT Package (2x SO8 FL)

Figure 44. Recommended Layout When Using SRMOSFET in TO220 Package


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Figure 45. NCP43080 Operation after Start−Up Event

VDS = VCS

VTH_CS_RESET

VTH_CS_OFF

VTH_CS_ON

VCCON

Min OFF− time

VDRV

VCC

Min ON−time

t MIN_TOFF t MIN_TOFF

t MIN_TON

Not completetMIN_TOFF −> ICis not activated

Completet MIN_TOFF

activates IC

tMIN_TOFF is stoppeddue to VDS drops

below VTH_CS_RESET

t1t2

t3t4

t5t6

t7t8

t9t10

t11t12

t13t14

t15

Self SynchronizationSelf synchronization feature during start−up can be seen

at Figure 45. Figure 45 shows how the minimum off−timetimer is reset when CS voltage is oscillating throughVTH_CS_RESET level. The NCP43080 starts operation attime t1 (time t1 can be seen as a wake−up event from thedisable mode through LLD pin). Internal logic waits for onecomplete minimum off−time period to expire before theNCP43080 can activate the driver after a start−up orwake−up event. The minimum off−time timer starts to runat time t1, because VCS is higher than VTH_CS_RESET. Thetimer is then reset, before its set minimum off−time periodexpires, at time t2 thanks to CS voltage lower thanVTH_CS_RESET threshold. The aforementioned resetsituation can be seen again at time t3, t4, t5 and t6. A

complete minimum off−time period elapses between timest7 and t8 allowing the IC to activate a driver output after timet8.

Minimum tON and tOFF AdjustmentThe NCP43080 offers an adjustable minimum on−time

and off−time blanking periods that ease the implementationof a synchronous rectification system in any SMPStopology. These timers avoid false triggering on the CS inputafter the MOSFET is turned on or off.

The adjustment of minimum tON and tOFF periods aredone based on an internal timing capacitance and externalresistors connected to the GND pin − refer to Figure 46 fora better understanding.


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Figure 46. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)

Current through the MIN_TON adjust resistor can becalculated as:

IR_MIN_TON �Vref

RTon_min(eq. 5)

If the internal current mirror creates the same currentthrough RMIN_TON as used the internal timing capacitor (Ct)charging, then the minimum on−time duration can becalculated using this equation.

tMIN_TON � Ct

Vref

IR_MIN_TON

� CtVref

Vref

RMIN_TON

� Ct � RMIN_TON

(eq. 6)

The internal capacitor size would be too large ifIR_MIN_TON was used. The internal current mirror uses aproportional current, given by the internal current mirrorratio. One can then calculate the MIN_TON andMIN_TOFF blanking periods using below equations:

tMIN_TON � 1.00 * 10−4 * RMIN_TON [�s] (eq. 7)

tMIN_TOFF � 1.00 * 10−4 * RMIN_TOFF [�s] (eq. 8)

Note that the internal timing comparator delay affects theaccuracy of Equations 7 and 8 when MIN_TON/MIN_TOFF times are selected near to their minimumpossible values. Please refer to Figures 47 and 48 formeasured minimum on and off time charts.


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Figure 47. MIN_TON Adjust Characteristics

Figure 48. MIN_TOFF Adjust Characteristics

RMIN_TON (k�)

9060504030201000

1

2

4

5

6

7

10t M

IN_T

ON

(�s)

100

3

8070

RMIN_TOFF (k�)

9060504030201000

1

2

4

5

6

7

10

t MIN

_TO

FF (�s)

100

3

8070

8

9

8

9

The absolute minimum tON duration is internally clampedto 55 ns and minimum tOFF duration to 245 ns in order toprevent any potential issues with the MIN_TON and/orMIN_TOFF pins being shorted to GND.

The NCP43080 features dedicated anti−ringingprotection system that is implemented with a MIN_TOFFblank generator. The minimum off−time one−shot generatoris restarted in the case when the CS pin voltage crossesVTH_CS_RESET threshold and MIN_TOFF period is active.The total off-time blanking period is prolonged due to theringing in the application (refer to Figure 38).

Some applications may require adaptive minimum on andoff time blanking periods. With NCP43080 it is possible tomodulate blanking periods by using an external NPNtransistor − refer to Figure 49. The modulation signal can bederived based on the load current, feedback regulatorvoltage or other application parameter.

Figure 49. Possible Connection for MIN_TON and MIN_TOFF Modulation


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Maximum tON adjustmentThe NCP43080Q offers an adjustable maximum on−time

(like the min_tON and min_tOFF settings shown above) thatcan be very useful for QR controllers at high loads. Underhigh load conditions the QR controller can operate in CCMthanks to this feature. The NCP43080Q version has theability to turn−off the DRV signal to the SR MOSFET beforethe secondary side current reaches zero. The DRV signalfrom the NCP43080Q can be fed to the primary side througha pulse transformer (see Figure 4 for detail) to a transistor onthe primary side to emulate a ZCD event before an actualZCD event occurs. This feature helps to keep the minimumswitching frequency up so that there is better energy transferthrough the transformer (a smaller transformer core can beused). Also another advantage is that the IC controls the SRMOSFET and turns off from secondary side before theprimary side is turned on in CCM to ensure no crossconduction. By controlling the SR MOSFET’s turn offbefore the primary side turn off, producing a zero crossconduction operation, this will improve efficiency.

The Internal connection of the MAX_TON feature isshown in Figure 50. Figure 50 shows a method that allowsfor a modification of the maximum on−time according tooutput voltage. At a lower VOUT, caused by hard overloador at startup, the maximum on−time should be longer than atnominal voltage. Resistor RA can be used to modulatemaximum on−time according to VOUT or any otherparameter.

The operational waveforms at heavy load in QR typeSMPS are shown in Figure 51. After tMAX_TON time isexceeded, the synchronous switch is turned off and thesecondary current is conducted by the diode. Informationabout turned off SR MOSFET is transferred by the DRV pinthrough a small pulse transformer to the primary side whereit acts on the ZCD detection circuit to allow the primaryswitch to be turned on. Secondary side current disappearsbefore the primary switch is turned on without a possibilityof cross current condition.

Figure 50. Internal Connection of the MAX_TON Generator, NCP43080Q


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VDS = VCS

VTH_CS _RESET – (RSHIFT _CS*ICS)

VTH_CS_OFF– (RSHIFT _CS*ICS)

VTH_CS _ON– (RSHIFT _CS*ICS)

VDRV

Min ON−time

t

Min OFF−time

tMIN_TON

tMIN_TOFF

ISEC

The tMIN _TON and tMIN_TOFF are adjustable by RMIN_TON and RMIN_TOFF resistors, tMAX_TON is adjustable by R MAX_TON

Turn−on delay Turn −off delay

Primary virtual ZCDdetection delay

Max ON−timetMAX _TON

Figure 51. Function of MAX_TON Generator in Heavy Load Condition

Adaptive Gate Driver Clamp and automatic Light LoadTurn−off

As synchronous rectification system significantlyimproves efficiency in most of SMPS applications duringmedium or full load conditions. However, as the loadreduces into light or no−load conditions the SR MOSFETdriving losses and SR controller consumption become morecritical. The NCP43080 offers two key features that help tooptimize application efficiency under light load and no loadconditions:

1st − The driver clamp voltage is modulated and followsthe output load condition. When the output load decreasesthe driver clamp voltage decreases as well. Under heavyload conditions the SR MOSFET’s gate needs to be drivenvery hard to optimize the performance and reduceconduction losses. During light load conditions it is not ascritical to drive the SR MOSFET’s channel into such a lowRDSON state. This adaptive gate clamp technique helps tooptimize efficiency during light load conditions especiallyin LLC applications where the SR MOSFETs with highinput capacitance are used.

Driver voltage modulation improves the system behaviorwhen SR controller state is changed in and out of normal ordisable modes. Soft transient between drop at body diode

and drop at MOSFET’s RDS(on) only improves stabilityduring load transients.

2nd − In extremely low load conditions or no loadconditions the NCP43080 fully disables driver output andreduces the internal power consumption when output loaddrops below the level where skip−mode takes place.

Both features are controlled by voltage at LLD pin. TheLLD pin voltage characteristic is shown in Figure 52. Drivervoltage clamp is a linear function of the voltage differencebetween the VCC and LLD pins from VLLD_REC point up toVLLD_MAX. A disable mode is available, where the ICcurrent consumption is dramatically reduced, when thedifference of VCC − VLLD voltage drops below VLLD_DIS.When the voltage difference between the VCC − VLLD pinsincrease above VLLC_REC the disable mode ends and the ICregains normal operation. It should be noted that there arealso some time delays to enter and exit from the disablemode. Time waveforms are shown at Figure 53. There is atime, tLLD_DISH, that the logic ignores changes from disablemode to normal or reversely. There is also some timetLLD_DIS_R that is needed after an exit from the disable modeto assure proper internal block biasing before SR controllerstarts work normally.


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VDRVCLAMP

VCC −VLLD

ICC

VDRVMAX

VLLD_MAXVLLD_DIS VLLD_REC

Figure 52. LLD Voltage to Driver Clamp and Current Consumption Characteristic (DRV Unloaded)

Figure 53. LLD Pin Disable Behavior in Time Domain

ICC

VCC−VLLD

DISABLE MODE NORMAL

NO

RM

AL

NO

RM

AL

DISABLE MODE

tLLD_DISH tLLD_DISH tLLD_DISHtLLD_DISH

VLLD_DIS

VLLD_REC

ttLLD_DIS_R

tLLD_DIS_R

The two main SMPS applications that are usingsynchronous rectification systems today are flyback andLLC topologies. Different light load detection techniquesare used in NCP43080 controller to reflect differences inoperation of both mentioned applications.

Detail of the light load detection implementationtechnique used in NCP43080 in flyback topologies isdisplayed at Figure 54. Using a simple and cost effectivepeak detector implemented with a diode D1, resistors R1

through R3 and capacitors C2 and C3, the load level can besensed. Output voltage of this detector on the LLD pin isreferenced to controller VCC with an internal differentialamplifier in NCP43080. The output of the differentialamplifier is then used in two places. First the output is usedin the driver block for gate drive clamp voltage adjustment.Next, the output signal is evaluated by a no−load detectioncomparator that activates IC disable mode in case the loadis disconnected from the application output.


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Figure 54. NCP43080 Light Load and No Load Detection Principle in Flyback Topologies

RTN

VmodulTo DRV clamp

To disablelogic

VCC

LLD

GND

NCP43080

Operational waveforms related to the flyback LLDcircuitry are provided in Figure 55. The SR MOSFET drainvoltage drops to ~ 0 V when ISEC current is flowing. Whenthe SR MOSFET is conducting the capacitor C2 charges−up,causing the difference between the LLD pin and VCC pin toincrease, and drop the LLD pin voltage. As the loaddecreases the secondary side currents flows for a shorter ashorter time. C2 has less time to accumulate charge and thevoltage on the C2 decreases, because it is discharged by R2and R3. This smaller voltage on C2 will cause the LLD pinvoltage to increase towards VCC and the difference betweenLLD and VCC will go to zero. The output voltage then

directly reduces DRV clamp voltage down from itsmaximum level. The DRV is then fully disabled when ICenters disable mode. The IC exits from disable mode whendifference between LLD voltage and VCC increases overVLLD_REC. Resistors R2 and R3 are also used for voltagelevel adjustment and with capacitor C3 form low pass filterthat filters relatively high speed ripple at C2. This low passfilter also reduces speed of state change of the SR controllerfrom normal to disable mode or reversely. Time constantshould be higher than feedback loop time constant to keepwhole system stable.

Figure 55. NCP43080 Driver Clamp Modulation Waveforms in Flyback Application Entering into Light/No LoadCondition

ISEC

VC2

VDRV

VC3

VLLDMAXVLLD_REC

VLLD_DIS VDRVMAX

t

IC enters disable mode


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Figure 56. NCP43080 Driver Clamp Modulation Circuitry Transfer Characteristic in Flyback Application

IOUT

VCC−VLLD

VDRV

IC enters disable mode

VLLDMAXVLLD_REC VLLD_DIS

VDRVMAX

t

The technique used for LLD detection in LLC is similarto the LLD detection method used in a flyback with the

exception the D1 and D2 OR−ing diodes are used to measurethe total duty cycle to see if it is operating in skip mode.

Figure 57. NCP43080 Light Load Detection in LLC Topology

RTN

VmodulTo DRV clamp

To disablelogic

VCC

LLD

GND

VmodulTo DRV clamp

To disablelogic

VCC

LLD

GND

NCP43080

NCP43080

The driver clamp modulation waveforms of NCP43080 inLLC are provided in Figure 58. The driver clamp voltageclips to its maximum level when LLC operates in normalmode. When the LLC starts to operate in skip mode thedriver clamp voltage begins to decrease. The specific outputcurrent level is determined by skip duty cycle and detection

circuit consists of R1, R2, R3, C2, C3 and diodes D1, D2.The NCP43080 enters disable mode in low load condition,when VCC−VLLD drops below VLLD_DIS (0.9 V). Disablemode ends when this voltage increase above VLLD_REC(1.0 V) Figure 59 shows how LLD voltage modulates thedriver output voltage clamp.


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VCS1

VCS2

VC2

VCC−VLLD

DRV clamp

Skip operationNormal operation

(VC3)

IC entersdisable mode

VDRVMAX

VLLDMAX

VLLD_REC VLLD_DIS

t

Figure 58. NCP43080 Driver Clamp Modulation Waveforms in LLC Application

VCC−VLLD

IOUT

DRV clamp

IC entersdisable modeVLLDMAX

VLLD_REC VLLD_DIS

VDRVMAX

tFigure 59. NCP43080 Driver Clamp Modulation Circuitry Characteristic in LLC Application


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There exist some LLC applications where behaviordescribed above is not the best choice. These applicationstransfer significant portion of energy in a few first pulses inskip burst. It is good to keep SR fully working during skipmode to improve efficiency. There can be still saved someenergy using LLD function by activation disable modebetween skip bursts. Simplified schematic for this LLD

behavior is shown in Figure 60. Operation waveforms forthis option are provided in Figure 61. Capacitor C2 ischarged to maximum voltage when LLC is switching. Whenthere is no switching in skip, capacitor C2 is discharged byR2 and when LLD voltage referenced to VCC falls belowVLLD_DIS IC enters disable mode. Disable mode is endedwhen LLC starts switching.

Figure 60. NCP43080 Light Load Detection in LLC Application − Other Option

RTN

VmodulTo DRV clamp

To disablelogic

VCC

LLD

GND

VmodulTo DRV clamp

To disablelogic

VCC

LLD

GND

NCP43080

NCP43080


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VCS1

VCS2

VC2

VCC−VLLD

DRV clamp

Skip operationNormal operation

IC enters disable modeVDRVMAX

VLLDMAX

VLLD_RECVLLD_DIS

tFigure 61. NCP43080 Light Load Detection Behavior in LLC Application – Other Option

Power Dissipation CalculationIt is important to consider the power dissipation in the

MOSFET driver of a SR system. If no external gate resistoris used and the internal gate resistance of the MOSFET isvery low, nearly all energy losses related to gate charge aredissipated in the driver. Thus it is necessary to check the SRdriver power losses in the target application to avoid overtemperature and to optimize efficiency.

In SR systems the body diode of the SR MOSFET startsconducting before SR MOSFET is turned−on, because thereis some delay from VTH_CS_ON detect to turn−on the driver.On the other hand, the SR MOSFET turn off process alwaysstarts before the drain to source voltage rises up

significantly. Therefore, the MOSFET switch alwaysoperates under Zero Voltage Switching (ZVS) conditionswhen in a synchronous rectification system.

The following steps show how to approximately calculatethe power dissipation and DIE temperature of theNCP43080 controller. Note that real results can vary due tothe effects of the PCB layout on the thermal resistance.

Step 1 − MOSFET Gate−to Source Capacitance:During ZVS operation the gate to drain capacitance does

not have a Miller effect like in hard switching systemsbecause the drain to source voltage does not change (or itschange is negligible).


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Figure 62. Typical MOSFET CapacitancesDependency on VDS and VGS Voltages

Ciss � Cgs � Cgd

Crss � Cgd

Coss � Cds � Cgd

Therefore, the input capacitance of a MOSFET operatingin ZVS mode is given by the parallel combination of the gateto source and gate to drain capacitances (i.e. Ciss capacitancefor given gate to source voltage). The total gate charge,

Qg_total, of most MOSFETs on the market is defined for hardswitching conditions. In order to accurately calculate thedriving losses in a SR system, it is necessary to determine thegate charge of the MOSFET for operation specifically in aZVS system. Some manufacturers define this parameter asQg_ZVS. Unfortunately, most datasheets do not provide thisdata. If the Ciss (or Qg_ZVS) parameter is not available then

it will need to be measured. Please note that the inputcapacitance is not linear (as shown Figure 62) and it needsto be characterized for a given gate voltage clamp level.

Step 2 − Gate Drive Losses Calculation:Gate drive losses are affected by the gate driver clamp

voltage. Gate driver clamp voltage selection depends on thetype of MOSFET used (threshold voltage versus channelresistance). The total power losses (driving loses andconduction losses) should be considered when selecting thegate driver clamp voltage. Most of today’s MOSFETs for SRsystems feature low RDS(on) for 5 V VGS voltage. TheNCP43080 offers both a 5 V gate clamp and a 10 V gateclamp for those MOSFET that require higher gate to sourcevoltage.

The total driving loss can be calculated using the selectedgate driver clamp voltage and the input capacitance of theMOSFET:

PDRV_total � VCC � VCLAMP � Cg_ZVS � fSW (eq. 9)

Where:VCC is the NCP43080 supply voltageVCLAMP is the driver clamp voltageCg_ZVS is the gate to source capacitance of the

MOSFET in ZVS modefsw is the switching frequency of the target

applicationThe total driving power loss won’t only be dissipated in

the IC, but also in external resistances like the external gateresistor (if used) and the MOSFET internal gate resistance(Figure 44). Because NCP43080 features a clamped driver,it’s high side portion can be modeled as a regular driverswitch with equivalent resistance and a series voltagesource. The low side driver switch resistance does not dropimmediately at turn−off, thus it is necessary to use anequivalent value (RDRV_SIN_EQ) for calculations. Thismethod simplifies power losses calculations and stillprovides acceptable accuracy. Internal driver powerdissipation can then be calculated using Equation 10:


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Figure 63. Equivalent Schematic of Gate Drive Circuitry

PDRV_IC �1

2� Cg_ZVS � VCLAMP

2 � fSW � � RDRV_SINK_EQ

RDRV_SINK_EQ � RG_EXT � Rg_int�� Cg_ZVS � VCLAMP � fSW � �VCC � VCLAMP

�

�1

2� Cg_ZVS � VCLAMP

2 � fSW � � RDRV_SOURCE_EQ

RDRV_SOURCE_EQ � RG_EXT � Rg_int�

(eq. 10)

Where:RDRV_SINK_EQ is the NCP43080x driver low side switch

equivalent resistance (0.5 �)RDRV_SOURCE_EQ is the NCP43080x driver high side switch

equivalent resistance (1.2 �)RG_EXT is the external gate resistor (if used)Rg_int is the internal gate resistance of the

MOSFET

Step 3 − IC Consumption Calculation:In this step, power dissipation related to the internal IC

consumption is calculated. This power loss is given by theICC current and the IC supply voltage. The ICC currentdepends on switching frequency and also on the selected mintON and tOFF periods because there is current flowing outfrom the min tON and tOFF pins. The most accurate methodfor calculating these losses is to measure the ICC currentwhen CDRV = 0 nF and the IC is switching at the targetfrequency with given MIN_TON and MIN_TOFF adjustresistors. IC consumption losses can be calculated as:

PCC � VCC � ICC (eq. 11)

Step 4 − IC Die Temperature Arise Calculation:The die temperature can be calculated now that the total

internal power losses have been determined (driver lossesplus internal IC consumption losses). The package thermalresistance is specified in the maximum ratings table for a35 �m thin copper layer with no extra copper plates on anypin (i.e. just 0.5 mm trace to each pin with standard solderingpoints are used).

The DIE temperature is calculated as:

TDIE � �PDRV_IC � PCC� � R�J−A � TA (eq. 12)

Where:PDRV_IC is the IC driver internal power dissipationPCC is the IC control internal power

dissipation R�JA is the thermal resistance from junction to

ambientTA is the ambient temperature


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PRODUCT OPTIONS

OPN Package UVLO [V] DRV clamp [V] Pin 5 function Usage

NCP43080ADR2G SOIC8 4.5 4.7 NC

LLC, CCM flyback, DCM flyback, forward,QR, QR with primary side CCM control

NCP43080AMTTWG WDFN8 4.5 4.7 NC

NCP43080DDR2G SOIC8 4.5 9.5 NC

NCP43080DMNTWG DFN8 4.5 9.5 NC

NCP43080DMTTWG WDFN8 4.5 9.5 NC

NCP43080QDR2G SOIC8 4.5 9.5 MAX_TON QR with forced CCM from secondary side

ORDERING INFORMATION

Device Package Package marking Packing Shipping†

NCP43080ADR2G SOIC8 43080A SOIC−8(Pb−Free)

2500 /Tape & Reel

NCP43080DDR2G 43080D

NCP43080QDR2G 43080Q

NCP43080AMTTWG WDFN8 FA WDFN−8(Pb−Free)

3000 /Tape & Reel

NCP43080DMTTWG FD

NCP43080DMNTWG DFN8 43080D DFN−8(Pb−Free)

4000 /Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.


ÉÉÉÉÉÉ

DFN8, 4x4CASE 488AF−01

ISSUE CDATE 15 JAN 2009

NOTES:1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.

5. DETAILS A AND B SHOW OPTIONAL CON-STRUCTIONS FOR TERMINALS.

DIM MIN MAXMILLIMETERS

A 0.80 1.00A1 0.00 0.05A3 0.20 REFb 0.25 0.35D 4.00 BSCD2 1.91 2.21E 4.00 BSC

E2 2.09 2.39e 0.80 BSCK 0.20 −−−L 0.30 0.50

DB

E

C0.15

A

C0.15

2X

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

ÇÇÇÇ

ÇÇÇÇ

Ç

C

A

(A3)A1

8X

SEATINGPLANE

C0.08

C0.10

Ç

ÇÇÇÇÇe

8X L

K

E2

D2

b

NOTE 3

1 4

588X

0.10 C

0.05 C

A B

1SCALE 2:1

XXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

XXXXXXXXXXXXALYW�

�

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.

PIN ONEREFERENCE

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

8X0.63

2.21

2.39

8X

0.80PITCH

4.30

0.35


L1

DETAIL A

L

OPTIONALCONSTRUCTIONS

ÉÉÉÉÉÉÇÇÇ

A1

A3

L

ÇÇÇÇÇÇÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATECONSTRUCTIONS

L1 −−− 0.15

DETAIL B

NOTE 4

DETAIL A

DIMENSIONS: MILLIMETERS

PACKAGEOUTLINE

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON15232DDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1DFN8, 4X4, 0.8P

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

ÍÍÍÍÍÍ

C

A

SEATINGPLANE

D

E

0.10 C

A3

A

A1

0.10 C

WDFN8 2x2, 0.5PCASE 511AT−01

ISSUE ODATE 26 FEB 2010

SCALE 4:1

DIMA

MIN MAXMILLIMETERS

0.70 0.80A1 0.00 0.05A3 0.20 REFb 0.20 0.30DEeL

PIN ONEREFERENCE

0.05 C

0.05 C

A0.10 C

NOTE 3

L2

e

bB

4

88X

1

5

0.05 C

L1

2.00 BSC2.00 BSC0.50 BSC

0.40 0.60--- 0.15

BOTTOM VIEW

L7X

L1

DETAIL A

L

ALTERNATE TERMINALCONSTRUCTIONS

L

ÉÉÉÉÉÉÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATECONSTRUCTIONS

DETAIL B

DETAIL A

L2 0.50 0.70

B

TOP VIEW

SIDE VIEW

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30 MM FROM TERMINAL TIP.



2.30

0.50

0.787X

DIMENSIONS: MILLIMETERS0.30 PITCH

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.


8X

1

PACKAGEOUTLINE

RECOMMENDED

XX = Specific Device CodeM = Date Code� = Pb−Free Device

XXM�

�

1

0.88


2X

2X

8X

e/2


PACKAGE DIMENSIONS


98AON48654EDOCUMENT NUMBER:

DESCRIPTION:


PAGE 1 OF 1WDFN8, 2X2, 0.5 P


SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package


1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1



Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.


PACKAGE DIMENSIONS


98ASB42564BDOCUMENT NUMBER:

DESCRIPTION:


PAGE 1 OF 2SOIC−8 NB


SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1


98ASB42564BDOCUMENT NUMBER:

DESCRIPTION:


PAGE 2 OF 2SOIC−8 NB


onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliatesand/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to anyproducts or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its productsand applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications informationprovided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systemsor any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. ShouldBuyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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