Safe Harbor Statement - ChinaFlashMarket · Global talent fuels innovation Top 50 on US Patent list...
Transcript of Safe Harbor Statement - ChinaFlashMarket · Global talent fuels innovation Top 50 on US Patent list...
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Safe Harbor StatementDuring the course of this meeting, we may make projections or other forward-looking statements regarding future events or the future financial performance of the Company and the industry. We wish to caution you that such statements are predictions and that actual events or results may differ materially. We refer you to the documents the Company files from time to time with the Securities and Exchange Commission, specifically the Company’s most recent Form 10-K and Form 10-Q. These documents contain and identify important factors that could cause the actual results for the Company to differ materially from those contained in our projections or forward-looking statements. These certain factors can be found at http://www.micron.com/certainfactors. Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements. We are under no duty to update any of the forward-looking statements after the date of the presentation to conform these statements to actual results.
©2019 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice.
All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including regarding their
features, availability, functionality, or compatibility, are provided for informational purposes only and do not modify the warranty, if any,
applicable to any product. Drawings may not be to scale. Micron, the Micron logo, and all other Micron trademarks are the property of
Micron Technology, Inc. All other trademarks are the property of their respective owners.
Scott DeBoer, Executive Vice President
2019 Analyst & Investor Webcast | May 2019
Accelerating Memory and Storage Innovation
Team
Core Technology
Execution
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Agenda
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Team
Core Technology
Execution
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Industry’s Best TalentGetting Even Stronger
Attracting the World’s Best
>50% of R&D new hires with MS, PhD
>60% technical with industry experience
Certified 2018 Great Place to Work
Strong and Getting Stronger
Global talent fuels innovation
Top 50 on US Patent list
Forbes 2019 “The Best Employer for Diversity” list
New TalentTeamAdvancing STEM Education
Advancing Curiosity grants
Promoting STEM education
Engaged with top global universities
Pipeline
3D XPointTM
Utah, U.S.PackagingTaiwan
DRAMJapan
NANDSingapore
Strong Development Capability at Manufacturing Locations
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Global Technology DevelopmentDelivering World Leading Innovation and Execution
Core R&DIdaho, U.S.
Accelerate Core Technology with Disruptive Innovation
Automotive Virginia, U.S.
Core Technology Delivering Across Spectrum of Customer Needs
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Reliable
High Performance
Light &Thin
Low Power
Reliable
High Bandwidth
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Team
Core Technology
Execution
DRAM
3D NANDNOR
3D XPointTM
3D Packaging
Emerging Technologies
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Core TechnologyThe Industry’s Most Comprehensive Technology Portfolio
DRAM
Core Technology
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1Znm DRAMContinuing Rapid Improvement in Competitive Position
Competitor 1 Competitor 2 Micron
Mid High Speed
Power Consumption – YouTube (lower = better)*
1.0X
1.6X1.3X
Competitor 1 Competitor 2 Micron
Mid Low Speed
Power Consumption -- Music (lower = better)*
1.0X
1.7X
1.1X
1Znm DRAM: 16Gb LP-DDR4
*Source: Micron – performance based on competitor samples and results may vary
Industry leading mobile 16Gb
Rapid progress on 1Znm yield ramp
Strengthening competitive position
Source: Micron12
DRAM Scaling TrendsDRAM Scaling Challenges Evident in Industry Trends
Gb/Wafer increases significantly more difficult
Cost of node transitions challenging ultimate benefits
Capex Intensity continues to grow
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
% C
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DRAM Gb per Wafer Growth Over Time
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
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Cost Reduction per Gb Over Time
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DRAM Scaling: Driving Towards Technology LeadershipContinuing to Extend Roadmap for Cost and Performance Improvement
Technology roadmap extending
Difficult physics and cost challenges beyond 1b
Node transition value evolution
Yield Improvement1α Early Process
Integration1bCustomer Qualification 1Z Architectural
Pathfinding1g
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Optimized Approach to Lithography Multiple Patterning Technology Optimized for Micron Future DRAM Nodes
Lithography technology breakpoints & relative costs
EUV Double Patterning
ImmersionQuad Patterning Limit
ImmersionDouble Patterning Limit
Region for Future Critical Level Processing
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5.5
4.5
3.5
2.5
1.5
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Cost Compared to Immersion
EUV Limit
DRAM Node 1Z1g 1b 1a 1X1Y
Co
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Mu
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Micron’s pattern multiplication technology is a strategic advantage
Proven technology capability and cost efficiency for 1Znm through 1gnm
Ongoing evaluation of EUV Lithography for DRAM
Prepared for implementation of EUV when beneficial to Micron
Uniformity(Local Variation)
Cost Competitiveness ($ per Wafer)
DRAM 1Znm → 1anm Immersion Multi Patterning
EUV Single Exposure
Optimal Dose
DRAM beyond 1anm Immersion Multi Patterning
EUVSingle Exposure
High Dose
EUVSingle Exposure
Low Dose
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Optimized Approach to Lithography EUV Patterning Challenges for Advanced DRAM Applications
Source: Micron
NAND
Core Technology
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Solid Progress on Replacement Gate Technology Provides Confidence for Transition
128 Layer NAND
Transition from Floating Gate to Replacement Gate
Continued use of CMOS under array technology
3rd node of array stacking
Enables leadership in die size, sequential write performance and write energy/bit
32 LayerGen. 1
32 32
32
64 LayerGen. 2
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96 LayerGen. 3
128 LayerGen. 4
64
64
Periphery Circuitry
Memory Array
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NAND Scaling Trends
Substantial increase in Gb/wafer driven by planar to 3D conversion
Gb/wafer growth slows beyond the 64 layer transition
Industry rate of cost reduction leveling off
Node to Node Benefits Reducing Post 3D NAND Transition
Source: Micron
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NAND Gb per Wafer Growth Over Time
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Cost Reduction per Gb Over Time
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NAND Scaling: Leadership Through Technology Transition Delivering World Leading Cost and Performance
RG technology transition primary focus
Density increases and cost reductions slowing
Driving towards cost and performance leadership
96 Layer FGMature Yield
1YY Layer RGEarly Process Integration
128 Layer RG Yield Improvement
2XX Layer RG Architectural Pathfinding
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Team
Core Technology
Execution
Source: Micron
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Delivering Faster Yield RampsTime to Mature Yield Reduced by More than Half
DRAM
Time to Mature Yield
(25nm)
(1Ynm)
(20nm)
(1Xnm)
NAND
(16nm)
(96 layer)
(32 layer)
(64 layer)
Time to Mature Yield
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Driving our performance to a still higher level.
Team Technology Execution
Micron Confidential23