S ynthesis of Communication Schedules for TTEthernet -based Mixed-Criticality Systems
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Transcript of S ynthesis of Communication Schedules for TTEthernet -based Mixed-Criticality Systems
Synthesis of Communication Schedules forTTEthernet-based Mixed-Criticality Systems
Domițian Tămaș-Selicean1, Paul Pop1 and Wilfried Steiner2
1Technical University of Denmark2TTTech Computertechnik AG
2
OutlineMotivationTTEthernet
ARINC 664p7 “Aircraft Data Network” TT and RC Traffic Transmission
Problem Formulation Motivational Example
Optimization Strategy RC End-to-End Analysis
Experimental resultsConclusions
3
Point-to-point connection
Motivation Real time applications implemented using distributed systems
PE
Application A 1 -- highly critical
Application A 2 -- critical
Application A 3 -- non-critical
Bus connection
Reduces wiring and weight Mixed-criticality applications share
the same network
4
ARINC 664 p7 “Aircraft Data Network”
ES1
ES2
NS1 NS2
ES3
ES4
Full-Duplex Ethernet-based data network for safety-critical applications
End System
Network Switch
5
ARINC 664 p7 “Aircraft Data Network”
ES1
ES2
NS1 NS2
ES3
ES4
CPURAM
ROMNIC
6
ARINC 664 p7 “Aircraft Data Network”
ES1
ES2
NS1 NS2
ES3
ES4
NS1 to ES1
ES1 to NS1
dataflow link
7
ARINC 664 p7 “Aircraft Data Network”
NS1 NS2
vl2
vl1
ES1τ1
ES2τ4
ES3τ2 τ5
ES4τ3
Highly critical application A 1: τ1, τ2 and τ3
τ1 sends message m1 to τ2 and τ3
Non-critical application A 2: τ4 and τ5
τ4 sends message m2 to τ5
virtual link
8
ARINC 664 p7 “Aircraft Data Network”
NS1 NS2
dp1
vl1
dp2
l1
l2
l3
l4
ES1τ1
ES2τ4
ES3τ2 τ5
ES4τ3dataflow
path
Highly critical application A 1: τ1, τ2 and τ3
τ1 sends message m1 to τ2 and τ3
Non-critical application A 2: τ4 and τ5
τ4 sends message m2 to τ5
9
ARINC 664 p7 “Aircraft Data Network”
Deterministic Event Triggered communicationSeparation of traffic enforced through “bandwidth allocation”Bandwidth Allocation Gap (BAG) – minimum time interval
between two consecutive instances of a frame on a virtual link
fx,1
fx,2
BAGx
Maximum bandwidth assigned to virtual link vli
BW (vli) = fi .size/BAGi
10
TTEthernet
ARINC 664p7 compliantTraffic classes:
synchronized communication Time Triggered (TT)
unsynchronized communication Rate Constrained (RC) – ARINC 664p7 traffic class Best Effort (BE) – no timing guarantees
Standardized as SAE AS 6802Marketed by TTTech Computertechnik AG Implemented by Honeywell on the NASA Orion Constellation
11
TTEthernet
Composed of clustersEach cluster has a clock synchronization domain Inter-cluster communication using RC traffic
ES1
ES2
NS1
ES3
ES4
ES5
ES6
NS2
ES7
ES8
Cluster 1 Cluster 2
12
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
b
13
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
14
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
15
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
16
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
17
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
18
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
19
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
20
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
21
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
22
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
23
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
24
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
25
b
b
TT Transmission
CPU
P1,1 τ
1
P1,2 τ
2
B2,Tx
B1,Tx
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
TT
a
c
de
f
g
h
ij
k lm
SR
SS
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
a
c
d
e
f
g
h
i
j
k
l
m
Packing message m2 into frame f2
Place f2 in buffer B1,Tx for transmissionSend time specified in send schedule SS
TTS sends f2 to NS1
f2 is sent on the dataflow link to NS1
The Filtering Unit (FU) checks the frame f2
Expected receive time specified in receive schedule SR
TTR checks if f2 arrives according to schedulePlace f2 in buffer B1,Tx for transmission
Send time specified in send schedule SS
FU checks f2
Store the frame into receive buffer B2,Rx
Task τ4 reads f2 from buffer
b
26
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
27
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
28
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
29
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
30
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
31
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
32
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
33
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
34
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
35
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
36
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
37
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
38
RC Transmission
CPU
P1,1 τ
1
P1,2 τ
2
Q1,Tx
Q2,Tx
B2,Tx
B1,Tx
TR2
TR1
RCS
TTS
P1,3
P2,1τ
4
P2,2τ
3
P2,3
CPUFU
Q1,Rx
Q2,Rx
B1,Rx
B2,Rx
ES1
ES2
NS2
NS3
FU
TP
TTR
B1,Tx
B2,Tx
TTS
NS1
SS
f2
f3
f4
f1
RC
TT
QTx
1
2 34
5
67
8 9
10
11
12
13
SR
SS
1 Packing message m1 into frame f1
2 Insert it in queue Q1,Tx
3 Traffic Regulator (TR) ensures bandwidth for each VL4 RC scheduler RC multiplexes frames coming from TRs5 TTS transmits f1 when there is no TT traffic6 f1 is sent on the dataflow link to NS1
7 FU checks the validity of the frame
8 Traffic Policing (TP) checks that f2 arrives according to the BAG
9 Copy f1 to outgoing queue QTx10 Send f1 when there is no TT traffic11 FU checks f112
Copy to receiving Q2,Rx13
Task τ3 reads f1 from the queue
A1: τ
1 à m
1 à τ
3, RC
A2: τ
2 à m
2 à τ
4, TT
39
Problem formulationGiven
The topology of the network G The set of TT and RC frames FTT and FRC
The set of virtual links VL The assignment of frames to virtual links M For each frame the size, the deadline and the period
40
Problem formulationGiven
The topology of the network G The set of TT and RC frames FTT and FRC
The set of virtual links VL The assignment of frames to virtual links M For each frame the size, the deadline and the period
Determine The set of TT schedules
41
Problem formulationGiven
The topology of the network G The set of TT and RC frames FTT and FRC
The set of virtual links VL The assignment of frames to virtual links M For each frame the size, the deadline and the period
Determine The set of TT schedules
Such that The deadlines for the TT and RC frames are satisfied The end-to-end delay of RC frames is minimized
42
Motivational Example
ES1
ES2
NS1 ES3
vl3
vl1
vl2
period (us) deadline (us) Ci (us) M
f1 ∈ FRC 300 300 75 vl1
f2 ∈ FTT 200 200 50 vl2
f3 ∈ FTT 300 300 50 vl3
43
Motivational Example
ES1
ES2
NS1 ES3
vl3
vl1
vl2
period (us)
deadline (us) Ci (us) M
f1 ∈ FRC 300 300 75 vl1f2 ∈ FTT 200 200 50 vl2f3 ∈ FTT 300 300 50 vl3
Initial TT schedule
44
Motivational Example
ES1
ES2
NS1 ES3
vl3
vl1
vl2
period (us)
deadline (us) Ci (us) M
f1 ∈ FRC 300 300 75 vl1f2 ∈ FTT 200 200 50 vl2f3 ∈ FTT 300 300 50 vl3
Optimized TT schedule
45
Optimization Strategy
TTEthernet Schedule Optimization (TTESO) strategy: Tabu Search meta-heuristic
The TT schedules S Such that:
TT and RC frames are schedulable The end-to-end delay of the RC frames is minimized
Tabu Search Minimizes the cost function Explores the solution space using design transformations
46
Optimization StrategyDegree of schedulability
Captures the difference between the worst-case delay and deadline
Cost Function
47
Optimization Strategy: Design Transformations
TT frame moves advance frame transmission time advance frame predecessors transmission time postpone frame transmission time postpone frame successors transmission time
RC frame moves reserve space for RC frame resize reserved space for RC frame remove reserved space for RC frame
48
Frame Representation for Moves
ES1
ES2
NS1 NS2
ES3
ES4vl1
f1,1[ES1, NS1] f1,1
[NS1, NS2]
f1,1[NS1, NS2]
f1,1[NS1, NS2]
49
Design transformations: Postpone move
50
Design transformations: Advance move
51
Design transformations: Reserve space for RC
52
Design transformations: Resize RC reserved space
53
RC Frame End-to-End Analysis
On a dataflow link, a RC frame can be delayed by: scheduled TT frames queued RC frames technical latency policy specific:
timely block pre-emption
54
RC Frame End-to-End Analysis
ES1
NS2
NS1 ES4
vl3
vl2vl1
NS3
NS2 → NS
1f
3,j
0 100 200 300 400 500 600
f4,1NS
3 → NS
1
NS1 → ES
4
f2,1ES
1 → NS
1f
1,i
f2,1
f4,1
f1,i
f3,j
C [NS1, ES
4]
f1
QTT
[NS1, ES
4] QRC
[NS1, ES
4]
QTL
NS1
R f1
vl4
55
RC Frame End-to-End Analysis
Approaches for analysis of ARINC 644p7 network traffic: Network Calculus, (Boyer, 2008) Finite State Machine, (Saha, 2007) Timed Automata, (Adnan, 2010) Trajectory Approach, (Bauer, 2009)
We use the method proposed in (Steiner, 2011) it takes into account also the TT traffic it is pessimistic:
does not ignore frames that already delayed a RC frame on a previous link
assumes uniformly distributed intervals of equal length reserved for RC traffic
56
Experimental Results
Benchmarks 17 synthetic 1 real life test cases based on the SAE Automotive benchmark
TTESO compared to: Straightforward Solution (SS)
Builds TT schedules with the goal of minimizing the end-to-end delay of TT frames, without considering the RC frames
57
Experimental Results
58
Experimental Results
59
Experimental Results
60
Experimental Results
61
Experimental Results
62
ConclusionsTTEthernet is very well suited for mixed-criticality applications
Predictability is achieved using three classes of traffic: TT, RC and BE Spatial separation is achieved trough virtual links Temporal separation is enforced by schedule tables for TT traffic and
bandwidth allocation for RC traffic
We have addressed the optimization of the TTEthernet protocol The TT schedules are determined such that TT and RC frames are
schedulable, and the end-to-end delay of the RC frames is minimized
Optimization tools are needed to support the designer in order to obtain schedulable solutions We have proposed a Tabu Search-based optimization solution
63