S. Reda EN160 SP08 Design and Implementation of VLSI Systems (EN1600) Lecture11: Delay Estimation...

S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture11: Delay Estimation

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]


Circuit characterization: delay and power estimation

Delay estimation Logical effort for delay estimation Power estimation Interconnects and wire engineering Scaling theory


Delay definitions

• tpdr: rising propagation delay– From input to rising output crossing VDD/2

• tpdf: falling propagation delay– From input to falling output crossing VDD/2

• tpd: average propagation delay. tpd = (tpdr + tpdf)/2• tcdr: rising contamination (best-case) delay

– From input to rising output crossing VDD/2• tcdf: falling contamination (best-case) delay

– From input to falling output crossing VDD/2• tcd: average contamination delay. tpd = (tcdr + tcdf)/2• tr: rise time

– From output crossing 0.2 VDD to 0.8 VDD• tf: fall time

– From output crossing 0.8 VDD to 0.2 VDD


How to calculate delay? Just run SPICE!

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf = 66ps tpdr = 83psVin Vout

• Time consuming• Not very useful for designers in evaluating different options

and optimizing different parameters

• We need a simple way to estimate delay for “what if” scenarios.• Fidelity vs. accuracy


Transistor resistance

In the linear region

• Not accurate, but at least shows that the resistance is proportional to L/W and decreases with Vgs

• If R/C are for a unit size transistor then a transistor of K unit width has KC capacitance and R/K resistance

• The resistance of a PMOS transistor = 2× resistance of NMOS transistor of the same size


Switch-level RC models

• Use equivalent circuits for MOS transistors– Ideal switch + capacitance and ON resistance

– Unit nMOS has resistance R, capacitance C

– Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width• Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kCR/k

kg

s

d

g

s

d

kC

kC

kC

2R/k


Inverter RC delay estimate

• Estimate the delay of a fanout-of-1 inverter in response to a step input function

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

tpd = 6RC


Elmore delay model

• ON transistors look like resistors• Pullup or pulldown network modeled as RC ladder• Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

( ) ( )nodes

1 1 1 2 2 1 2... ...

pd i to source ii

N N

t R C

RC R R C R R R C

− −≈

= + + + + + + +

∑


Example: 3-input NAND gate

• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

3

3

222

3



2 2 2

3

3

33C

3C

3C

3C

2C

2C

2C

2C

2C

2C

3C

3C

3C

2C 2C 2C

• Annotate the 3-input NAND gate with gate and diffusion capacitance



• Annotate the 3-input NAND gate with gate and diffusion capacitance

9C

3C

3C3

3

3

222

5C

5C

5C


Computing the rise and fall delays

• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

h copies

6C

2C2

2

22

4hC

B

Ax

Y

R

(6+4h)CY ( )6 4pdrt h RC= +

( )( ) ( ) ( )( )

2 2 22 6 4

7 4

R R Rpdft C h C

h RC

= + + +⎡ ⎤⎣ ⎦= +

(6+4h)C2CR/2

R/2x Y


Delay components

• Delay has two components:– Parasitic delay (due to gate own diffusion capacitance)

• 6 or 7 RC

• Independent of load

– Effort delay• 4h RC

• Proportional to load capacitance


Contamination delay• Best-case (contamination) delay can be substantially less than

propagation delay.• Ex: If both inputs fall simultaneously

6C

2C2

2

22

4hC

B

Ax

Y

R

(6+4h)CYR

( )3 2cdrt h RC= +

• Order of inputs also impact propagation delay. Which is better AB=10 -> 11 or AB=01 ->11?


Diffusion capacitance

7C

3C

3C3

3

3

222

3C

2C2C

3C3C

IsolatedContactedDiffusionMerged

UncontactedDiffusion

SharedContactedDiffusion

• we assumed contacted diffusion on every s / d.• Good layout minimizes diffusion area• Ex: NAND3 layout shares one diffusion contact

– Reduces output capacitance by 2C– Merged uncontacted diffusion might help too


Layout Comparison

• Which layout is better?

AVDD

GND

B

Y

AVDD

GND

B

Y

S. Reda EN160 SP08 Design and Implementation of VLSI Systems (EN1600) Lecture11: Delay Estimation...

Documents

Transcript of S. Reda EN160 SP08 Design and Implementation of VLSI Systems (EN1600) Lecture11: Delay Estimation...