Application Note

WEBSITE: www.jdsu.com

Running OTN FEC Systems to ITU-T G.709 Standard with the ONT-5xxby Daniel Bleicher

Running OTN FEC systems to ITU-T G.709 standardThe optical transport network (OTN) is one of the major steps in moving towards deploying agile optical networks (AON). This step allows network providers to leverage from available fiber infrastructure with Forward Error Correction (FEC) which minimizes the number of 3R regenerators needed in a network. The OTN system is transparent for various clients and accommodates extended tandem connection monitoring (TCM) processes for easy fault location in multi provider networks. The ITU-T has published the following recommendations giving guidelines for OTN elements.G.709: “Interfaces for the OTN” G.798: “Characteristics of OTN hierarchy equipment functional blocks”.

OTN bit rates:

OTU-1: 2.666 057 Gb/sOTU-2: 10.709 255 Gb/sOTU-3: 43.018 414 Gb/sOTU-LAN without fixed stuff: 11.049 107 Gb/s (not standardized)OTU-LAN with fixed stuff: 11.095 730 Gb/s (not standardized)The OTN frame consists of: the mapped transparent client, the extensive overhead (OH) which is used for operations, administrations, monitoring and provisioning (OAM&P) and the FEC. As with SDH/SONET, the quality of transmission is monitored by multiple parity checks and the corresponding reactions of the OTN elements. These new systems are cur-rently designed, produced and installed by several different vendors.To check the designs and elements produced against ITU-T recommendations, various tests must be performed according to the following categories:• Interface specification

• DUT response

• ITU-T conformance and interoperability

• Mapping/demapping of client signals

• Correct FEC behavior

The following pages describe these tests performed with JDSU’s Optical Network Testers ONT-506 and ONT-512.

Menu ONT-5xx: DUT alarm responses

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 2

Figure 2: Verify alarm responses

During verification, the JDSU ONT-5xx optical network tester sends a stimulus to the DUT and checks for the responses in the up and downstream. For example, the detection of a LOF at the 10.7G interface will force an OTU-AIS in the 10.7G forward and an OTU-BDI in the 10.7G backward signal (figure 2).

Figure 3: OTN maintenance integration

During system verification, the condition of the combina-tion must be checked against the ITU-T recommendation G.798. The ONT-5xx and the controller of the DUT show the alarm status simultaneously. Should the results of DUT and the ONT-5xx not match, the user receives information on the DUT allowing for further investigations to be carried out.

Are the line interfaces compliant with ITU-T recommendations?One of the most important stress tests is the verification of the input parameters of all interfaces of the device under test (DUT). This test is essential in ensuring the proper interop-erability of equipment from single and multi vendors.The synchronization to the incoming signal must first be checked before the more “physical” tests – such as sensitiv-ity to optical power – can be carried out. Here, an optical attenuator (OLA) is used to reduce the optical power until the threshold of the input receiver is reached (BER on the test unit). The optical power meter (OLP) displays the min-imum optical input power.

Figure 1: Check for line interface conformance with optical attenua-

tor (OLA) and optical power meter (OLP)

With variation of the signal offset, the maximum allowed clock deviation has to be checked. For 2.7G, 10.7G and 43 Gb/s interfaces this is defined with ± 20 ppm. During conformance testing, the maximum tolerable jitter (MTJ) of the input as well as the maximum allowed intrin-sic jitter of the outputs must both be verified. By performing these measurements the interface can be fully checked and detailed digital parameter tests can be initiated.

Does the DUT generate the correct response?Depending on signal input failures and degradation, the DUT will generate alarm responses in the up and down-stream direction to deliver information on the line quality to neighboring network elements.The OTN maintenance interaction shown in figure 3 illus-trates the coherence of alarm and error sources and sinks.

DUT2.7, 10.7 and43 Gb/s

OLPOLA

OTU-1, OTU-2,OTU-3

OTU-BDI

DUT

Insert alarm

LOF

OTU-AIS

Generation Detection

Optical channelTransport Unit

OTU

BIP-8

BEI

TIM

BDI

IAE

BIAE

OTU-AIS

Opticalchannel

OCh

AIS

LOM

LOF

LOS-P

Optical channelData Unit

ODU

AIS

BIP-8

BEI

TIM

BDI

OCI

PLMODU-AIS

SM-BIP-8SM-BEISM-TTISM-BDISM-IAESM-BIAEPM-BIP-8PM-BEIPM-TTIPM-BDIPM-STATPSI-PT

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 3

Verifying ITU-T conformance and interoperability The ITU-T G.798 standard defines the generation and detection criteria of certain alarm events (figure 4).

Figure 4: Verify ITU-T conformance

The thresholds are usually specified by a number of optical transport unit (OTU) frames such as the detection of sec-tion monitoring SM_BDI: SM_BDI bit = 1 in 5 consecutive OTU frames (table 1). Abbreviation Detection criteria according to G.709

and G.798OOF FAS (bytes 3, 4 and 5) are errored for ≥

5 framesLOF If OOF persists ≥ 3 msOOM MFAS numbers errored for ≥ 5 framesLOM If OOM persists ≥ 3 msOTUSM BEI SM byte 3, bits 1 to 4:

value 0 to 8: SM BIP-8 error countvalue 9 to 15: no SM BIP-8 errorsvalue 11: see SM BIAE

OTU-AIS PN-11 sequence (covers complete Och) ≥ 3 × 8192 bits

SM BDI SM byte 3 bit 5 = 1 ≥ 5 framesSM IAE SM byte 3 bit 6 = 1 ≥ 5 framesSM BIAE SM byte 3 bits 1 to 4 = “1011” ≥ 3 framesODU – PMPM BEI PM byte 3, bits 1 to 4:

value 0 to 8: PM BIP-8 error countvalue 9 to 15: no PM BIP-8 errors

ODU-AIS PM byte 3 bits 6 to 8 = “111” ≥ 3 framesODU-OCI PM byte 3 bits 6 to 8 = “110” ≥ 3 framesODU-LCK PM byte 3 bits 6 to 8 = “101” ≥ 3 framesPM BDI PM byte 3 bit 5 = 1 ≥ 5 framesODU – TCMTCMi BEI TCM byte 3, bits 1 to 4:

value 0 to 8: TCM BIP-8 error countvalue 9 to 15: no TCM BIP-8 errorsvalue 11: see TCM BIAE

TCMi-BDI TCM byte 3 bit 5 = 1 ≥ 5 framesTCMi-BIAE TCM byte 3 bits 1 to 4 = “1011” ≥ 3

frames

Table 1

The ONT-5xx simulates the alarms with a variable number of frames known as dynamic alarms which verify the detec-tion criteria of the DUT. A practical measurement such as the activation of SM BDI bit for 4 frames would cause no SM BDI alarm whereas activation of 5 frames would. Analysis of specific OH bytes is necessary to ensure interop-erability of equipment from different vendors. All major bytes need to be accessible to prove correct interpretation of the DUT.For chip designers it is very helpful to have the capabil-ity to “stress” dedicated overhead bytes. This is useful for example, when proper synchronization of MFAS has to be proved with different conditions or the reaction of DUTs to different patterns in FTFL or PSI sequence fields need to be checked.The ONT-5xx’s “Sequencer” provides the ideal tool for gen-erating byte stress sequences up to 256 frames.To identify the source and destination of a signal, the SM TTI is used with its SAPI and DAPI identification fields. Tandem connection monitoring (TCM) is used to check the cause of errors between different network providers. Interoperability is the key to securing this. The ONT-5xx is able to generate fully ASCII editable bytes and generate TTI mismatch alarms to perform a quick check of accurate matches in received and expected values.

Figure 5: Menu ONT-5xx: OTU overhead

DUT

Controller

2.7 Gb/s10.7 Gb/s43 Gb/s

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 4

Correct mapping and demapping of client signalsThe OTNs framing structure allows for the mapping of a variety of traffic types into OPUs including: SDH/SONET, ATM cells and Generic Frame Procedure (GFP) frames. The G.709 specifies guidelines for synchronous and asyn-chronous mapping. With asynchronous mapping, rate differences between the client and the OPU are adjusted through “stuffing”. To check the mapping capability of e.g. a 10/10.7G DUT, an input client signal of 10 Gb/s with varying offset (allowed deviation ± 20 ppm) is transmitted then mapped into the OPU by the DUT. The ONT-5xx is then able to detect whether the client has been properly mapped into the OPU without alarm or error.In checking the demapping, the ONT-5xx sends a 10.7 Gb/ s signal together with a mapped SDH/SONET client. The DUT demaps the client and sends the 10 Gb/s signal to the ONT-5xx. The ONT-5xx can then detect, if the client has been correctly demapped.To stress the DUT, the offset of the client can be varied above the specified limits.The two OTU-LAN bit rates mentioned above are not stan-dardized until now but are proprietary. Nevertheless these techniques are used very often. The idea behind this solu-tion is to map 10G Ethernet directly into an OTN frame. The standardized line rate for 10G Ethernet is 10.3125 Gb/s and therefore is slightly higher than the SDH/SONET line rate with 9,953 Gb/s. To compensate the higher speed the OTN wrapper gets overclocked. The resolving tests remain the same as for “normal” OTU-2.

Verification of correct FEC behaviorIf errors occur on an OTN line in any area of the frame, the receiver of the DUT is able to correct up to 8 symbol errors per subrow or to detect up to 16 symbol errors per subrow. In other words, it is able to correct 512 errors or to detect 1024 errors per optical channel (OCh) frame. In order to verify correct FEC testing, a varying number of error pat-terns are inserted in subrows of the transmitted signal then transmitted through an OTN DUT. The ONT-5xx there-fore generates correctable and uncorrectable FEC errors and as a stress test “maximum” FEC errors for correction by the DUT. As an additional stress test for the DUT the ONT-5xx is capable of generating special error patterns to stress every single FEC bit to the maximum amount of cor-rectable errors at different positions.At the receiving end, the optical channel (OCh) is checked to determine the error correcting capability of the DUT. If the number of inserted errors exceeds the correction

capability of the DUT, the ONT-5xx and DUT will reflect them as uncorrectable errors (figure 6).

Figure 6: Check for FEC behavior

As G.709 systems are still in the design and manufactur-ing phases, engineers often want to stress the DUTs with different types of FEC errors. The ONT-5xx provides a set of advanced FEC error insertion possibilities offering the user the flexibility to select which and how many rows and subrows should be affected. The number of errored bytes and their start positions in the subrow can also be selected. An editable byte error mask points to the bits to be errored in the byte thus allowing for the testing of almost any FEC error condition.

Figure 7: Menu ONT-5xx: Advanced FEC error insertion

For additional information about FEC testing, please refer to the appendix “Guide to FEC testing acc. to ITU-T rec. G.709” at the end of this document.

DUT

Controller

2.7 Gb/s10.7 Gb/s43 Gb/s

OH FEC

Errrors inOTN frame

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 5

SummaryTo verify OTN network elements to ITU-T recommenda-tions, the following should be performed:

1. Interface specification

• Synchronization to incoming signal (FAS)

• Optical power sensitivity

• Clock deviation

• Maximum tolerable jitter

• Intrinsic jitter (outputs)

2. Alarm/error response

3. ITU-T conformance and interoperability

• Dynamic alarms

• OH bytes

• Sequencer

• TTI mismatch

4. Mapping/demapping

• Client signal offset

• Duplex testing

5. FEC verification

• Correctable, uncorrectable, stress

• Advanced

Abbreviations

DAPI Destination Access Point Identifier

DUT Device under test

FEC Forward error correction

FTFL Fault Type Fault Location

LOF Loss of frame

MFAS Multiframe alignment signal

OCh Optical channel

OH Overhead

OLA Optical attenuator

OLP Optical power meter

OPU Optical channel Payload Unit

OTN Optical transport channel network

OTU Optical transport channel unit

OTU-AIS OTU alarm indication signal

OTU-BDI OTU backwards defect indication

PSI Payload Structure Identifier

SAPI Source Access Point Identifier

SM Section monitoring

SM TTI SM trail trace identifier

SM-BDI SM backwards defect indication

TCM Tandem connection monitoring

TTI Trail trace identifier

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 6

Appendix

Guide to FEC testing acc. to ITU-T rec. G.709 Guaranteeing correct FEC behavior

The ONT-5xx Optical Network Tester from JDSU delivers in-depth analysis of FEC algorithm implementation, analysis of FEC related parameters and has the most comprehensive FEC testing functionality on the market today. To better understand and apply the advantages enabled by this functionality, this appendix has been prepared to provide in depth information on the FEC manipulation capability of the ONT-5xx and the implemented FEC test functionality that helps users achieve reduced design and verification times for development and deployment of FEC systems.

The importance of FEC testing

FEC testing is essential for• Verifying correct implementation of the FEC algorithm in FEC encoders and decoders in an R&D environment

• Performing maximum stress testing of network elements (NE) with maximum number of possible errors. This is a requirement for example when performing system verification testing

• Validating correct installation (deployment and integration) of NEs and final installation tests

The benefits of ONT’s FEC testing capabilities

FEC_corr & FEC_uncorr: FEC_adv:

Simple, one-button click, FEC error insertion allows the installer to verify the FEC algorithm in the field. If failure occurs or improper operation detected in performing this straightforward test, further analysis (FEC_adv) is required.

This tool allows the user to perform detailed testing on a particular subset of all possible sections of the OTU-frame for errors.This is required for:• Verifying FEC encoder and decoder design• enabling the user to pinpoint failures or improper operation of the FEC algorithm design. This allows fast detection of poorly designed encoders and decoders used for the encoding/decoding of all 64 sub-rows.

FEC_stress:

A single button click, delivers clear PASS / FAIL criteria of the device under test (DUT).This maximum stress test inserts the maximum number of possible errors a DUT should still be able to correct entirely in accordance with ITU-T G.709 recommendations.The error pattern applied guarantees that every bit position in the frame is errored at least once.The test duration is 0.5/2/8 seconds for OTU-1/-2/-3.If failure occurs or improper operation is detected in performing this straightforward test, further analysis (FEC_adv) is required.

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 7

Implementation of FEC in ITU-T G.709The G.709 recommendation employs the Reed-Solomon code RS (255/239) which stipulates that 239 bytes be used as information bytes to calculate the FEC parity check of 16 bytes (255-239).An OTN frame consists of 4 OTU-rows. An OTU-row is split into 16 sub-rows (code words) each consisting of 255 bytes. The sub-rows are formed byte interleaved, which means that the first sub-row contains the first OH byte, the first payload byte and the first FEC byte. The FEC byte of each sub-row is inserted into byte position 240. This is true for all 16 sub-rows. Figure A-1 illustrates this process. The Reed-Solomon code is capable of detecting 16 byte (symbol) errors or correcting up to 8 byte errors in a sub-row.In order to explain the various FEC insertion methods the ONT-5xx offers, a matrix is created as illustrated in figure A-2.

FEC functionality of the ONT-5xx OTN moduleThe FEC error generation and detection capability of the ONT can be divided into two significant areas: pre-defined testing of FEC functionality (FEC_correctable, FEC uncor-rectable and FEC_stress), and user-defined (expert) testing (FEC_advanced).

FEC_correctable error insertionAs the error description suggests, when inserting FEC_corr errors, the DUT should still be capable of correcting these errors. This is a simple test used by field engineers in carry-ing out initial inspections to verify the correct installation of the NEs.In this case, the ONT-5xx displays no error reading as the DUT should correct the inserted FEC errors.The implementation in the ONT is performed by inserting errors in the first sub-row of the first OTU-row as illus-trated in the figure A-3. Given that the RS code is capable of correcting up to 8 symbol errors in a sub-row, exactly 8 bytes are errored in the dedicated sub-row. The byte inver-sion is implemented from byte position 240 to 247 of the sub-row shown in the figure A-3.

Figure A-1: OTN frame

Figure A-2: Matrix illustrating the 4 OTU rows and all 16 sub-rows for

each OUT row

Why insert the errors in the FEC section of the OTU-frame?

The position for the 8 byte inversions is selected on the basis that should the FEC decoder be unable to correct the errors, the original payload can still be made completely available given that the errors are only inserted in the FEC section of the OTU-frame.

Why insert errors in first sub-row of first OTU-row?

Assuming that 16 encoders are used for all OTU-rows in the implementation of FEC, it would be sufficient to test only one encoder in an OTU-row. This is due to the fact that all encoders for the sub-rows should have the same design and should also have been subjected to maximum stress testing prior to installation.

FEC_uncorrectable error insertionIt is also a requirement to test the maximum number of errors a DUT is able to detect. Here, it is not possible for the errors to be corrected by the DUT. The necessity to perform this test feature is identical to that previously mentioned for the FEC_corr feature.When inserting the FEC_uncorr error, alarms by the DUT can be expected when the DUT is operating correctly.In performing this test, 16 bytes are inverted in the first sub-row of the first OTU-row. This is similar to the byte inversion for the correctable errors, with the exception that all 16 bytes (240 to 255) of the sub-row are inverted.

FEC

FEC

FEC

Payload

Payload

Payload

OH

OH

OH

OH

16 sub-row

2 sub-row

2 sub-row

1

1

1

16

16

17

17

32 3824

3824

3825

3825

4080

408012

34

11

3 4 5 6 7 8 9 10 11 12 13 14 15 16

3

4

2

2

1 239 240 255

Information bytes Parity check

Sub-rows

OTU-rows

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 8

FEC_stress testThis functionality allows the user to acquire a PASS / FAIL criteria of the DUTs capability to correct up to 8 symbol errors.In this case, the ONT-5xx inserts the maximum number of possible byte (symbol) errors which the DUT should still be capable of correcting. In other words, the system is stressed to its maximum. This test inserts errors over the entire OTU frame.A graphical representation of a sub-row is used to describe in detail error insertion when using FEC (figure A-5).Performing the maximum stress test ensures that the fol-lowing test conditions are met:• all combinations of byte error masks will be used

during error insertion

• a maximum of 8 symbol errors are inserted in each sub-row (figure A-5)

• all 16 sub-rows of all 4 OTU-rows will be errored .

• all possible byte positions of the whole OTU-frame will contain errors

In order to guarantee that all the bytes of the OTU-frame are errored at least once, the following parameters are deter-mined internally:• Starting position of error insertion

The starting position of the error insertion is defined from the time the insertion button is pressed

• Determination of byte error mask Random generation of all possible bit combinations between 0x01 and 0xFF determines which bit in a byte is inverted. This could be for example the following mask: F3 03 A1 B7 7B 04 AB 32, which specifies the position of inversion in the 8 individual errored bytes. This error mask changes continuously resulting in a random sequence of generated symbol errors.

Figure A-3: Insertion of errors in the first sub-row of the first OTU row

Figure A-4: FEC _uncorrectable error insertion

• Distribution of errored positions Once the starting position of the first 8 symbol errors is determined, the position of the following 8 byte errors are distributed throughout the whole OTU-frame. This guarantees a pseudo-random distribution of errors over the entire OTU frame.

This test setup guarantees that after approximately 0.3/2/8s of FEC error insertion, every byte in the OTU-1/-2/-3 frame is errored at least once. Should the DUT behave correctly under maximum stress test conditions it should be able to correct all errors. The return signal generated toward the ONT-5xx should as a result be free from errors. However, when the ONT-5xx receives errors from the DUT, further testing is necessary using the ONT-5xx’s FEC_advanced functionality.

FEC_advanced error insertionThe FEC_advanced functionality implemented in the ONT allows a “microscopic” view of implementation of the FEC algorithm.FEC_adv is used in:• R&D when the FEC algorithm is being designed and

verified

• Allowing quick pin pointing of failures inside encoder and decoder designs FEC_stress is used to test the limit of the DUTs correction capabilities

FEC_advanced is capable of testing below and beyond these limits. To be more specific, it enables the user to define exactly which bit in a particular byte of an OTU-row and sub-row should be errored.As previously mentioned, the FEC_adv functionality helps to define which bit should be errored and where in the OTU-frame.The graph in figure A-6 shows the parameters that can be specified in the FEC_adv. feature.This implemented feature makes it possible to choose the following parameters:• Selection of row

• Selection of sub-row

• Starting position of burst in the sub-row

• Number of errored bytes per sub-row

• Specify which bit should be inverted in the selected bytes

A possible scenario for testing the limit and beyond could be:• Select all 4 OTU rows by choosing for example, 1111

• Select first sub-row, for example, 0000 0000 0000 0001, which means that the first sub-row will be errored in all the OTU-rows

11

3 4 5 6 7 8 9 10 11 12 13 14 15 16

3

4

2

2

1 239 240 255 Error insertion

11

3 4 5 6 7 8 9 10 11 12 13 14 15 16

3

4

2

2

1 239 240 255 Error insertion

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 9

• By selecting the number of errored bytes, the correction capability limit and beyond can be tested. When selecting 8 bytes, the DUT must be able to correct the errors. However, when inserting 9 bytes, the DUT must respond with errors. The selection of the starting position allows the user to specify particular parts of the sub-row to be tested. For example, sections of the FEC part can be errored to put focus on the FEC functionality

• The last parameter specifies the specific bits inverted in the bytes selected within the sub-row parameter. This is a requirement when testing particular sequences of the FEC encoder and decoder on a bit basis.

With careful selection of these parameters, each individual byte can be errored and the resulting behavior be tested.

Figure A-5: Sub-row illustrating detail error insertion using FEC

Figure A-6: Parameters for specification in FEC_adv feature

1 239 240 255

8 symbols }

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 10

What to expect when using the various FEC functionalitiesTx error insertion type Rx response at ONT-5xx after DUT.

Note: FEC evaluation and correction can be turn on/off separately

FEC_correctable Rx eval off: No errors Rx eval on: No errors

FEC_uncorrectable Rx eval off: No errorsRx eval on: The ONT-5xx displays count, ratio and seconds of uncorrectable errors in the case of no new FEC being calculated by the DUT

FEC_maximum (stress test) Rx eval off: No errorsRx eval on: No errors

FEC_advanced Rx eval off: No errorsRx eval on: • No errors when testing the limit of the DUT (see FEC_max testing)• When testing beyond the limit: The received signal at the ONT-5xx is dependent on the configuration of the DUT (e.g. calculation of new FEC, generation of alarms) and the specified insertion position (payload section or FEC section) of the error in the OTU-frame

SummaryThe ONT-5xxs FEC functionality provides the user with in-depth FEC testing making the instrument suitable for use in early development stages, during verification stages, as well as in the installation and maintenance of FEC systems.The ONT-5xx is the only test solution on the market that delivers this level of FEC testing together with simple, one-button, stress testing functionality.

AbbreviationsDUT Device Under TestFEC Forward Error CorrectionFEC_adv FEC_advancedFEC_corr FEC_correctableFEC_stress FEC_stressFEC_uncorr FEC_uncorrectableNE Network ElementOTU Optical channel Transport Unit

Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 11

JDSU ONT-5xx Optical Network Tester – the right solution for G.709 testingThe ONT-5xx combines optical and digital testing in a single unit, making it a com-plete solution for both optical layer and performance testing. Featuring a modular design, the ONT-5xx allows easy upgrades, powerful software and remote web-based monitoring. The ONT-5xx measures all optical bit rates up to 43 Gb/s, making it the most complete digital and optical DWDM solution. When these capabilities are com-bined with the ONT-5xx’s powerful optical spectrum analyzer (OSA), engineers and network operators can perform all tests required during optical system verification and maintenance and optical component verification.

ONT-5xx Highlights:

• Multi-application platform for OTU-1, OTU-2, OTU-3, NewGen SDH/SONET, Ethernet, OSA

• Multi-port capability for simultaneous and independent use of different modules

• Multi-user functionality for several users at one machine at a time.

• Multi-channel application for simultaneous evaluation of thousands of SDH/SONET channels

• High-accurate jitter measurement according to ITU-T O.172 appendices VII & VIII

• Full remote capabilities with Tcl/TK, C- and LabWindows driver libraries

• Common, intuitive graphical browser user interface

JDSU 40/43G solutionThe JDSU ONT-5xx enables evaluation and characterization of 40/43 Gb/s electrical/optical devices. The ONT supports unframed BER testing, and framed SDH/SONET/OTN functional testing including jitter/wander generation and analysis. The modular concept starts with 3 slots for 40 Gb/s optical framed and unframed. Further modules can be added to enable electrical interfaces and jitter/wander applications. In addition, the programmable hardware architecture allows to add a payload module for the com-bined OTN with SDH/SONET client testing and to assure the future-proof for further applications.

Related productONT-50 Optical Network TesterPortable desktop solution for testing of design and conformance of Next Generation transport networks. SDH/SONET, OTU-1, OTU-2, Jitter, NewGen, Ethernet. Mul-tiple users can run multiple applications simultaneously and independently. VxWorks operating system. High resolution 12” colored touchscreen, 4 slots.

For further information on the ONT-50/-5xx solution, refer to: www.jdsu.com/ont.

All statements, technical information and recommendations related to the products herein are based upon informa-tion believed to be reliable or accurate. However, the accuracy or completeness thereof is not guaranteed, and no responsibility is assumed for any inaccuracies. The user assumes all risks and liability whatsoever in connection with the use of a product or its applications. JDSU reserves the right to change at any time without notice the design, specifications, function, fit or form of its products described herein, including withdrawal at any time of a product offered for sale herein. JDSU makes no representations that the products herein are free from any intellectual property claims of others. Please contact JDSU for more information. JDSU and the JDSU logo are trademarks of JDS Uniphase Corporation. Other trademarks are the property of their respective holders. © 2006 JDS Uniphase Corporation. All rights reserved. 30137344 501 0906 FEC.AN.OPT.TM.AE

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Application Note: Running OTN FEC Systems to ITU-T G.709 Standard 12