Rohan_Reddy_NCState
1
Rohan Rajeshwar Reddy 919-931-7595 • [email protected] • www.linkedin.com/in/reddyrohan93 OBJECTIVE Seeking Full-Time opportunities starting January 2017 in Design Verification PROFESSIONAL EXPERIENCE Cirrus Logic – Design Verification Intern , Austin Summer 2016 • Worked on verification of pad interface of the DSP chip • Followed the verification flow, from Design/Verification Requirements to Sequence items, Sequence Configuration, Interfaces, Assertions, Tests, Code and Functional Coverage, Gate level Simulations as a part of my verification plan • Was involved in improving the functional coverage numbers and also fixed gate level simulation failures by modifying the test case flow EDUCATION North Carolina State University, Raleigh, North Carolina 3.78 /4.0 Master of Science in Computer Engineering Anticipated: Dec 2016 University of Mumbai, Maharashtra, India 71% - First Class Graduate Bachelor of Engineering in Electronics and Telecommunication May 2014 Relevant Coursework: ASIC Verification, ASIC Design, Computer Architecture, Advanced GPGPU Architecture, Architecture of Parallel Computers, Compilers Optimization and Scheduling, VLSI System Design, Internet Protocols, Discrete Time Signal Processing, Computer Networks. Certifications: Digital System Design using HDL (Mar 2015 - May 2015), Diploma in Embedded System (Jan 2015 - May 2015) Languages: SystemVerilog, Verilog, C++, Python, CUDA Tools: Modelsim, Questasim, Calibre, Synopsys Design Compiler, HSPICE, Xilinx ISE, Matlab, SciLab PROJECTS LC3 Microcontroller Data path and Control path Verification Mar 2015 to May 2015 • Verified the data-path and the control-path of a fully pipelined LC3 Microcontroller using SystemVerilog • Developed a reusable and layered test-bench, drove the DUT and the golden model with fully constrained random inputs and enabled coverage feedback. Implemented assertion points to verify the identified corner cases and specific critical blocks • This included implementation of interfaces, inter-process communication, multi-threading and probing signals from DUT Hardware Accelerator for Bellman Ford Algorithm. (Verilog HDL) Sept 2015 to Dec 2015 • Designed a synthesizable digital ASIC in Verilog for computing shortest path from a source vertex to all of the other vertices in a weighted digraph. It also detects the presence of negative cycle, if any, in the digraph • The design is capable of handling graphs with negative edge weights, and up to 128 nodes. Performance optimizations such as pipelining, register level bypassing were used to improve performance i.e. product of area, frequency Simultaneous Branch and Warp Interweaving in GPGPU Feb 2015 to May 2015 • GPU performance gets affected due to divergence problems. Stack based reconvergence system does not allow parallel execution of branches • Simultaneous warp interviewing technique was implemented to overcome the idle SIMD lanes problem caused by divergence Out-of-Order Superscalar Processor Simulator Nov 2015 to Dec 2015 • Developed a simulator for an out-of-order superscalar processor that fetches and issues configurable number of instructions per cycle • Issue Queue (IQ) size and Reorder Buffer (ROB) size is configurable. Modelled timing information of every instruction in each pipeline stage • Implementation in C++ and processor performance (Instructions Per Cycle) was studied by varying Issue size, Reorder Buffer size Cache and Memory Hierarchy Simulator Sept 2015 to Oct 2015 • Design and Development of a cache simulator which can simulate hierarchies of memory in a CPU • Simulator is able to simulate only L1,L1 with victim,L1-L2 and L1-Victim-L2 configurations with configurable parameters • Simulator uses ‘Least-Recently-Used(LRU)’ replacement policy and Write-back Write-allocate(WBWA) write policy for cache operations Multiprocessor and Multi-level Cache Simulator with Cache Coherence Oct 2015 to Nov 2015 • Implemented Cache coherence protocols MSI, MESI and DRAGON for variable number of processors in C++ • The simulator tracks various performance counters like flushes, writebacks, cache to cache transfers 128-bit Synchronous SRAM Mar 2016 to May 2016 • Built the layout in 15nm FinFet process with clean DRC and LVS checks. The design had a 6T bitcell along with TSPC flipflops and equalisers Parallelize Sequential Code using OpenMP directives Sept 2015 to Oct 2015 • Parallelized various statistical computation algorithms with OpenMP directives and compared the performance of code with its sequential counterpart Branch Predictors Oct 2015 to Nov 2015 • Implemented trace driven bimodal, gshare and hybrid branch predictor simulators in C++ MIPS 32bit single cycle processor with 21 instructions (Verilog HDL) May 2015 to June 2015 • The processor’s ALU was implemented using a 32bit Carry Look Ahead Adder PUBLICATION SUV detection algorithm for speech signals in IJARCSSE (ISSN: 2278-9359)
-
Upload
rohan-reddy -
Category
Documents
-
view
18 -
download
2
Transcript of Rohan_Reddy_NCState
Rohan Rajeshwar Reddy
919-931-7595 • [email protected] • www.linkedin.com/in/reddyrohan93
OBJECTIVE
Seeking Full-Time opportunities starting January 2017 in Design Verification
PROFESSIONAL EXPERIENCE
Cirrus Logic – Design Verification Intern , Austin Summer 2016 • Worked on verification of pad interface of the DSP chip • Followed the verification flow, from Design/Verification Requirements to Sequence items, Sequence Configuration, Interfaces, Assertions, Tests,
Code and Functional Coverage, Gate level Simulations as a part of my verification plan • Was involved in improving the functional coverage numbers and also fixed gate level simulation failures by modifying the test case flow
EDUCATION
North Carolina State University, Raleigh, North Carolina 3.78 /4.0 Master of Science in Computer Engineering Anticipated: Dec 2016
University of Mumbai, Maharashtra, India 71% - First Class Graduate Bachelor of Engineering in Electronics and Telecommunication May 2014
Relevant Coursework: ASIC Verification, ASIC Design, Computer Architecture, Advanced GPGPU Architecture, Architecture of Parallel Computers, Compilers Optimization and Scheduling, VLSI System Design, Internet Protocols, Discrete Time Signal Processing, Computer Networks.
Certifications: Digital System Design using HDL (Mar 2015 - May 2015), Diploma in Embedded System (Jan 2015 - May 2015) Languages: SystemVerilog, Verilog, C++, Python, CUDA Tools: Modelsim, Questasim, Calibre, Synopsys Design Compiler, HSPICE, Xilinx ISE, Matlab, SciLab
PROJECTS
LC3 Microcontroller Data path and Control path Verification Mar 2015 to May 2015 • Verified the data-path and the control-path of a fully pipelined LC3 Microcontroller using SystemVerilog • Developed a reusable and layered test-bench, drove the DUT and the golden model with fully constrained random inputs and enabled coverage
feedback. Implemented assertion points to verify the identified corner cases and specific critical blocks • This included implementation of interfaces, inter-process communication, multi-threading and probing signals from DUT Hardware Accelerator for Bellman Ford Algorithm. (Verilog HDL) Sept 2015 to Dec 2015 • Designed a synthesizable digital ASIC in Verilog for computing shortest path from a source vertex to all of the other vertices in a weighted digraph.
It also detects the presence of negative cycle, if any, in the digraph • The design is capable of handling graphs with negative edge weights, and up to 128 nodes. Performance optimizations such as pipelining, register
level bypassing were used to improve performance i.e. product of area, frequency Simultaneous Branch and Warp Interweaving in GPGPU Feb 2015 to May 2015 • GPU performance gets affected due to divergence problems. Stack based reconvergence system does not allow parallel execution of branches • Simultaneous warp interviewing technique was implemented to overcome the idle SIMD lanes problem caused by divergence Out-of-Order Superscalar Processor Simulator Nov 2015 to Dec 2015 • Developed a simulator for an out-of-order superscalar processor that fetches and issues configurable number of instructions per cycle • Issue Queue (IQ) size and Reorder Buffer (ROB) size is configurable. Modelled timing information of every instruction in each pipeline stage • Implementation in C++ and processor performance (Instructions Per Cycle) was studied by varying Issue size, Reorder Buffer size Cache and Memory Hierarchy Simulator Sept 2015 to Oct 2015 • Design and Development of a cache simulator which can simulate hierarchies of memory in a CPU • Simulator is able to simulate only L1,L1 with victim,L1-L2 and L1-Victim-L2 configurations with configurable parameters • Simulator uses ‘Least-Recently-Used(LRU)’ replacement policy and Write-back Write-allocate(WBWA) write policy for cache operations Multiprocessor and Multi-level Cache Simulator with Cache Coherence Oct 2015 to Nov 2015 • Implemented Cache coherence protocols MSI, MESI and DRAGON for variable number of processors in C++ • The simulator tracks various performance counters like flushes, writebacks, cache to cache transfers 128-bit Synchronous SRAM Mar 2016 to May 2016 • Built the layout in 15nm FinFet process with clean DRC and LVS checks. The design had a 6T bitcell along with TSPC flipflops and equalisers Parallelize Sequential Code using OpenMP directives Sept 2015 to Oct 2015 • Parallelized various statistical computation algorithms with OpenMP directives and compared the performance of code with its sequential counterpart Branch Predictors Oct 2015 to Nov 2015 • Implemented trace driven bimodal, gshare and hybrid branch predictor simulators in C++ MIPS 32bit single cycle processor with 21 instructions (Verilog HDL) May 2015 to June 2015 • The processor’s ALU was implemented using a 32bit Carry Look Ahead Adder
PUBLICATION
SUV detection algorithm for speech signals in IJARCSSE (ISSN: 2278-9359)
