Reversible Logic
6
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 321 Design of sequential circuit using reversible logic Prashant R. Yelekar Department of Electronics & Telecommunications, Yeshwantrao Chavan College of Engineering, Nagpur, India [email protected] Abstract- The reversible logic design in today's era is attracting more interest due to its low power consumption. Reversible logic has g r o w i n g importantance in low- power circuit design and high processing com puting. This paper provides synthesizing reversible counter which is the new approach in designing four bit reversible asynchronous sequential circuit. This paper also proposed a reversible D flip- flop and Tflip-op. The important reversible gates used for reversible logic synthesis are Feynman gate, Fredkin gate, TSG gate and sayem gate etc. This p a p e r presents a basic reversible gate to build more complicated circuits. The transistorized implementation of reversible gate presented in this paper are completely reversible in nature i.e. it can perform both foard and backward computation. Keywords- Low-power VLSJ, Low-power CMOS design, reversible logic, reversible counters. I. INTRODUCTION Energy loss is an important consideration in digital circuit design, also known as circuit synthesis. Part of the problem of energy dissipation is related to technological non- ideality of switches and materials. Higher levels of integration and the use of new fabrication processes have dramatically reduced the heat loss over the last decades. Reversible logic has received eat attention in e recent years due to their ability to reduce the w dissipation which is the main requirement in low power VLSI desi. It has wide applications in low power CMOS and Optical information processing, quantum computation and nanotechnology. Irreversible hardware computation results in energy dissipation due to information loss. According to Landauer research, the amount of energy d i s s i p a t e d for e v e r y irrepressible bit Operation is at least KTln2 joules, where K=1.3S06505*10 23 m 2 kg 2 K l Uoule/Kelvin -l ) is the Boltzmann's constant and T is the temperature at which n is performed [1]. In 1973, Bennett showed that KTln2 energy would not dissipate from a system as long as the allows the reproduction 0 f the in put s from 0 b s e r v e d 0 u t p u t s [ 2]. Energy dissipation can be reduced or even eliminated if computation becomes Information-lossless Reversible logic supports the process of Prof. Sujata S. Chiwande Department of Electronics & Telecommunications, Yeshwantrao Chavan College of Engineering, Nagpur, India Su jata _ [email protected] running the system both forward and backward. This means that reversible computations can generate inputs from outputs and can stop and go back to any point in the computation history. II. THE CONCEPT Reversibility in computing implies that no information about the computational states can ever be lost, so we can recover any earlier stage by computing backwards or computing the results. This is termed as logical reversibility. The benefits of logical reversibility can be gained only aſter employing ysi reversibility. Physical reversibility is a process that dissipates no energy to heat. Absolutely perfect physical reversibility is practically unachievable. Computing systems give off heat when voltage levels change from positive to negative: bits from zero to one. Most of the energy needed to make that change is given off in the form of heat. Ratherthan changing voltages to new levels, reversible circuit elements will adually move charge from one node to the next. This way, one can only expect to lose a minute amount of energy on each transition. Reversible computing y affects digital logic desis. Reversible logic elements are needed to recover the state of inps from the outputs. It will impact instruction sets and high-level programming languages as well. Eventually, these will also ve to be reversible to provide optimal efficiency. III. NEED OF REVERSffiLE COMPUTING Reversible computing provide Reliable and low power design, high performance circuits synchronous with speed and processing power. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away, will soon offer the only physically possible way to keep improving performance. It again Improve computational efficiency this can be done by building circuits which reduce energy from state will save energy. Reversible computing will also lead to improvement in energy efficiency. It Increase portability of device to reduce element size to atomic size. It has incurred more hardware cost, but power cost and performance are dominant ISBN: 978-S1-909042-2-3 ©2012 IEEE
description
Reversible Logic IEEE for Sequential Counters
Transcript of Reversible Logic
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 321
Design of sequential circuit using reversible logic
Prashant R. Yelekar Department of Electronics & Telecommunications,
Yeshwantrao Chavan College of Engineering, Nagpur, India
Abstract- The reversible logic design in today's era is
attracting more interest due to its low power consumption.
Reversible logic h a s g r o w i n g importantance in low
power circuit design and high processing com puting. This
paper provides synthesizing reversible counter which is the new
approach in designing four bit reversible asynchronous
sequential circuit. This paper also proposed a reversible D flip
flop and Tflip-f1op. The important reversible gates used for
reversible logic synthesis a r e Feynman gate, Fr edkin g a t e ,
TSG gate and sayem gate etc. This p a p e r presents a basic
reversible gate to build more complicated circuits. The
transistorized implementation of reversible gate presented in this
paper are completely reversible in nature i.e. it can perform both
fonvard and backward computation.
Keywords- Low-power VLSJ, Low-power CMOS design, reversible logic, reversible counters.
I. INTRODUCTION
Energy loss is an important consideration in digital circuit design, also known as circuit synthesis. Part of the problem of energy dissipation is related to technological non- ideality of switches and materials. Higher levels of integration and the use of new fabrication processes have dramatically reduced the heat loss over the last decades. Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. It has wide applications in low power CMOS and Optical information processing, quantum computation and nanotechnology. Irreversible hardware computation results in energy dissipation due to information loss . According to Landauer research, the amount of energy d i s s i p a t e d for e v e r y irrepressible bit Operation is at least KTln2 joules, where
K=1.3S06505* 1023m2kg2K lUoule/Kelvin-l) is the Boltzmann's constant and T is the temperature at which operation is performed [1]. In 1973, Bennett showed that KTln2 energy would not dissipate from a system as long as the system allows the reproduction 0 f t h e i n p u t s from 0 b s e r v e d 0 u t p u t s [ 2]. Energy dissipation can be reduced or even eliminated if computation becomes Information-lossless Reversible logic supports the process of
Prof. Sujata S. Chiwande Department of Electronics & Telecommunications,
Yeshwantrao Chavan College of Engineering, Nagpur, India
Su jata _ [email protected]
running the system both forward and backward. This means that reversible computations can generate inputs from outputs and can stop and go back to any point in the computation history.
II. THE CONCEPT
Reversibility in computing implies that no information about the computational states can ever be lost, so we can recover any earlier stage by computing backwards or lDl-computing the results. This is termed as logical reversibility. The benefits of logical reversibility can be gained only after employing physical reversibility. Physical reversibility is a process that dissipates no energy to heat. Absolutely perfect physical reversibility is practically unachievable. Computing systems give off heat when voltage levels change from positive to negative: bits from zero to one. Most of the energy needed to make that change i s g i v e n o f f i n t h e form o f hea t . Rather t h a n changing voltages to new levels, reversible circuit elements will gradually move charge from one node to the next. This way, one can only expect to lose a minute amount of energy on each transition. Reversible computing strongly affects digital logic designs. Reversible logic elements are needed to recover the state of inputs from the outputs. It will impact instruction sets and high-level programming languages as well. Eventually, these will also have to be reversible to provide optimal efficiency.
III. NEED OF REVERSffiLE COMPUTING
Reversible computing provide Reliable and low power design, high performance circuits synchronous with
speed and processing power. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away, will soon offer the only physically possible way to keep improving performance. It again
Improve computational efficiency this can be done by building circuits which reduce energy from state will save energy. Reversible computing will also lead to improvement in energy efficiency. It Increase portability of device to
reduce element size to atomic size. It has incurred more hardware cost, but power cost and performance are dominant
ISBN: 978-S1-909042-2-3 ©2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 322
than hardware cost. Hence need of reversible computing
cannot be ignored in computing era,
Some factor regarding reversible logic are given below
The number of garbage outputs (GO): This refers to the number of unused outputs p-esent in a reversible logic circuit. One cannot avoid the garbage outputs as these are very essential to achieve reversibility.
• Quantum cost (QC): This refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1 * 1 or 2*2) required to
realize the circuit. of reversible gates used in circuit.
• The number of constant inputs (CI): This refers to the number of inputs that are to be maintained constant at either 0 or 1 in order to synthesize the given logical function
IV. REVERSIBLE LOGIC GATES
A reversible logic gate has equal number of input and output terminals and there is one to one mapping between them. again we can say, gate is reversible if we can determine input vector from output vector and vice-versa.revrsible gate should practically loose very little amount of energy. Fan-out is not allowed in reversible circuits however fan-out can be achieved using additional gate. In this paper we have discuss basic reversible gate like Feynman gate, fredkin gate, TSG gate and Sayem gate Which we have used in implementing reversible sequential circuits.
A. FEYNMAN GATE
Feynman gate is a 2*2 one through reversible gate
as shown in figure l. The input vector is I(A, B) and the
output vector is O(P, Q). The outputs are defined by P=A,
Q=A B. Quantum cost of a Feynman gate is l. Feynman
Gate (FG) can be used as a copying gate. Since a fan-out
is not allowed in reversible logic, this gate is useful for
duplication of the required outputs.
A
B
Feynman gate
Figure I: Feynman gate
P=A
Q=AEi7B
i) TRANSiSTOR iMPLEMENTATiON Figure 2 shows the transistor implementation of the
Feynman gate. The transistor implementation is fully reversible, that is, the given circuit can also work for forward as well as reverse operation.
Figure 2: Reversible Transistor Implementation of the Feynman gate
As shown in design in Fig.2, only four transistors are needed to design the fully reversible Feynman gate.
B. FREDKlN GATE
Figure 3 shows a 3*3 Fredkin gate. The input vector is I (A, B, C) and the output vector is 0 (P, Q, R). The output is
defined by P=A, Q=A'B EB AC and R=A'C EB AB. Quantum cost of a Fredkin gate is 5
A -
B -F REDKIN
GATE
r- P=A
c - r R=A'C AlB
Figure 3: Fredkin gate
i) TRANSISTOR iMPLEMENTATION Figure 4 shows the transistor implementation of the
Fredkin Gate that need only four transistors. In the implementation, the output P is directly taken from input A as output P is same as input A. The proposed transistor implementation is suitable both for forward as well as backward computation, i.e., completely reversible in nature. The forward and backward computations for Fredkin gate are explained below.
o
cD-.-t--+----!;
Figure 4: Transistor Implementation of Fredkin Gate
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C. TSG GATE
Fig 5 shows a 4*4 TSG gate. The input vector is I (A, B, C, D) and the output vector is 0 (P, Q, R, S). The output is
defined by P = A, Q = A'C'EBB', R = (A'C'EBB')EB D and S =
(A'C'EBB').DEB (ABEBC) The proposed TSG gate is capable of implementing all Boolean functions and can also work singly as a reversible Full adder as shown in figure 6
1)
A P A
B--SG Gle - Q=A'C'(I)B'
C R (A'C'(I) B') $D 0- --- 5 (A'C'@ B').D$(AS$C )
Figure 5: TSG gate
A-
B
0-
TSG Gate
P=A
Q= AEDB
R = AED BED c. .. = sum
S -C A ED B ) c,,,EJ)o.:a - Cout
Figure 6: TSG Gate Working As Reversible Full Adder
TRANSISTOR IMPLEMENTATION The transistorized implementation of TSG gate is as
shown in figure
Figure 7: Transistor Implementation of TSG Gate
D. SAYEM GATE
Sayem gate (SG) is a 1 trough 4x4 reversible gate. The input and output vector of this gate are, Iv = (A,
B, C, D) and Ov = (A, A'B EB AC, A'B EB ACEB D, AB EB
A'C EB D). The block diagram of this gate is shown in Fig 8. The sayem gate can be used to build reversible T flipflop along with Feynman gate.
A A A'BffiAC B SG A'B ffi AC ffi D C
D AB ffi A'Cffi D
Figure 8: Sayem gate
I) TRANSISTOR IMPLEMENTATION Transistorized implementation of sayem gate (SG) is
shown in figure. The sayem gate is extension of Feynman gate. The implementation of sayem gate requires four transistors with two buffers and two Feynman (FG) gate as shown in figure. The buffer is introduced so as maintain proper voltage level. The given implementation is completely reversible i.e. it works for both forward and backward computation.
EIj------�------------�
r .... u' U� . .
Figure 9: Transistor Implementation of Sayem Gate
E. LATCHES
Here we can use D-Latch or T-Latch depending upon choice that can be used in implementing reversible sequential circuit (counter)
I) D-LATCH The D flip-flop is a circuit that needs only a single
input and clock pulses. The action of the D flip-flop is straightforward. When the clock pulse transitions from low to high, the value of D is transferred to Q. The characteristic equation of D-Latch is Q+ =DE+E'Q. Realization can be done using single SG gat by giving E, Q, D and 0 respectively in 1st, 2nd, 3rd and 4th input of SG. Fig lO(a) shows the design
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of D-Latch with only Q output and Fig 10(b) shows the design of reversible D-Latch with both the output present Q and next Q+ .One FG is needed to copy and produce the complement of Q from SG for the design of Fig lOeb)
E
SG D -
0_ - g2
g, Q Q
Fig IO(a): Proposed design of D-Latch with only output Q
E----t
D
o
SG
Fig I O(b): Proposed design of D-Latch with output Q and Q+
2) T-Flip Flop As the name suggests, this flip-flop circuit used to
toggle the output when input is high (1) and retains the output when input is low (0), thus it does two operation, it either holds the last state or toggles the output. Essentially, it has a logical symmetry with Controlled NOT kind operation.
Table I: Truth table of T flip-flop
The reversible realization of T Flip-flop has two SG gates and one Feynman Gate is shown in fig 11 [6].
r.:;-----;:-l----r:---:l.. "c'
"1---, "
Fig II: Reversible Positive Edge Triggered T Flip-flop
-n=Q CP Q'
Figure 12: reversible T flip flop
F FOUR BfT ASYNCHRONOUS UP/DOWN COUNTER
The implementation of reversible asynchronous Up/Down Counter is shown in Fig. 13 [6]. The Up/Down operation of this reversible circuits is controlled by the control input UP/DOWN. For UP operation, the control input should be 1 and for down operation, the control input should be O.
c,w Fuh.
Cowluilf
imrilli JI1i)4I�
Q
Ql
IJ,�r! ....... __ -+_--1 ___ +-_...1.... __ -+ __ -"
UI : OOUX ---.....I-----...I....------I Figure 13: Four-bit Reversible Asynchronous Up/Down
Counter
V. SIMULATION ANALYSIS
Simulation is based on "TANNER TOOL V13".model file used is "0.35J.!"technology file. Graph presented below are input and output signal at respective input and output terminal at each gate.
f) FEYNMAN GATE
: -r�-�T--:-:--- -----+---------1----- -----:� -- -- +---- i----- i p � -r-----r------- --------r------ - ----- ----- ,---------------
r------i---------r-------l
T-- ----r- - --- -------r---- - -------T------ --------T------,------T------T � .. T--------r-------- - ---------r--------- --------
T------- --------r-----T-------r-----T
t :� r:;_::::I-=::�·�·::]�_:::_L.::L_ _ _ _ _ _ J=r=I __ �J u __ 1 ________ 1____________ _ _________ I __ _ ___ .L __ _____ _ L _______ __ _ _ _ __ 1.. ______ L ________ .1 _________ 1 ___________ L __________ L _________ L _______ ,
·
.... "-
:: :;::::;:::::-
------------I--------- 1:::=:r= := ----1 ----- ::::::=:r:=�p;;. .. -"1"---------)"----------- -----------1---------- -----------1----- ----- -----------l----------l .. -r----- ----,------------ --- --------1""----------- ---------l----- -------r----1-
i ::r:-�=:_l-=-:::- ��- :; -----r----- ----l-----�---r::=-i .. T-----------r--------- -------T--------- ---- ----r------- ------T-----T .. "[-----r---- ----T------ -----r---- ---- -"[-----T :: T-- --r---- -----T---=:-T::=-:::- __ ---T---,:
·
....
:: ;---�-�------:-;-----t-----------'-----1----1-----------:�-----i-F-•• -r--- --·-----l---·-------- 1-- ---- -r ,,---- ------ 1 -. -.- r----- -1 1 1 " r--- ------r----------r-----·--r- -
- ------- r---- - r------T - T---- T � u --r--------T------------r---------r------------ --------T-- -----r-------r---------------T------1" ; " r--- -----T --- --T----- --r- -- --- r- r--"1 -- "["-- -T � .. -r-----r----T----T---- -----,-- -- r - ---r---- -------T-----T
,. --[---------1--------"[--------T------------ ----------r----------T---------r----- ----------""["-------1" :: ::::::::::::::l:::::::::::i:::::::::::::::::::::: :::F::::f::::�=�: :::=:F:=::l ·
..
avgyower = 1.196Ie-005 Figure 14: simulation of Feynman gate (forward direction)
ISBN: 978-81-909042-2-3 ©2012 IEEE
QI
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--
: T:::-r:::=-:--·--·-+-·-···-·-t··-·--·-··t··-·-- - �:-:::::::=:==r:--:=�·:::�-=r-� ·r-·-.... ·-·-I----·--· -.-.---.'1""-... -.-1'--.-.--'1" .. -.--.... -" '-'--'-r'--'-'--1"'--'-"'-j "---'-'-1 " ··,-·-.... ·-·-1--·--.. ·- -.----.'1"--... --1'--.-.--'1"--.--.-. -·--·--·-I--- -·--·1-·---.. ·-r----·-·'1' " "1'-'-"'-"'1""''''''''-' "'''''''''-T-'''-'''-J'-'''-''''''T-''''''''-' ,,···-""·-r·"-"-"·I-""·" .. T" .. ·"·" .. T " ··]-· .. ···--1-" .
. ·-·-- ,,·-·-··-T"· .. · .. -·-T-"-·-,···--·-· .. -"'-"-'T"---'I--'T-'--"'1'
.. ]--... .. -"1"-.--.--. "'-'--'-T-'-"'--r---'--'T---"'-' -···--T·-----l"·"-·T"·---r
.. [-...... .. -.-1'.".--... - ".-.-" ... "1"".".-" .. '1'-".-.--'1" .. -.-...... -···,,·--···r·--·-·--·, .. ·,,-·-.. ·"r .... ·"·-.. '1'
"1= .. ,,+. .- : �]��:�+::=:]:=:: ·
:=::+�:"�T::::::·=::
·:::
·l
.
� ..
1 H ·'1'"·" ........ "1 .. • .. "" .... "1"·"·" ...... ·, ........ ,,.. .."·" ...... 1 .. ·1 ...... " .... ·"1· ..... "." ..... · ...... • .. r ...... " .. ·1· � "1" -
" ... ·1·· .. · .. --1· --...... 1.... ........ . ... '''1 ·,-.... • .. -.. 1 .. ·- -. '1' " ··r-·-.. ···-·-I .. · .. --.. · .. ·t-·"·"--.. r .. -"·-"· '--'-"'-'1 ····1·-·····--·1""-·-·--· .. · .. -·,,""'1" .. ,,·-·-"·1·
" I'" . -'1"-- -r"-'- 1 .. T " ''1'" '' 1 ... " , .. ,.-.-. ""-I"-"'-'--r---'-r'-"'--' --·-.. ·-·T··-·--·-·I·-···-·--·T-·-"--· '--'-"T-'-'-"'1' '1'-'- .. · .. ·T-·--· .. -·r---·-T .. · ... -- -'-"'-'1""-'-"'T-'-'-"'T " '-'-'-r"'--"T
"1'-'- ··· .. ·-r· .. ···· . . -j-·-·--" .. r·- .. -·- ·--·-···-'1"··"-······r-···········T··-·"·-··· · .. -.. · .. ·-r .. · .. ·-·-.. '1'
"r'" '1 -T r T" T I T T " .r·· . "I" T r" · . _ _ .:_ L: :: . C: ::r:_ __ T 1:
:: ::::::::::::�:::::::: _____ + __ .. __ ::::=::::::::: _____ , ___ · __ ..:::_..:::==:::r;.l � "j--'-'''--'-I''-'--'''-' ----.-"[-... -".-.-. .. -·-· .. -.. t .. ·-·-.. ·-· -.. ·---·-1------· "'--"'-[--'-'-"'1"
" 'I' "I ." .- .. I , 1 ., ·_-t
a .. t-·-.... ·-·-, .. -·--·--· -.---.--,-.-... -.-. .. --.. ·-.. t .. ·--.. ·-· -... -.--.-, .. -----. -'--"'-,-"'--"'1"
\� ·i�:�::�:�i::���=·I::::=:.::::::: :�:�¥�:::�::¥���: -::�f�:�:l :: IT ... "1' 1 . r " 1 I ,
.
� ..
avgyower = 2.066Se-OOS Figure IS: simulation of Feynman gate (backward direction)
2) FREDKlN GATE (;Hli
lllil [ i � r ) � t I: ;$ ) !i 0: ,
1!'l1�
�l_r .. ) � 1 Ii ::" .Ii � lll]!(
(;Hll
jli=iili:j=r ) I t 1/ ;$ J Ii ': &
1!l1�
avgyower = 1.2270e-006 Figure 16: simulation of Fredkin gate (forward direction)
' · 1: : : :V····················· ····· ····· ••••• ••••••• ••••••• ••••••• ••••••• I .... " ,. ". � � � : : : : ! :� ,
',-'Ill
::::::::::::::: 1 ••••• ••••••• ••••••• ••••••• ••••••• 1 :l:::::!.� 1'" :' ::�::::
� : q::::
, ,
ldi'lj •••••••••••••••••• 1 ••••••••••••••••••••••••••••••••••••••••••••••• i·::l:
',�
avgyower = -6.S332e-007
··I·-· I�i.: ::::::::::::::::i:::
Figure 18: simulation of Fredkin gate (backward direction)
3) T FLIP-FLOP
l<7" l.i7'· l<: ;l.:.;.. ... ...................... .. ...... .
;:1::... .. ... ......... .. ...... . l�1.· ....
-m
::::r: ��:: ::::::::::::::::f .. · ..
1'" ----,.1 ti+. « :.... �=�='7."="""=""'";==i,---;;--..J..=""""==#.==;;-
l;� ........... ....................... .. ........... .. ... ................................ � .. .. Ie'; .................................. . ........... .......................... .. {;.:.. .. ............................... , • .... •• .... • .... •• .... • .......... T .. ..
•• m X. m .. mmm ... j!,
r� ____
==I·m. m
::� ··· 1··· ..
{�:,,,. ;=='i=='7."'="""'=""'i;,,==;"'m"" .... = .... = .... "' .... = ..... = .... = .... � .. '= .... =�=�=""";=
li�._ .. lI�._ .. J �';._ .. �<.:..-.. :.i+_ .. ���.-.. l� : ll�._ .. ,�.;.-.. ((..:..-.. !l !l !l !l !"
avgyower = 2.9826e-004
Figure 17: simulation of T llip-llop
ISBN: 978-81-909042-2-3 ©2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 326
4) COUNTER OUTPUT
.... .... .... , , ...
.. . ...• .. .
.. ....-:::;:-,;;;;-,�"'""':::;-,::::-:=-:::::-;;;;;-,';;;;� .--et.:;�=-:=-:=-:;;;-;;:;-:=-:::::-::::;-;:::;-;::::-_ : .l � fl:f:1B f1 :O:HnflH Aqn B nnPj ELflfl •••••• ' ·I::lJ IJLl:l1tIIJLI: t1 I[UtJIJIJI.1utJtIIJt11
avgyower = 1.9988e-003
Figure 18: simulation analysis of counter output
Likewise we will get simulation of other reversible logic
gates.
VI. APPLICA TlON
Reversible computing may have applications in computer security and transaction processing, but the main long-term benefit will be felt very well in those areas which require high energy efficiency, speed and performance .it include the area like 1. 2. 3. 4. 5.
6.
Low power CMOS. Quantum computer. Nanotechnology Optical computing Design of low power arithmetic and data path for digital signal processing (DSP). Field Programmable Gate Arrays (FPGAs) in CMOS technology for extremely low power, high testability and self-repair.
VII. CONCLUSION
This paper proposes designs of basic reversible sequential elements such as latches, flip-flops and four bit reversible asynchronous up/down counter. We have shown average power dissipation in each gate in simulation part which indicates negligible energy dissipation which in turn improves performance of circuit. Basic reversible gate presented in this paper can be used in regular circuits realizing Boolean functions. The proposed asynchronous counter designs have the applications in building reversible ALU, reversible processor etc. In this paper, we present a method of
asynchronous counter design directly from reversible gates. This work forms an important move in building large and complex reversible sequential circuits .
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ISBN: 978-81-909042-2-3 ©2012 IEEE
