Fault Tolerance and Online Testability of Reversible Logic

Fault Tolerance and Online Testability Fault Tolerance and Online Testability of Reversible Logicof Reversible Logic

Presented by

Kaynat Quayyum

Roll: RH-209

Farzana Sharmin Farah

Roll: RH-234

Department of Computer Science & Engineering University of Dhaka

OverviewOverview•Fault Tolerant System•Reversible Fault Tolerant Gates•Online Testability•Gates with Built-in Testability•Online Testable Block•Railchecker•Online Testable Circuit•Constructing online testable 2 to 4 decoder•References

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Fault Tolerant SystemFault Tolerant System•Property that enables a system to continue operating properly in the event of the failure.•No single point of failure•Fault isolation to the failing component•Fault containment to prevent propagation of the failure•Availability of reversion modes

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Reversible Fault Tolerant Gates (1/2)Reversible Fault Tolerant Gates (1/2)•Solve the problem of bit error•Reversible•Parity preserving•

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2 n ,O .O O O I .. I I I 1-n2101-n210

Reversible Fault Tolerant Gates (2/2)Reversible Fault Tolerant Gates (2/2)

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A

B FredkinGate

C

P = A

Q = A’B AC

R = A’C AB

A

B F2G

C

P = A

Q = A B

R = A C

A

B NFT

C

P = A

Q = B’C AC’

R = BC AC’

(a) Feynman double-gate (b) New fault tolerant gate

(c) Fredkin gate

Figure 11: Fault Tolerant Gates

Fredkin Gate (1/2)Fredkin Gate (1/2)Fault tolerant

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A

1 FredkinGate

0

P = A

Q = A’

Figure 11: Fault tolerant Fredkin Gate

Odd

Even

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 0 1

1 1 1 1 1 1

Parity

Even

Even

Even

Odd

Odd

Odd

1

0

Q = A’

R = A

Fredkin Gate (2/2)Fredkin Gate (2/2)•Universal gate•Can be used as swapping gate

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0

B FredkinGate

C

P = 0

Q = B

R = C

1

B FredkinGate

C

P = 1

Q = C

R = B

Figure 12: Fredkin Gate as swapping gates

Online TestabilityOnline Testability

•Ability of a circuit to test a reversible block at computation time.•Testing in implementation phase saves time.

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Gates with Built-in TestabilityGates with Built-in Testability

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R2 Gate Gate

RR FEDRSFZEYDX

F

DE

P BCABCPQCBAT

BCABCBVBAU

C

AB

R1 Gate

•Online testable gate proposed by Dilip P. Vasudevan.•Used in pairs to make a testable block.

Online Testable BlockOnline Testable Block

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R 1 Gate

R 2 Gate

ABC0

ABC0

R 2 Gate

TB

Q1

1

XYZQS

X

ZY

S

If Q = S’ then R1 is fault free

Railchecker (1/4)Railchecker (1/4)•Used for the purpose of checking the output of online testable block.•First railchecker circuit proposed using R3 gate.

R 3 Gate

A

B

C ABCZAY

BAX

'

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Railchecker (2/4)Railchecker (2/4)

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Error checking function:

• e1=x0y1+y0x1

• e2=x0x1+y0y1

x0/y0 and x1/y1 are compliment of each other. So, for fault free circuit e1=e2’

x1

1

y0

1

y1

x1

1

1

x0

y0

1

e2

e1

1

R3

R3

R3

R3

R3

R3

Railchecker using R3


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X0

X1

G

G

G1

C=0

10 XXA

CA'D

Feynman Gate

Fredkin Gate

A C D=A’+ C

0 0 1

0 1 1

1 0 0

1 1 1

In Improved railchecker (IRC) output D did the same task as e1 and e2 for pair railchecker


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a

TB R1+R2

b101 TB

R1+R2101

TB R1+R2

d101 IRC IRC IRC

c

0e

Constructing Online Testable Constructing Online Testable CircuitCircuit

Step1:Convert each reversible gate to deduced reversible gateStep 2:Construction of testable reversible cellStep 3: Construct Testable cell TC when we have N TRC

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Constructing Online Testable Constructing Online Testable Circuit…Circuit…

N*N reversible gate

Deduced reversible gate (DRG)

I1

I2

I3

In-1

In

O2

O3

On-1

On

I1

I3

In-1

In

O1

On-1OnPout

O1

I2

Pin

O2

O3

Step1:Convert each reversible gate to deduced reversible gate

Input vector: I = [I1 , I2, .. In]Output Vector: O = [O1, O2, … On] where

16inout PFP nOOOOF ...321


nob

noa

ooOOPpooOOPp

.......321ib

.......321ia

Case 1: if Pia =Pib and if Poa≠pob then one of the output of DRGa or DRGb is faulty

Step 2:Construction of testable reversible cell

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DRGa

In-1

I2I3

Pia

DRGb

O1O2

O3

On-1OnPib Pob

Poa

I1

In

TRC

O1O2

O3

On-1OnPob

I2I3

Pia

I1

In

Pib Pob

In-1

nob

noa

ooOOPpooOOPp

.......321ib

.......321ia

Step 2:Construction of testable reversible cell

Case 2: if Pia ≠ Pib and if Poa=pob then one of the output of DRGa or DRGb is faulty


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DRGa

In-1

I2I3

Pia

DRGb

O1O2

O3

On-1OnPib Pob

Poa

I1

In

TRC

O1O2

O3

On-1OnPob

I2I3

Pia

I1

In

Pib Pob

In-1

Step 3: Construct Testable cell TC when we have N TRC

Here, Qoai = poai

Qobi = pobi

E = T (if there is no error)


TC

p′oa1p′ob1p′oa2

p′oan

p′obn

E=0

p′ob2

Q′oa1Q′ob1Q′oa2

Q′oan

Q′obn

T

Q′ob2

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EPPPPPPT obnoanoboaoboa )}(...)(){( 2211

Case 1 :If there is a any single bit error in any of the TRC then T=1 Because we provide E = 0 and poai = pobi

Constructing online testable 2 to Constructing online testable 2 to 4 decoder4 decoder

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Constructing online testable 2 to Constructing online testable 2 to 4 decoder…4 decoder…

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if T = 1 then there is a Error


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Not same, TRC1 is Faulty


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ReferencesReferencesBehrooz Parhami, “Fault-Tolerant Reversible Circuits”Dilip P. Vasudevan, “Reversible-Logic DesignWith

Online Testability”.Sk Noor Mohammad, “Constructing Online Testable

Circuits Using Reversible Logic”.N.M. Nayeem and J. E. Rice, “A simple Approach for

Designing Online Testable Reversible Circuits”

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Thank you

Fault Tolerance and Online Testability of Reversible Logic

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