Resume_BikashPoudel_01_04_2017
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int erests SoC Design & Verification, FPGA & ASIC, Microcontroller Programming, Reconfigurable Computing, Evolvable Hardware, Cryptography, Hardware-based Security, Cyber-Physical Systems, Game Theory, Evolutionary Computing edu cation 2015-2017 MS in Computer Science University of Nevada, Reno MS Thesis: Hardware-based Security 2008-2012 BE in Electronics and Communication Engineering TU, IoE, Pulchowk Campus Final Year Project: Digital Audio Processor in FPGA pub lications 2016 Design and Evaluation of a Novel ECU Architecture for Secure and Depend- able Automotive CPS, IEEE-CCNC 2014 Algorithm for Resource Optimized Design of Any N-Point FFT Computation, TU, IoE Graduate Conference 2014 Design, Simulation, Implementation, and Performance Analysis of a Fixed Point 8-Point FFT Core for Real Time Application in Verilog HDL, IJARS 2014 Implementation of Audio Eect Generator in FPGA, NJST 2014 Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA using Verilog, NJST awa rds 2014 Best Poster Presentation Award, TU, IoE Graduate Conference 2012 Hardware Competition First Prize, LOCUS, TU, IoE, Pulchowk Campus 2008-2012 College Fellowship Scholarship, TU, IoE, Pulchowk Campus exp erience 2015-2017 Graduate Research Assistant University of Nevada, Reno Working on design and evaluation of security hardware cores by lever- aging cryptography, genetic algorithm, game theory, and dynamic partial reconfiguration of FPGA. 2013-2014 Project Coordinator and Supervisor TU, IoE, Thapathali Campus, Nepal Supervised and coordinated multiple final year undergraduate projects. 2012-2013 Digital Design Engineer RiEmCom SCCS Pvt Ltd, Tyanglaphat, Nepal Performed design, functional verification, and implementation of various digital circuits using VHDL/Verilog as hardware design language. pro jects 2016-2017 Design of Side-Channel Resistant ECC Hardware University of Nevada, Reno Developed multi-objective genetic algorithm to auto-generate a side- channel attack resistant combinational circuit that performs elliptic curve cryptography (ECC). 2016 Design of a Novel ECU Architecture University of Nevada, Reno Designed electronic control unit (ECU) architecture for real-time automo- tive cyber-physical systems by harnessing the compute capability of FPGA and GPGPU. 2011-2012 Digital Audio Processor in FPGA TU, IoE, Pulchowk Campus, Nepal Designed and implemented a VHDL module in FPGA to generate various real-time audio eects using digital audio processing algorithms. ref erences Arslan Munir [email protected] Bikash Poudel Researcher i 27 March 1991 B Reno, NV USA T +1 631-431-0286 m https://linkedin.com/in/bpoudel7, https://github.com/bpoudel7, https://esrd2014.blogspot.com/ @ [email protected] About me I am a researcher and SoC enthusi- ast. I have been working in digital sys- tem design, verification, and synthesis in FPGA and microcontroller program- ming since 2010. Personally, I am un- derstanding, easy going, always smil- ing, and faithful person. Skill R, MATLAB, ModelSim Embedded System Design C, Embedded C, C++ Programming Evolutionary Computing Cryptography, Security, Game Theory Microcontroller Programming Xilinx ISE, Vivado, ISIM Simulator Design Verification, Timing Analysis VHDL, Verilog, System Verilog, FPGA Research python?2 latex?3 leadership?3.5 linux?3.5 cuda?3.5 git?2 (*)[The skill scale is from 0 (Fundamental Awareness) to 6 (Expert).]
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Transcript of Resume_BikashPoudel_01_04_2017
interestsSoC Design & Verification, FPGA & ASIC, Microcontroller Programming, ReconfigurableComputing, Evolvable Hardware, Cryptography, Hardware-based Security, Cyber-PhysicalSystems, Game Theory, Evolutionary Computing
education2015-2017 MS in Computer Science University of Nevada, Reno
MS Thesis: Hardware-based Security2008-2012 BE in Electronics and Communication Engineering TU, IoE, Pulchowk Campus
Final Year Project: Digital Audio Processor in FPGA
publications2016 Design and Evaluation of a Novel ECU Architecture for Secure and Depend-
able Automotive CPS, IEEE-CCNC2014 Algorithm for Resource Optimized Design of Any N-Point FFT Computation,
TU, IoE Graduate Conference2014 Design, Simulation, Implementation, and Performance Analysis of a Fixed
Point 8-Point FFT Core for Real Time Application in Verilog HDL, IJARS2014 Implementation of Audio E�ect Generator in FPGA, NJST2014 Design and Implementation of Synthesizable 32-bit Four Stage Pipelined
RISC Processor in FPGA using Verilog, NJST
awards2014 Best Poster Presentation Award, TU, IoE Graduate Conference2012 Hardware Competition First Prize, LOCUS, TU, IoE, Pulchowk Campus2008-2012 College Fellowship Scholarship, TU, IoE, Pulchowk Campus
experience2015-2017 Graduate Research Assistant University of Nevada, Reno
Working on design and evaluation of security hardware cores by lever-aging cryptography, genetic algorithm, game theory, and dynamic partialreconfiguration of FPGA.
2013-2014 Project Coordinator and Supervisor TU, IoE, Thapathali Campus, NepalSupervised and coordinated multiple final year undergraduate projects.
2012-2013 Digital Design Engineer RiEmCom SCCS Pvt Ltd, Tyanglaphat, NepalPerformed design, functional verification, and implementation of variousdigital circuits using VHDL/Verilog as hardware design language.
projects2016-2017 Design of Side-Channel Resistant ECC Hardware University of Nevada, Reno
Developed multi-objective genetic algorithm to auto-generate a side-channel attack resistant combinational circuit that performs elliptic curvecryptography (ECC).
2016 Design of a Novel ECU Architecture University of Nevada, RenoDesigned electronic control unit (ECU) architecture for real-time automo-tive cyber-physical systems by harnessing the compute capability of FPGAand GPGPU.
2011-2012 Digital Audio Processor in FPGA TU, IoE, Pulchowk Campus, NepalDesigned and implemented a VHDL module in FPGA to generate variousreal-time audio e�ects using digital audio processing algorithms.
referencesArslan Munir [email protected]
Bikash PoudelResearcher
i 27 March 1991
B Reno, NV USA
T +1 631-431-0286
m https://linkedin.com/in/bpoudel7,https://github.com/bpoudel7,https://esrd2014.blogspot.com/
AboutmeI am a researcher and SoC enthusi-
ast. I have been working in digital sys-tem design, verification, and synthesisin FPGA and microcontroller program-ming since 2010. Personally, I am un-derstanding, easy going, always smil-ing, and faithful person.
Skill
R, MATLAB, ModelSim
Embedded System Design
C, Embedded C, C++ Programming
Evolutionary Computing
Cryptography, Security, Game Theory
Microcontroller Programming
Xilinx ISE, Vivado, ISIM Simulator
Design Verification, Timing Analysis
VHDL, Verilog, System Verilog, FPGA
Research
python?2 latex?3 leadership?3.5linux?3.5 cuda?3.5 git?2(*)[The skill scale is from 0 (Fundamental Awareness)to 6 (Expert).]
