REPORT of STTP on

“Advances in VLSI Technology”

Preamble The quality of teaching and learning in today’s scenario is faced with many challenges like competitiveness, management, financing and reorientation of program by laying equal emphasis on quality of higher education, ethics and values together with the assessment of educational institutions and their accreditation. In the 21st century, the higher education can be used as a powerful tool to build knowledge based society. Quality of teaching should be viewed as a long-term social investment for the promotion of social cohesion, cultural development, economic growth, equity and justice. Quality of Indian education system can address itself to the global challenges through maintaining the right balance between the need and the demand and channelizing teaching, research and extension activities.

Background

With the support of Directorate of Technical Education (DTE), eInfochipts and ISTE, Ahmedabad the Electronics and Communication Engineering department, L.D College of Engineering, Ahmedabad had organized a one week short term training programme on “Advances in VLSI Technology” during 28th May – 1st June 2018 at Bhaskaracharya Hall, Block No. 9, Electronics and Communication Department, L.D. College of engineering, Ahmedabad.

Learning Objectives

The course was designed primarily to train post graduate students , professionals, research scholars, faculties to enhance their knowledge in VLSI technology. Its objective was

To keep the faculty and researchers abreast of the new advancements in VLSI technology. To give an idea of Eco-system market trends, Design of RTL with different HDLs like

VHDL and Verilog. To give overview of verification flow, Backend flow, DFT with mini projects To provide the insight of VLSI technology as an emerging application in space science

domain.

STTP Organizing Committee

Patron- Dr. G.P Vadodaria (Principal, L.D College of Engineering) Convenor-Prof. Usha Neelakantan (HoD EC, L.D College of Engineering) Coordinators

o Prof. A. B. Nandurbarkar (Associate Professor LDCE) Co-coordinators

o Prof. S. K. Gonsai (Assistant Professor LDCE)

Expert Speakers

There were two eminent experts from SAC-ISRO, Ahmedabad, Nine experts from eInfochips, Ahmedabad and one expert from NEC, Japan.

1. Dr. Nilesh Desai, SAC Shri Nilesh M. Desai is a top ranker and gold-medalist of 1986 BE (Electronics & Communication) batch of L.D.College of Engineering, Gujarat University, Ahmedabad, India. Since joining SAC/ISRO, in his around Thirty two years of dedicated and illustrious engineering and research career, he has been involved in design and development of ISRO’s Microwave Radar Payloads like RISAT-1 Synthetic Aperture Radar (SAR), Oceansat-II and Scatsat-1 Scatterometers, Chandrayaan-2 etc.

2. Mr. TVS Ram, SAC He is the Group Director, Optical and Digital Communication Group, Satcom and Navigation Payload Area, Space Applications Centre. He was the Project Director IRNSS-Payload.

3. Mr. Snehal Patel, eInfochips He is Delivery Manager at eInfochips, An Arrow Company. He has 17+ years of ASIC/VLSI industry experience. He has been involved in more than 10+ complex SoC product tap-out. His main expertise is in providing turnkey solution for IP/SoC ASIC/FPGA verification.

4. Mr. Kaushal Modi, eInfochips He is Technical Manager Lead at eInfochips, An Arrow Company. He has overall 12+ years of experience in ASIC + FPGA Verification Domain, and currently working as Technical Manager in eInfochips. He has mainly worked on various complex SoC verification projects for eInfochips’ prestigious customers. Apart from SoC verification, he also possesses good hands on Power Aware Verification and Formal Verification domains.

5. Mr. Rushang Shah, eInfochips Rushang is a senior Technical lead at einfochips. Rushang brings to einfochips more than 13+ years of experience in ASIC verification. Prior to joining einfochips, Rushang was working as a Senior member Technical staff at Intel, USA. He has working experience on HVLs like Specman, System Verilog, Verification methodology like eRM, UVM, Specification like OTN, PCI and Ethernet.

6. Mr. Baboon Pal, eInfochips Technical Lead at eInfochips, An Arrow Company. Babun Chandra Pal has 7 years of ASIC/VLSI industry experience. He is taking care of AMS verification activities for turnkey projects which includes development of AMS verification methodologies, AMS test bench component developments and Verilog-AMS model development. He has successfully delivered 5 tape-outs at eInfochips. He has past experience with Wipro, AMD and Samsung.

7. Mr. Chintan Panchal, eInfochips Technical Manager at eInfochips, An Arrow Company. Chintan Panchal, having more than 17 years of ASIC/VLSI industry experience. He has all experience in ASIC/VLSI field with hand on expertise in ASIC development life cycles – DFT, Design, and Verification.

He has an extensive experience in ASIC DFT domain and worked on multiple DFT projects with multiple clients involving multiple geography on several ASIC projects on technological node 110nm to 7nm.

8. Mr. Janak Patel, eInfochips Janak Patel working as a Technical Lead in ASIC Functional Verification group at eInfochips, An Arrow Company. He is having skill in designing complex verification Testbench environment using industry standard HVL (System Verilog) and methodologies like UVM (Universal Verification Methodology). He has been working on execution of different industry standard complex protocol IP as well System on Chip (SoC) Verification for different application areas like Audio/Video processing, Gaming Processing, Automotive functional safety.

9. Mr. Balkrishna Agarwal, eInfochips Member Technical Staff at eInfochips, An Arrow Company. Balkrishna has more than 13 years of experience in field of ASIC design and implementation. Prior to Einfochips he has worked at Intel, Sandisk, Samsung and Broadcom on variety of chips and SOCs from 65nm to 14nm, mixed signal to pure ASIC, gate count ranging from 2M to 30M. He specializes in overall implementation and signoff, with 17 successful tape-outs to production including Intel Northbridge, Flash memory controller for 2and 3 level memory, Intel X86 CPU, ARM based SOC for mobile, TSMC DDR and PHY.

10. Mr. Abhishek Chhajer, eInfochips Senior Engineer at eInfochips, An Arrow Company. Abhishek Chhajer has more than 7 Years of experience in Physical Design. He has worked on cutting edge technology like 2.5D design, 3D design, HBM memories, 28nm, 16nm and 7nm. He has worked on complex networking chips working at more than 1GHz and with more than 100M instance count, Low power chips, and complex hierarchical implementation project.

11. Mr. Ajay Jani, eInfochips Delivery Manager at eInfochips, An Arrow Company. Ajay Jani has 20+ years of experience in VLSI world. He has been in Einfochips for little over 4 years. Before joining Einfo, he worked at Qualcomm-Bangalore and Intel-USA. He manages design team, which works on ASIC and FPGA projects.

12. Mr. Kazutoshi Wakabayashi, NEC, Japan

Dr Wakabayashi is Chief Scientist and product owner of CWB tool. He has more than 45 years of rich experience in silicon designing for both ASIC and FPGA. He is working for Chip designing at Higher Level of Abstraction since 1989. He has delivered many lectures to enlighten students worldwide.

STTP Course contents

Day1

Registration and Inauguration

Aerospace Sector and VLSI Requirements Ecosystem Market trends Front End Design (Design – RTL fundamentals, Verilog) Front end Exercise and hands on

Day 2

Overview of Verification, methodology, language and flow Hands on session-verification

Day 3

Back end flow- DFT Back end flow-DFT with mini project and example Back end flow-Physical design Back end flow-Physical design with mini project and example

Day 4

Mini Project-1 Mini Project-1 presentation of Project /QA Overview of CyberWorkBench tool from NEC

Day 5

Design, Simulation, Implementation of FIR Digital Filter and its verification mechanism Physical Design-DFT future trends Design thinking, Summary Feedback by participants Valedictory Function

Participants:

The STTP was attended by academicians from government engineering colleges, government polytechnic, and by scientists from PRL. There were total 19 participants from all over Gujarat. The list is attached as Annexure-2.

Detail Technical report of Short Term Training Program

The STTP was opened at 9:30 am with registration. The participants received there STTP kit from the registration desk. The session was opened by a small inauguration function where there were distinguished guests present at the dais. Mr. Atit Desai (GM –L&T, Ahmedabad.) was the chief guest, followed by honourable Dr. G.P Vadodaria (Patron (STTP), Principal-LDCE), Prof. Usha Neelakantan (Convener (STTP)-HoD EC, LDCE), Dr. Nilesh Desai (SAC-ISRO). The inauguration function started with the remembrance of almighty God and motivational speeches by one and all present at the dais.

DAY 1

Basically the whole STTP was divided into three basic sessions of Advancements in VLSI technology.

1. Designing aspect of VLSI domain i.e. logical designing of chip 2. Functional or logical verification of the chip 3. DFT and Physical design as well as verification of the chip

The first day was covered up by three sessions each of which was elaborated in the following points.

Session - 1

The STTP started with the lecture session by Dr. Nilesh M. Desai who is the deputy director-SSAA, Outstanding scientist – SAC, Ahmedabad on “Aerospace Sector & VLSI Requirements”. The lecture was started by the introduction to SAC-ISRO along with the major activities of it in various domains. Then he has explained the radiation effects on electronics and its mitigation at device level, circuit level and layout level. Further along with the introduction of FPGA and ASIC, he has explained the development of VLSI in SAC by discussing Xillinx FPGA, SatCom services, GSAT-19, IRNSS, GSAT-6 MSS services and technologies, MOM, Chandrayan mission as well as NavIC receiver.

Session - 2

The second session was on the concept of eco-system approach in VLSI advancement by Mr. Snehal Patel of eInfochips. He has initiated the presentation by giving the background of eInfochips. Then he has narrated the complete ecosystem for the product design that includes multi protocol ASIC with 802.11 and 802.15, advanced driver assistant system, embedded system, cloud and IoT, 28 nm mega data centre ASIC, sensor hub ASIC for sports and NYC smart city project using Qualcomm snapdragon 600.

Session - 3

The third session was on Verilog and FPGA architecture which was delivered by Mr. Ajay Jani of eInfochips. He has explained the following points:

Introduction to Verilog Verilog parameters and syntaxes Verilog v/s VHDL FPGA v/s ASIC Introduction to new Intel Stratix 10 architecture Stratix 10 Hyper Flex architecture

DAY 2

Day 2 was scheduled for design and verification of digital VLSI system and Analog Mixed signal design and verification. As a whole three sessions were there to cover whole these two topics. Three experts from eInfochips have delivered the lectures for whole day.

Session - 1

The day was started with the session of basic introduction to design and verification by two experts from eInfochips – Mr. Kaushal Modi and Mr. Rushang Shah. They have explained the basic mechanism of digital verification in VLSI domain in terms of the following points:

Design evolution according to gate width parameter. Background of new evolution which is memory oriented rather than new protocol designs Example and show piece of Arria 10 FPGA chip (20nm design) developed by Mr. Rushang

Shah. Example of complex SoC with PLL design. Introduction of verification flow in three different steps that is

o IP level o Cluster level o SoC level

Session – 2

The second session of day 2 was in line with the first session that is continuation of verification requirements which was delivered by Mr. Janak Patel of the same firm. The session was very interactive and logical session that has helped the participants to apply their mind at the fullest. His delivery content can be described in terms of following points:

Requirement of functional verification Example of calculator for understanding of the terms verification, testing plan, testing vectors

and scenario of verification Example of BCD to 7 segment decoder Choice of different stimulus for verifying the function of chip Concept of Test bench Concept of Checker Aspect of coverage plan (functional coverage) Time line regarding Netlist verification, RTL verification and ASIC design

Session – 3

The post lunch session was regarding the Analog Mixed Signal (AMS) design which was in sync with previous two sessions only but now it was the turn of verification of analog chips. The session was delivered by Mr. Babun Pal from eInfochips only. The session can be summarized by the following points:

Fundamental of AMS verification Requirement of AMS: bridge between analog circuits and digital blocks in a system Mixed signal types: Analog centric (ex. ADC)

Digital centric (ex. Oscillator) Mixed signal design verification flow Example of mixed signal design compiler developed by Cadence Concept of connect module which will behave as bridge between analog and digital blocks Concept of Mixed signal simulator i.e. UltraSIM

DAY 3

The third day of the STTP session was one more further step in the area of Advancements in VLSI technology i.e. Design For Testability (DFT) and Physical design of VLSI chip. The two interesting and knowledge sharing sessions from eInfochips experts have covered the whole day.

Session – 1

The day was commenced with the session on DFT Training delivered by Mr. Chintan Panchal of eInfochips. The main goal of this aspect is to detect the manufacturing faults of VLSI chips. The session was very worthy from current and future technical aspects point of view in the domain of VLSI chip fabrication and testing. The expert has thoroughly explained the concept by elaborating the following points:

Introduction to DFT along with difference between functional verification and physical verification

Requirement of DFT for enhancing the ability of chip to test the design by adding extra hardware inside the chip itself.

Principle of DFT – “All the INPUTS should be Controllable and all the OUTPUTS should be Observable”

Types of manufacturing faults and causes of it DFT v/s Verification Concept of Yield Different DFT techniques:

o SCAN based technique o ATPG o Boundary SCAN / JTAG o Memory testing

Different fault models and its thorough analysis Sign-off criterion

Session – 2

Post lunch session was centred on the concept of Physical designing which was delivered by MR. Balkrishna Agarwal. He has explained the concept by covering following points:

Introduction to ASIC design Overview of 16nm technology Planer CMOS v/s FinFET Detailed Physical Design flow Concept of Metal layers and Floorplan Effect of technology node shrink Placement and Routing steps Concept of Congestion and techniques required to remove it Congestion avoidance mechanism

Clock Tree Synthesis (CTS) and clock mesh concept Concept of Via and Via pillar Concept of cross talk aware routing Sign-off check matrices

DAY 4

Forth day of the STTP was purely based on practical aspects of VLSI domain which was covered up by two sessions from eInfochips experts and expert from NEC-JAPAN.

Session – 1

This session was typically assigned for showcasing of verification demos by Mr. Kaushal Modi, Mr. Rushang Shah and Mr. Janak Patel from eInfochips. They have covered up following points:

Verification flow design Concept of Test Bench Plan and Test Plan Simulation of design Concept of Verification analysis and Verification Closure Demo of Router with one input port and three output ports Test bench verification architecture

Session – 2

This post lunch session of forth day was on “Behavioural C-based Synthesis with CyberWorkBench” delivered by Mr. Kazutoshi Wakabayashi from NEC, Japan. The agenda of his session was centred on following points:

VLSI Design flow High level Synthesis Introduction of NEC’s HLS Tool CyberWorkBench Features of CyberWorkBench Why CyberWorkBench

DAY 5

The last day was on dedicated to the current technology aspects and future trends of DSP and VLSI technologies in the area of Space and research. The two sessions were conducted by experts from SAC and eInfochips, respectively on that day.

Session – 1

This session was on “Design, Simulation, Implementation of FIR Digital Filter and its verification mechanism” by TVS Ram of SAC, Ahmedabad. He has covered the following points:

Functionality of digital filter

Different utilities of filter Types of digital filters and concept of FIR filter Analysis and design of Digital FIR filter MATLAB and Verilog coding of FIR filter

Session – 2

This session was delivered by two eInfochip experts Mr. Chintan Panchal and Mr. Balkrishna Agarwal on Physical Design and DFT future trends. They have included following points:

ASIC future trends Cutting edge and Bleeding edge technologies IoT usage and growth Trends at various levels i.e.

o Device physical level 14nm and 7nm technology Nano scale MEMS and sensors FPGA and ASIC

o Implementation level Integrated software and tools Optimization and custom tools Low power methodology 2.5D and 3D chips

o Application level Google duplex, Amazon’s drone delivery Watches and wearables IBM Watson, IoT, Car play Samsung smart fridge, google nest Industrial IoT

VALEDICTORY

Valedictory session was graced by the presence of Dr. G.P. Vadodariya (Principal, LDCE), Prof Usha Nilakanthan (HOD EC Engineering), Prof. B. S. Sedani (Professor-EC Engineering) and Prof. A.B Nandurbarkar (Associate Professor and coordinator of STTP-EC Engineering). The experts from the eInfochips, Ahmeabad were also present during the valedictory session. Principal sir and Head of EC department have shared their experiences and motivated all the participants. Participants were asked to give oral feedbacks. Overall the feedback was positive and encouraging. eInfochip experts were felicitated by mementos and certificate of appreciation. Certificates of participation were awarded to the participants by the honourable guests along with a Group photograph for memory.

Implications of this STTP on teaching, student's projects n dissertation, industry and the society Implications of this short term training program will educate and train the graduates with knowledge and skills necessary toformulate, design and solve problems in Analog, Digital & Mixed Signal VLSI system design, VLSI Signal Processing, Real Time Embedded System design and Hardware Software Co-Design. Also it enables to provide technical skills in software and hardware tools related to the design and implementation of integrated Circuits, System on Chip for real time applications. Finally this training program will provide scope for Applied Research and innovation in the various fields of VLSI and Embedded Systems, and enabling the students to work in the emerging areas and enhance the skills of participates to make them work effectively as a team.

Outcomes of STTP

The participants

Learnt advancements and future trends in the field of VLSI technology. Learnt the front end designing by means of hardware description languages. Got aware with process of verification and testing. Got conversed Backend design flow in terms of DFT and physical design. Got to know the tool CyberWorkBench by NEC, Japan Got aware with the trends of VLSI domain in the area of space science.

Suggestions

Overall all the participants were happy with the conduction of STTP in this area, which is rarely taken up. There were few suggestions from the participants.

Some of the participants suggested conducting more such STTPs. One of the participants suggested having 2 weeks training programme to cover all topics.

Acknowledgement

We are really grateful from bottom of our heart to the Commissionerate of Technical Education (CTE), Gandhinagar for giving us permission to conduct the STTP. We appreciate prompt action in giving permission to all the participants to attend training in such a short notice. We consider ourselves lucky enough to get associated with eInfochips, Ahmedadbad for organizing the STTP. We would also like to thank eInfochips for providing logistic support for the STTP in terms of certificates and registration kit. It is our immense pleasure to thank the experts for sparing their time to share critical ideas and their experiences in the area of VLSI. How can we forget to thank our honourable principal Dr. G.P Vadodaria for being always encouraging for such events? We appreciate all the principals and heads for allowing the participants to attend the STTP. Last but not the least we are grateful to all the participants for their discipline and enthusiasm.

Photo Gallery

INAUGURAL

STTP

Valedictory

STTP GROUP

Prepared by Dr. Nirali A. Kotak Assistant Professor, E.C. Department, L.D.C.E. Ahmedabad