VLSI DesignLecture 1: Digital Systems and VLSI

Mohammad Arjomand

CE DepartmentSharif Univ. of Tech.

Adapted with modifications from Wayne Wolf’s lecture notes

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Overview

Why VLSI? Moore’s Law. The VLSI design process. IP-based design.

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Features of Better Circuit

1. Lower cost (chip area, number of ICs, …)2. Better performance (speed)3. Lower power4. Better reliability

More integration less inter-chip connections better reliability

Better testability5. Better repeatability6. Less design and fabrication time

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Components of an Electronic System Chip (usually a small part of the total cost, but can

influence the cost of other parts) Power supply Fan PCB (Printed Circuit Board) Bus Box

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Why VLSI?

Integration improves the design: lower parasitic = higher speed;

» Shorter length of signal transfer is another reason for higher speed (3 cm wire 3*10-2/3*108 = 0.1nsec)

lower power (hence better reliability);» Power is a limiting factor for high integration.

physically smaller. Integration reduces manufacturing cost -(almost) no

manual assembly.Greatly reduces cost of parts other than chip (supply, fan,

PCB, …)ASIC might be more expensive than standard IC, but

system’s cost will be lower.

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Levels of Integration

SSI MSI LSI VLSI Criteria:

Gate count (2-20, 20-200, 200-2000, 2000 +); you may see different numbers in literature

Pin countFeature size (line widths, line spacing, size)Chip sizeFunction (gate & FF, module, subsystem, system)

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Levels of Integration (cont’d)

Where to go after VLSI? ULSI (Ultra Large Scale Integration - which is between

500,000 and 10,000,000 transistors), GSI (Gigantic Scale Integration - which is over 10,000,000

transistors). Who knows the next step? Maybe:

UBSI (Unbelievably Big Scale Integration)! or

YWBHLI (You Wouldn't Believe How Large the Integration is)!!

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VLSI and you

Microprocessors:personal computers;microcontrollers.

DRAM/SRAM. Special-purpose processors.

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Moore’s Law

• Gordon Moore (co-founder of Intel( predicted that number of transistors per chip would grow exponentially (doubles every 18 months).

• Exponential improvement in technology is a natural trend: steam engines, automobiles.

• Obstacles for Moore’s law:1. Quantity and variety of products which use ICs has had less progress.2. Cost of design verification and test is large.3. Complexity of design makes it difficult to manage it among design and

engineering groups. Role of CAD tools.

log(#dev)

t

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Moore’s Law plot

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Moore’s Law and Intel processors

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Moore/Intel log scale

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Transistors/Intel Microprocessors

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Terminology

Manufacturing node: technology at a particular channel length.

Deep submicron technology: 250-100 nm. Nanometer technology: 100 nm and below.

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The cost of fabrication

Current cost: $4 billion. Typical fab line occupies about 1 city block, employs

a few hundred people. Most profitable period is first 18 months-2 years.

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Cost factors in ICs

For large-volume ICs:packaging is largest cost; testing is second-largest cost.

For low-volume ICs, design costs may swamp all manufacturing costs.

IC manufacturing technology is remarkably versatile (change masks).

Wafer size: 12 inch (moving to 18 inch) Chip size: 1.5 X 1.5 cm2 (moving to 2 X 2)

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Cost of design

Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU.

Cost elements:Architects, logic designers, etc.CAD tools.Computers the CAD tools run on.

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Intellectual property

Intellectual property (IP): pre-designed components.May come from outside vendors, internal sources.

IP saves time, design cost. IP blocks must be designed to be reused.

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Reliability

Nanometer technologies require attention to reliability. Design-for-manufacturing (DFM) and design-for-yield

(DFY) techniques adjust the design to improve yield. Circuit and architecture techniques can compensate for

unreliable components.

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The VLSI design process

May be part of larger product design. Major levels of abstraction:

specification;architecture; logic design;circuit design; layout.

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Role of Each Level

Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout:

Layout size determines fabrication cost.Shapes determine parasitics; hence the circuit speed and

power.

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Challenges in VLSI design

Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and

high performance are often at odds. Short design time: Late products are often irrelevant.

6 months delay losing 33% of the profit

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Techniques to eliminate unnecessary detail

1. Hierarchical design (divide and conquer, i.e.; breaking the chip into a hierarchy of components, where each consists of a body and a number of pins)

2. Design abstraction (use multiple levels of abstraction)3. Using CAD tools: tries to solve all 3 mentioned problems;

1. dealing with multiple levels of abstraction is easier when you are not absorbed in the details,

2. computer programs can analyze cost trade-offs much better (because they are methodical)

3. computers are much faster than humans.

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CAD Tools Categories

1. Design entry tools (e.g., schematic capture) capture a design in machine-readable form for use by other

programs, but don’t do any real design work.

2. Analysis and verification tools (e.g., spice) ease the analysis task, but don’t tell how to change the circuit for the

desired function/spec.

3. Synthesis tools (e.g., Leonardo) create a design at a lower level of abstraction from a higher level

description. Both hierarchical design and design abstraction are as

important to CAD tools as they are to humans.

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Dealing with complexity

Divide-and-conquer: limit the number of components you deal with at any one time.

Group several components into larger components: transistors form gates;gates form functional units; functional units form processing elements;etc.

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Hierarchical name

Interior view of a component:components and wires that make it up.

Exterior view of a component = type:body;pins.

Fulladder

a

bcin

sum

cout

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Instantiating component types

Each instance has its own name:add1 (type full adder)add2 (type full adder).

Each instance is a separate copy of the type:

Add1(Fulladder)

a

bcin

sum

cout

Add2(Fulladder)

a

bcin

sumAdd1.a

Add2.a

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A hierarchical logic design

z

box1 box2 x

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Net lists and component lists

Net list:net1: top.in1 in1.innet2: i1.out xxx.Btopin1: top.n1 xxx.xin1topin2: top.n2 xxx.xin2botin1: top.n3 xxx.xin3net3: xxx.out i2.inoutnet: i2.out top.out

Component list:top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outneti1: in=net1 out=net2xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3i2: in=net3 out=outnet

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Component hierarchy

top

i1 xxx i2

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Hierarchical names

Typical hierarchical name: top/i1.foo

component pin

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Design abstractions

specification

behavior

register-transfer

logic

circuit

layout

English

Executableprogram

Sequentialmachines

Logic gates

transistors

rectangles

Throughput,design time

Function units,clock cycles

Literals, logic depth

nanoseconds

microns

function cost

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Layout and its abstractions

Layout for dynamic latch:

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Stick diagram

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Transistor schematic

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Mixed schematic

inverter

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Circuit abstraction

Continuous voltages and time:

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Digital abstraction

Discrete levels, discrete time:

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Register-transfer abstraction

Abstract components, abstract data types:

+

+

0010

0001

0100

0111

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Top-down vs. bottom-up design

Top-down design adds functional detail.Create lower levels of abstraction from upper levels.

Bottom-up design creates abstractions from low-level behavior.

Good design needs both top-down and bottom-up efforts.

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Design validation

Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it.

Forward checking: compare results of less- and more-abstract stages.

Back annotation: copy performance numbers to earlier stages.

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Manufacturing test

Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right.

Must quickly check whether manufacturing defects destroy function of chip.

Must also speed-grade.

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IP-based design

Almost every chip uses some form of IP:Standard cell libraries.Memories. IP blocks.

Designers must know how to:Create IP.Use IP.

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Types of IP

Hard IP:Pre-designed layout.Allows more detailed characterization.

Soft IP:No layout---logic synthesis, etc. IP layout is created by the IP user.

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Hard IP

Must conform to many standards:Layout pin placement.Layer usage.Transistor sizing.

Hard IP blocks are usually qualified on a particular process.Qualification: Component is fabricated and tested to show

that the IP works on that fab line.

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Soft IP

Conformance of layout to local standards is easier since it is created by the user.

Timing can only be estimated until the layout is done. Must conform to interface standards.

A wrapper adapts a block to a new interface.

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IP across the design hierarchy

Standard cells.Pitch matched in rows, compatible drive.

Register-transfer modules. Memories. CPUs. Buses. I/O devices.

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Specifying IP

Hard or soft? Functionality. Performance, including process corners. Power consumption. Special process features required.

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The I/O lifecycle

specification

HDL design

characterizationand validation

documentation design

databaseextraction

qualification

IP modules chip design

IPdatabase

IPdocumentation

IP creation

IP use

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Using IP

May come from vendor, open source, or internal group. Must identify candidate IP, evaluate for suitability. May have to pay for IP. May want to qualify IP before use, particularly if it

pushes analog characteristics.