News on SOIPIX project

Recent progress on SOIPIX projectRyo Ichimiya (KEK/IPNS) on behalf of the SOIPIX collaborationhttp://rd.kek.jp/project/soi/ 18th International Meeting of Front-End Electronics (FEE2011), Bergamo, May 24-27, 20111Earthquake, Tsunami and recovery...On March 11th 2011 14:47 JST, Magnitude 9.0 earthquake hit East-Japan.Collaborating OKI Semiconductor Miyagi Fab. locates very near from the source of the earthquake.

the source of the earthquakeOKI Semi. Miyagi Fab.KEKJ-PARCTokyo 2Our big thanks to colleagues and friends outside Japan who support us and are giving warm words. They are highly appreciated. Wed like to keep them in our heart forever.Fukushima dai-ichi NPSOKI Semiconductor MiyagiOKI Semiconductor Miyagi, in which the SOIPIX is fabricated, has severe damage by the Earthquake and subsequent Water and electrical power stop.On April 15th, it resumed operation and now it produces products at 95% of normal level.Fortunately, our MPW run wafers (submitted on this Janually) were safe and are scheduled to ship in mid-July.3

KEK (Tsukuba)+J-PARC(Tokai)48-GeV Injector Q-Magnet(Tsukuba)

Groundwater discharges... (Tsukuba)

NU Target Station Building (J-PARC)

Linac building entrance (J-PARC)KEK recovery and responseNo human injured or casualties. Material damage are being assessed and will be recovered.Fortunately, we can resume to use our laboratory from the April 6th.

KEK radiation safety division has began real-time radiation monitoring just after electrical power recovered and made it publically viewable at KEK site: http://rcwww.kek.jp/norm/

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Radiation level is almost back to normal; its safe!!6

KEK Web page: http://www.kek.jp/intra-e/

OutlineSOIPIX technology Recent Test ResultsIssues & SolutionsSummary77No mechanical bump bondings-> High Density(pitch Low parasitic Capacitance, High SensitivityFast signal and High resolution (Full Depletion: >200mm Si)Standard CMOS circuits can be built.Thin active Si layer (~40 nm)-> No Latch Up, Small SEE Cross section, larger LET threshold.Based on Industrial standard technology -> Fabricate in a commercial fabrication plantMonolithic detector using Bonded wafer (SOI : Silicon-on-Insulator) of Hi-R (sensor) and Low-R (circuit) Si layers.SOI pixel detector

889SOI Pixel Process Flow

OKI 0.2mm FD-SOI Pixel Process Process0.2m Low-Leakage Fully-Depleted SOI CMOS (OKI)1 Poly, 4 (5) Metal layers, MIM Capacitor, DMOS optionCore (I/O) Voltage = 1.8 (3.3) VSOI waferDiameter: 200 mm, Top Si : Cz, ~18 -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thickHandle wafer: Cz ~700 -cm (n-type), FZ: ~10k-cm (n-type, p-type) up to 725 m thickBacksideThinned to 260 m and sputtered with Al (200 nm).

An example of a SOI Pixel cross section10Depletion layer10Recent Process Improvements11Increase No. of Metal Layer: 4 -> 5 layers --> Better Power Grid and Higher Integration

Shrink MIM Capacitor Size: 1.0 -> 1.5 fF/mm2 --> Smaller Pixel size become possible

Recent Process Improvements(contd)12Relax drawing rule: 30,45 -> Circle --> Smooth field and Higher breakdown Voltage

Introduction of source-inserted body contacts --> Better body contacts (Less kink and history effects, Lower noise).

Target Applications13High Energy PhysicsVertex detector Belle II @ KEK, ILC, sLHC,...Material ResearchX-ray Free Electron Laser (XFEL) @SPring-8Time resolved XAFS (X-ray absorption fine structure)...AstrophysicsX-ray Imaging detector, Infrared detectorMedical Mammography, CT, PET, Hadron Therapy,...Electron MicroscopyIndustrialX-ray Inspection SystemAdvantage: High density, Low material, Advanced functionality in each pixel.

RikenKEKINTPIX3KEKLBNL3D-AKEKLBNL3D-BKEKCNTPIX3LBNLJAXARikenCracowHawaiiKEKKEKTohokuMPW FY08(Feb.2009)MPW FY09-1 (Aug. 2009)MPW FY09-2 (Jan. 2010)14Multi Project Wafer (MPW) run KEK organizes MPW runs (2005-)Twice a year since 2009.This year: we have only one MPW run; tentatively scheduled on October. OKI Semiconductor Co. / Ltd. OKI Semiconductor Miyagi Co. Ltd. / T-Micro Co. Ltd.

KEK, LBNL, Hawaii, Cracow, Tohoku, JAXA, Riken/SPring-8KEK, Riken, Cracow, FNAL, Kyoto, HawaiiKEK, Riken, FNAL, LBNL, JAXA, KEK-MPI15

b-ray

Integration type pixel (INTPIX)Size : 14 mm x 14 mmwith CDS circuit1515Integration Type Pixel (INTPIX4)10.2 mm17x17 mm, 512x832 (~430kpixels, 13 Analog Out, CDS circuit in each pixel.Largest Chip so far.16

15.4 mm1617X-ray imaging test of INTPIX4

INTPIX4 & NIBOSHI

X-rayA small dried sardine (Niboshi in Japanese) is used.Bias Voltage: 200V (Vback)500 frame obtained Integration time: 250msX-ray tube(Mo): 20kV, 5mA

5mm18A small dried sardine (Niboshi in Japanese) is used.Bias Voltage: 200V (Vback)500 frame obtained Integration time: 250msX-ray tube(Mo): 20kV, 5mAX-ray imaging test of INTPIX4(contd)Pseudo-photon counting by INTPIX419

How to create above map:Calculate pulse height (PH) in each pixelSet threshold as 50 ADUIn each pixel frame, evaluate threshold(hit)Create count map (counts/pix)Energy Resolution20Energy ResolutionNeed to reduce noise, especially at read-out circuit.

Study of the limits of the energy resolution: single pixel readout modeDuring exposure, 1024 times samples sampled (scan interval=1ms)Signal level is calculated by difference between averaged 160 samples after X-ray hit and before hit.20

Counting Type Pixel (CNTPIX5)5 x15.4 mm272 x 212 pixels64um x 64 um pixel

Energy selection and Counting in each pixelTime Resolved Imaging9bit x 821Same architecture with HEP/NP pixels-> We are developing a prototype for next Belle II detector (SBPIX1).21Counting Type Pixel preamps(CSA)-22

AINAOUTTESTPulseCharge Sensitive Amp with sensor leakage current compensation circuit (F.Krummenacher, NIM A305 (1991) 527-532)Gain : 23.4mV/e-, ENC: 61.2e-

TEG31Step Input voltageCSA OutputCNTPIX5 Pixel Layout64x64 um2~600 Tr/pixx 72 x 212= 10,000,000 Trs23

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CNTPIX Measurement with X-rayCounting is increased with sensor bias voltage increase, but its behavior is unstable.Counting is increased with x-ray tube current increase, but insufficient linearity is obtained.CNTPIX2SOI Pixel Issues & SolutionsBack Gate Effect : Sensor voltage affect Tr. characteristics Buried P-Well (BPW) layerWafer Thinning : Thin Sensor TAIKO processWafer Resistivity: FZ(n, p) wafer and back-side processCross Talk & Radiation Hardness : Reduce coupling between Sensor and Circuit & control Back gate voltage Nested BNW/BPW, Double SOI WaferHigher Circuit Density : Increase pixel functionality. Vertical (3D) IntegrationLarger Detector: Cover Large area Larger Mask & Stitching2525a. Back Gate EffectFront Gate and Back Gate are coupled.(Back Gate Effect)

26Vg_back26BPW ImplantationSuppress the back gate effect. Shrink pixel size without loosing sensitive area.Increase break down voltage with low dose region.Less electric field in the BOX which may improve radiation hardness.BPWP+SOI SiBuriedOxide(BOX)Cut Top Si and BOXHigh DoseKeep Top Si not affectedLow DoseSubstrate ImplantationPixelPeripheralBuried p-Well (BPW)2727Id-Vg and BPW w/o BPWwith BPW=0VNMOSBack gate effect is suppressed by the BPW.

shiftback channel open28c. Thicker depletion layer (FZ SOI wafer)29

During the conventional SOI process, many slips were generated in the 8 FZ-SOI wafer. From the effort by an SOI wafer vendor and improvement of thermal process recipes, slip of FZ wafer can be reduced as it can be used for SOIPIX detector.c. Thicker depletion layer (FZ SOI wafer)30Spreading Resistance (SR) Measurement

725 mm260 mmFZ Wafer: 5e11cm-2~30VCZ Wafer: 5e12cm-2~200VCarrier concentration is determined by C-V method at 10V point.FZ: 5e11cm-2(~10kWcm), CZ: 5e12cm-2 (~1kWcm)We confirmed them and their flatness in depth with SR method.FZ wafer shows one order advantage to gain thicker depletion layer.Depletion depth vs Bias Voltage

Picture is borrowed fromhttp://www.toray-research.co.jp/kinougenri/hyoumen/hyo_009.html

FZ wafer of 260mm is fully depleted @~22Vc. Thicker depletion layer (FZ SOI wafer)CZ wafer: ~1k cm (5e12cm-2)FZ wafer: ~10K cm (5e11cm-2)31Breakdown:31c. FZ with backside polishing (CMP)32

Backside polished sensor can be operated at Vdet=400V, without increasing leakage current so much.

Note: Sensor width = 250mm (full deplete @22V); Over-depleted.

Depletion layerCZ: 230VFZ: 25V

SummarySOI detectors have become working detectors with 6 years study.Although we had several difficulties to maintain the SOI process, we run regular twice MPW runs a year and have very good collaboration with OKI semiconductor.This year: we have only one MPW run; tentatively scheduled on October.Main issue to realize the SOI pixel, back-gate effect, has been solved by Buried P-Well.Many R&D items are on-going to improve the performance of the SOI pixel detector (FZ, Nested BNW/BPW, 3D, Double SOI, stitching, radiation tolerance,...)We recognize that the SOI pixel comes to the stage of practical use, although there are still some items to be improved.Although tremendous Earthquake hit Japan, we are OK and we shall continue working on...333334Supplement

http://www.shimano.com/publish/content/global_cycle/en/us/index/products/road/105_5700.html 34KEK-OKI semiconductor SOI Brief History'05. 7: Start Collaboration with OKI Semiconductor. '05.10: First Submission in VDEC 0.15 mm MPW.'06.12: 1st (and last) 0.15 mm KEK MPW run.'07.3: 0.15 mm lab. process line was closed. --> move to 0.2 mm mass production line.'08.1: 1st KEK SOI-MPW run.'09.2: 2nd KEK SOI-MPW run. '09.8: 3rd KEK SOI-MPW run.'10.1: 4th KEK SOI-MPW run.'10.8: 5th KEK SOI-MPW run.'11.1: 6th KEK SOI-MPW run

3535Readout system for SOIPIXWe have developed a Ethernet-based (SiTCP) DAQ board for SOIPIX, named SEABAS (SOI EvAluation BoArd with Sitcp).Portable DAQ system; same software with Linux, Windows, Apple, etc.

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INTPIX4Sub Board for INTPIX4SEABASData Transferby EthernetADC & DACUSERFPGA300mmBias Voltage inletLV inlet36