Puneet Sharma and Puneet GuptaProf. Andrew B. KahngProf. Dennis SylvesterSystem-Level Living RoadmapAnnual Review, Sept. 2004

Basic Ideas

Gate-length biasing implies increasing the gate-length by 5%-10%.Impact of gate-length biasing:• Leakage reduces exponentially• Delay increases linearly

Impact on leakage variability:

Gate-Length BiasingA Highly Manufacturable Approach To Leakage Control

Device Numer

Gate Length (nm)PMOS NMOS

Unbiased Biased Diff. Unbiased Biased Diff.

1 125 132 +7 126 132 +62 124 126 +2 126 129 +33 124 126 +2 126 129 +34 121 127 +6 124 130 +65 121 127 +6 122 128 +66 122 128 +6 122 128 +67 125 131 +6 122 131 +7

0

0.2

0.4

0.6

0.8

1

1.2

130

131

132

133

134

135

136

137

138

139

140

Gate-length (nm)

Leakage

Delay

DOF(µm) ELAT(%) for 130nm ELAT(%) for 136nm0.09 7.66 7.710.33 6.97 7.040.50 5.98 6.230.67 4.67 5.021.00 2.06 2.71

Gate-Length

Leak

age

Gate-Length

Le

aka

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Gate-Length Variability

Biasing

Leakage Variability

Spice Model

Spice Model

Spice Netlists

Spice Netlists

Biased Gate-Length

Biased Gate-Length

GranularityGranularity

Characterize and augment standard cell library such that each master has a biased gate-length variant

Characterize and augment standard cell library such that each master has a biased gate-length variant

ExtendedStandard Cell

Library

ExtendedStandard Cell

Library

Circuit NetlistCircuit Netlist

Modified NetlistModified Netlist

Dynamic + LeakagePower Estimate

Dynamic + LeakagePower Estimate

IntroductionWith process scaling, leakage power reduction has become one of the most important design goals. In this research, we study the efficacy and feasibility of using a marginally increased gate-length for leakage power reduction.Delay increases linearly and leakage decreases exponentially as gate-length increases. We utilize this fact to propose the use of an increased gate-length for non-critical devices in a circuit. Application of this technique results in reduced leakage and leakage variability while having very small impact on circuit performance. Unlike the multi-Vt approach, which is highly effective and used in practice, the proposed approach does not require additional process steps and can be applied anytime during the design cycle.

Device Biasing• Which devices to bias?

Gate-length biasing reduces leakage and its variability,however, with a delay penalty.Solution: Selectively bias devices that are non-critical to circuit performanceReduction of leakage and its variability with no or very

small delay penalty• How much to bias?

Constrained to less than 10% to preserve pin- and layout-compatibility.Approach applicable as a post-layout/post-RET step

Methodology Overview

Leakage OptimizerUses slower, low-leakage cells in non-critical paths

Uses faster, high-leakage cells in critical paths

Leakage OptimizerUses slower, low-leakage cells in non-critical paths

Uses faster, high-leakage cells in critical paths

Methodology Details

Circuit delay penalty of less than 2.5%

Results: Leakage VariabilityLeakage variability reduction: 39%-54%

0.00%

10.00%

20.00%

30.00%

40.00%

50.00%

60.00%

c5315 c6288 c7552 alu128

Leakage distributionfor alu128

Percentage reductionin leakage spread

Ongoing Work• Extend to sequential test cases• Allow devices in a cell to have different biasing, and have cell

variants with different sets of timing arcs slowed down• Rise & fall transitions not both critical bias devices that

govern the non-critical transition• Timing arcs of a cell not all critical bias devices to

make non-critical arcs slow and reduce leakageInitial results:• Additional 2%-5% leakage reduction• Significant leakage variability reductionDisadvantages:• Increased cell library and GDSII size

• Evaluate at future technology nodes

Results: Manufacturability

Results: LeakageLeakage power reduction• Single Vt designs: 14-26% • Dual Vt designs: 4-15%

High correlation between drawn and printed gate-lengthPrinted and drawn gate-lengths of devices in AND2X6. Unbiased gate-length is 130nm; biased gate-length is 136nm.Tools: Mentor Calibre for OPC; Printimage for litho simulation

Process window improves with gate-length

CD tolerance: 13nmELAT: Exposure latitudeDOF: Depth of FocusTools: KLA-Tencor Prolith

Results generated by 2000 Monte-Carlo simulationsWID= DTD=3.33nm. Variations assumed to be Gaussian with no correlation.

Granularity: Freedom to assign different biased gate-lengths to different devices. We consider three options:

• Technology level: All devices in the library have the same biased gate-length.

• Cell level: All devices in a cell have the same biased gate-length. Devices in different cells may have different biased gate-lengths.

• Device level: All devices are free to have an independent biased gate-length.

Our approach: For each cell, NMOS devices have one biased gate-length and PMOS devices have an independent biased gate-length. Devices In different cells have independent biased gate-lengths.

Leakage optimizer: Simple TILOS like sizer; starts with all fastest cells, replaces cells that have slack with slower, low-leakage variants.

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c5315 c6288 c7552 alu128

Single Vt, Single Gate-Length

Single Vt, Dual Gate-Length

Dual Vt, Single Gate-Length

Dual Vt, Dual Gate-Length