Programming Example Lecture 8.6 A VHDL Forth Core for FPGAs: Sect. 7.
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Programming Example Lecture 8.6 A VHDL Forth Core for FPGAs: Sect. 7
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Transcript of Programming Example Lecture 8.6 A VHDL Forth Core for FPGAs: Sect. 7.
Programming Example
Lecture 8.6
A VHDL Forth Core for FPGAs: Sect. 7
Digilab D2E Development Board
Digilab D2E Development Board
50MHzCLK
Xilinx Spartan2XC2S200E-PQ208
Powerjack
5-9VDC
2.5VDCregulator
StatusLED
Expansion E Expansion F
Exp
ansi
on C
Exp
ansi
on D
Ser
ial P
ort
Par
alle
l Por
t
Port/progcontrolswitch
Expansion A Expansion B
EPP or SPPparallel port
JTAGPort
SerialPort
Pushbutton
Buf
fer
RS
-232
conv
erte
r
SPROM
3.3VDCregulator
Digilab DIO2 Peripheral Board
16x2LCD
15 LEDs4 7-seg.displays
8 switches 15 buttonkeypad
PS2port
XC95108PC84
10VGAport
5VDCregulator
2
3
8
data
cont
rol
4
addr
ess
6
JTA
G
4
Connector BConnector A
GNDVU
VDD
Digilab DIO2 Peripheral Board
FC16
clkclrTP
M
mclkbn
ProgramROM
P
M
TopDesign
clkdivcclk
IBUFG
clr clkled
oewe
cs
LCD_RW
LCD_RS
LCD_E
T(5:0) addr(5:0)
N
E1
Data(7:0)buff3
E2
Using the FC16Forth Core
DIO2@ ( addr – data )DIO2! ( data addr -- )
cs oe we addr(5:0) data(7:0) 1 1 0 xxxx00 btns(7:0) 1 1 0 xxxx01 ‘0’&btns(14:8) 1 1 0 xxxx1x switchs 1 0 000100 leds(7:0) 1 0 000101 leds(15:8) 1 0 000110 sseg_reg(7:0) 1 0 000111 sseg_reg(15:8)
Accessing the DIO2 Peripheral Board
DIO2@ ( addr – data )DIO2! ( data addr -- )
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity buff3 isgeneric (width:positive);port(
input : in STD_LOGIC_vector(width-1 downto 0); en : in STD_LOGIC; output : out STD_LOGIC_vector(width-1 downto 0)
);end buff3;
architecture buff3 of buff3 isbegin
output <= input when en = '1' else (others => 'Z');end buff3;
buff3.vhden
outputinput
Seven-segment LED display
constant DIO2store: opcode := X"010F"; -- DIO2!
constant LCDistore: opcode := X"0110"; -- LCDinst!
constant LCDdstore: opcode := X"0111"; -- LCDdata!
In opcodes.vhd
MultiCC: process (clk, clr, current_state)begin if clr = '1' then
ccycle <= "000001"; elsif (clk'event and clk = '1') then
if current_state = exec thenccycle <= ccycle + 1;
elseccycle <= "000001";
end if; end if;end process MultiCC;
signal ccycle: STD_LOGIC_VECTOR (5 downto 0);
In FC16_control add….
when exec => -- execute instr without fetching next one if (icode = X"010E" or icode = X"010F") and ccycle < 3 then next_state <= exec; elsif (icode = X"0110" or icode = X"0111") and ccycle < 8 then next_state <= exec;
--elsif icode = X"Code_for_multi-cycle" -- and ccycle < Num_cc_to_exec then -- next_state <= exec; else next_state <= fetch; -- go to fetch state end if;
In FC16_control add….
when DIO2store =>
cs <= '1'; oe <= '0';
pinc <= '0';
if ccycle = 1 then
we <= '1';
else
tload <= '1'; nload <= '1';
tsel <= "111"; nsel <= "01";
dpop <= '1';
end if;
In FC16_control add….
DIO2! ( data addr .. )
data_out <= btns(7 downto 0) when addr(1 downto 0) = "00" else '0'& btns(14 downto 8) when addr(1 downto 0) = "01" else switchs;
constant DIO2fetch: opcode := X"003A"; -- DIO2@
From DIO2 CPLD
In opcodes.vhd
In FC16_control.vhd
In FC16.vhd
E1 <= ground & data_io;
data <= data_io;
when DIO2fetch => -- read 8-bit DIO2-bus (E1)
tload <= '1'; -- DIO2@ ( addr – data )
tsel <= "100";
cs <= '1'; oe <= '1';
\ Test of DIO2 buttons, LEDs, and 7-seg displays : D2DIG! ( n -- ) \ Display n on 7-segment displays
DUP 8 RSHIFT \ n nHI7 DIO2! \ display nHI
6 DIO2! ; \ display nLO : D2LD! ( n -- ) \ Display n on the 16 LEDs
DUP 8 RSHIFT \ n nHI5 DIO2! \ display nHI
4 DIO2! ; \ display nLO : get.BTN2 ( -- n ) \ Push 15-button bit mask to T
1 DIO2@ \ btns(15:8)8 LSHIFT0 DIO2@ \ btns(7:0)
OR ;
: waitBTN2 ( -- n) \ Wait to push a button and get mask
BEGIN \ wait to lift fingerget.BTN2 0=
UNTILBEGIN \ wait to press button
get.BTN2UNTILget.BTN2 ; \ get buttons
: but>num ( n1 -- n2 ) \ convert button bit mask to button no. 15 FOR \ loop 15 times DUP 1 = IF \ value matches R> \ get loop value 15 SWAP - \ find index 1 >R \ break out of loop ELSE U2/ \ Shift button value THEN
NEXT NIP ; \ remove extra 1 from N
: main ( -- ) \ main program
BEGIN waitBTN2 \ wait to push BTN2 DUP D2LD! \ display on LEDs but>num \ find button number D2DIG! \ display on 7-seg displayAGAIN ;
type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (15 downto 0);constant rom: rom_array := (
JMP, --0X"0047", --1
-- D2DIG!dup, --2LIT, --3X"0008", --4rshift, --5LIT, --6X"0007", --7DIO2store, --8LIT, --9X"0006", --aDIO2store, --bRET, --c
-- D2LD!dup, --dLIT, --eX"0008", --frshift, --10LIT, --11X"0005", --12DIO2store, --13LIT, --14X"0004", --15DIO2store, --16RET, --17
-- get.BTN2LIT, --18X"0001", --19DIO2fetch, --1aLIT, --1bX"0008", --1clshift, --1dLIT, --1eX"0000", --1fDIO2fetch, --20orr, --21RET, --22
-- waitBTN2CALL, --23X"0018", --24zeroequal, --25JZ, --26X"0023", --27CALL, --28X"0018", --29JZ, --2aX"0028", --2bCALL, --2cX"0018", --2dRET, --2e
-- btn>numLIT, --2f
X"000f", --30tor, --31dup, --32LIT, --33X"0001", --34eq, --35JZ, --36X"0042", --37rfrom, --38LIT, --39X"000f", --3aswap, --3bminus, --3cLIT, --3dX"0001", --3etor, --3fJMP, --40X"0043", --41u2slash, --42drjne, --43X"0032", --44nip, --45RET, --46
-- mainCALL, --47
X"0023", --48dup, --49CALL, --4aX"000d", --4bCALL, --4cX"002f", --4dCALL, --4eX"0002", --4fJMP, --50X"0047", --51X"0000" --52);
Experiment #clock cycles Relative Speed Time (ms) @8MHz
Time (ms) @25MHz
FC16 - FPGA 60,299 1 0.034 0.151 8.83 7.54 2.41 Forth – HC12 1,763,369 29.244 1 4.419 258.26 220.42 ---- C – HC12 399,031 6.618 0.226 1 58.44 49.88 ---- FPGA-VHDL 6,828 0.113 0.004 0.017 1 0.85 0.273
Relative speed of FPGA Forth core
