Presenter : Ching-Hua Huang

2012/11/3

Implementation and Prototyping of a Complex Multi-Project System-on-a-Chip

Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Wei-De Chien, Shih-Lun Chen,Chi-Shi Chen, Jiann-Jenn Wang, and Chin-Long WeyNational Chip Implementation Center (CIC), Hsinchu, TaiwanDepartment of Electrical Engineering, National Central University, Jhongli, TaiwanCircuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

National Sun Yat-sen University

Embedded System Laboratory

A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip(MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform.

To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about 37.97mm2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2 by implementing these projects separately, the results show that there are 91.42mm2 silicon areas reduced by the MP-SoC platform.

Abstract(1)

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Abstract(2)

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In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented.

A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped-out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.

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What’s the problem

Many projects will be integrated in a SoC, namely MP-SoC. Reduced more area cost by use the MP-SoC.

In order to improve the robustness of MP-SoC design and verification A design flow was developed by CIC.

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Related work

[This paper]A Novel Methodology for

Multi-Project System-on-a-Chip

[Popular methodology]Integrated a complex system into a single

chip

[3-5][other paper reference]

[1] Surviving the SoC Revolution: A Guide to Platformbased Designs[2] Multiprocessor SoC Platforms: A Component-Based Design Approach[3] A Case Study of the Novel Low-Cost SoC Silicon Prototyping Service for Taiwan Academia [4] Multi-Project System-on Chip (MPSoC): A Novel Test Vehicle for SoC Silicon Prototyping[5] PrSoC: Programmable System-on-Chip (SoC) for Silicon Prototyping[6] ARM RealView Versatile, ARM[other paper reference] STEAC: A platform for automatic SOC test

[1]System

level integration

[2]Platform-based

design

Resolve the problem of high fabrication cost for SoC designs

An automatic SOCintegration platform “STEAC” was used to facilitate MP-SoC test integration

[6]

ARM™ RealView Versatile

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Proposed method Virtual Prototyping

A system modeling and HW/SW co-design virtual platform – ESL design methodology

Logical Implementation For IP’s development and verification

Rapid Prototyping ARM RealView Versatile A “CONCORD” platform

Physical Implementation The MP-SoC chip taped out to the foundry

Testing and Measurement Verigy 93000 ATE Customized development board

Virtual Prototyping

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The 1’st goal – CoSim All Verilog-based IP modules are packed with TLM

interfaces and connected to SystemC-based platform in the simulation environment.

The 2’nd goal – Performance analyze These analysis functions help designers to detect the

system bottlenecks.

Faster simulation speed About 100 times than pre-simulation.

Verilog-based IP module

Logical Implementation

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STEAC ： SOC TEST AID CONSOLE

Synopsys VIP ： Synopsys Verification IP Provide the effective approach to verify circuit

。It also can build the SoC platform rapidly. Provide the Functional Coverage and

Monitoring。It can analyze this design whether conform to the

specification.

IP1HDL coding

SynthesisDFT/ATPG

FPGA

Synthesis

HDL code

IPnHDL coding

…

SynthesisDFT/ATPG

… …

STEAC

SynthesisIEEE 1500 wrapper

APR

Netlist->post-sim

Netlist->pre-sim

STEAC

Test patterns

Rapid Prototyping – Two platform

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ARM™ RealView Versatile The connection architecture is not enough

。Support item One core tile sub board One FPGA tile sub board

CONCORD The bus architecture is designed into the main

board The silicon IPs are designed into the sub boards

。Support OpenRISC 、 ARM and LEON3 system

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Physical Implementation and Testing

Chip Area 4998x7598 um^2

Core Area 4000x6600 um^2

Ring Width 120um

I/O Pad # 485

Process TSMC 0.13um CMOS Process

Critical Path Delay

12.5ns(80MHz)@1.3V

TSMC 0.13um 1P8M There are two testing environments are used

in this MP-SoC. Verigy 93000 ATE Customized development board

Conclusion

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The silicon area can be significantly reduced. Saving approximately 70.6 % silicon area than

fabricated individually.

A CONCORD platform Emulating the MP-SoC hardware before chip taping

out.

… …

10 IPs

=129.39

… …

vvv=37.97

10 IPs91.42

My comment

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This paper is related to my tape-out working Virtual Prototyping

。Co-Ware Logical Implementation

。FPGA verification。Design compiler, IEEE 1500 wrapper, DFT and ATPG

Pre-layout simulation。SoC encounter, DRC and LVS check

Post-layout simulation Testing and Measurement

。Verigy 93000 ATE。Customized development board

It provide the different design approaches STEAC : A platform for automatic SOC test CONCORD : A modulation SoC verification platform