Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia...
Transcript of Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia...
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Prepared by
Dr. Ulkuhan Guler
GT-Bionics Lab
Georgia Institute of Technology
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Understanding Fabrication Imperfections
Layout of MOS Transistor
Matching Theory and Mismatches
Device Matching, Interdigitation and Common Centroid Layouts
Interconnections, Noise and Shielding
System Layout, Floor planning, Clock Design
OUTLINE
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Digital and Analog Transistors
Digital
• Speed• Load Driving Capability
• Area Optimization
Analog
• Accurate Aspect Ratio
• Matching• Noise• Minimize Stray and Gate Resistances
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W
W1
S
S1
Layout and Real Chip is Different
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Mask Production / Misalignment
Lateral Diffusion
Over‐Etching / Undercut
Boundary Conditions
Non‐Uniformity
3 D Effects
Possible Problems Related with Fabrication
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Mask Misalignment
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Mask Misalignment
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Lateral Diffusion
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Over Etching / Undercut EffectBoundary Dependent Etching
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Etching Variations due to Different Contact Resistance
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3 Dimensional Effects
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Difference between drawn and physical values
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OutlineUnderstanding Fabrication Imperfections
Layout of MOS Transistor
Matching Theory and Mismatches
Device Matching, Interdigitation and Common Centroid Layouts
Interconnections, Noise and Shielding
System Layout, Floor planning, Clock Design
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Forming NMOS and PMOS Transistors
Ptap and Ntap is necessary to isolate transistors
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Shallow Trench Isolation (STI)
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Proper NTAP and PTAP Connection
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Proper NTAP and PTAP Connection
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Source Drain Connection
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Multiple or Single Contact
Spiking
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Transistor Folding (Parallelization)
Analog Devices may have large W/L ratio
Drain and source
resistance are reduced with
contacts
Gate resistance is still high
Drain‐Bulk and Source‐Bulk capacitance is
still high
Gate capacitance is
still high
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Parasitic Capacitances
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Parasitic Resistances
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Transistor Folding (Parallelization)
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Transistor Folding (Parallelization)
Gate Resistance
Drain‐Bulk &Drain‐Source
Capacitance
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OutlineUnderstanding Fabrication Imperfections
Layout of MOS Transistor
Matching Theory and Mismatches
Device Matching, Interdigitation and Common Centroid Layouts
Interconnections, Noise and Shielding
System Layout, Floor planning, Clock Design
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Mismatch
Electrical properties of two devices are generally not same even they have the same layouts
This is called as Mismatch
Matching two devices is very important for some analog circuits such as, differential pair devices like opamp, and etc.
Some kind of mismatches can not be modeled with simulation tools
Designer should be aware of this during layout design
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Effects of Mismatch on Performance
• Eg. Current mirrors, Analog Digital Converter
Basic operation of some circuits directly depends on matching
• In differential pairsCommon‐mode rejection is limited
• In fully differential circuitsSupply noise rejection is limited
• Eg. band‐gap, LDOAmplifier offset and/or load mismatch degrade the performance of some circuits which contain amplifier
• Clock and signal skew and memory cell matchings
In digital circuits
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Mismatch
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid‐ State Circuits, vol. 24, pp. 1433 ‐ 1439, October 1989.
Suppose two matched devices have parameters P1 and P2
Mismatched between these two devices is ΔP
Mismatch has a Gaussian distribution, which has mean and standard deviation
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Mismatch
Systematic Mismatch
Mean µ(ΔP)
Due to process variation
Can not be eliminated totally but can be reduce significantly
Random Mismatch
Standard deviation σ(ΔP)
Due to imperfect balancing in circuit
and gradients
Can be minimized or even completely
eliminated
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Systematic Mismatch / Gradients
Certain physical parameters such as temperature, process biases, mechanical stress, oxide thickness, poly‐silicon etch etc. may vary gradually across an IC.
Since these variations can be computed mathematically, they are called as gradients.
These variations can cause to systematic mismatches. Another reason of systematic mismatch is inadequate layout.
Systematic mismatch can be very large and dominant.
In some cases ,a good way of testing systematic mismatch is power supply rejection simulation on the post layout netlist
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Random Mismatch/Dopant Fluctuations
Potential distribution of dopants in a 35nm MOSFETB.Cheng et al., “The impact of random doping effects on CMOS SRAM cell,” Proc. ESSCIRC, 2004, p219‐222
B. Hoeneisen and C. A. Mead, “Current‐voltage characteristics of small size MOS transistors,” IEEE Trans. Electron Devices, vol. ED‐19, pp. 382‐383, 1972
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Random Mismatch/Pelgrom’s Rule
∆ : : : : :
1‐ Place two devices closely2‐ Apply “Area Rule”, increase WL1‐ Place two devices closely2‐ Apply “Area Rule”, increase WL
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Random Mismatch / Some Analysis
Big Transistors match betterJose Pineda de Gyvez and Hans P, Tuinhout, "Threshold Voltage Mismatchand Intra‐Die Leakage Current in Digital CMOS Circuits", JSSC, Vol. 39, no. I, pp157‐168, Jan. 2004
Area RuleBrad Minch, 1999
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Random Mismatch / Some Analysis
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Why Matching?
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Orientation
Si and transistors are not perfectly isotropic
Keep direction of current flow same
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Exercise; Which layout?
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Exercise; Which layout?
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Exercise; Which layout?
Dummy Device is added
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Distance Effect
Remember “Pelgrom’s Theorem”,Place matched devices in close proximity
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Over‐Etching/ Under‐cut Effect / Boundary Effect
Use large W and L to reduce the effect of under‐cut
Use dummy devices to provide same environment
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Stress Effect
There is also stress caused by metallization. Therefore do not route metal across active area, if routing is unavoidable add
dummy metals so that each device sees same amount of metal
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Oxide Thickness
Devices with thinner oxide usually exhibit better matching
Use minimum tox devices for best matching if the process offers a choice
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Contacts
Contacts in active gate region may cause variation in Vt. Gate contacts must be outside the active region to reduce dopant effects, stress, work function etc.
Because of reliability issues use multiple contacts with exactly same number in the matched devices
One contact resistance is around several ohms. Use multiple contacts reduce resistance.
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Temperature effect
Temperature gradients affect accuracyDevices need to be placed symmetrical with respect to
power devices
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Bias Effect
Mismatch in the drain currents is bias dependent
Vt mismatch has a larger effect at low bias levels. High Vgs –Vt is good for current matching. Try to keep Vds same.
β mismatch dominates at high current
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid‐ State Circuits, vol. 24, pp. 1433 ‐ 1439, October 1989. 2.5um CMOS technology
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Current Matching
∆ ∆ //
∆/2
• Mismatch in the (W/L) values increase W/L• Mismatch in the threshold values increase overdrive
voltage
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Voltage Matching
• Threshold voltage mismatch can be reduced by careful layout
• Second component scaled with overdrive voltage, mismatch in the load and W/L
• Reduce overdrive voltage• Increase W/L and RL
∆ 2 ∆ ∆ /
/
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Current and Voltage Matching
MOS transistors can be optimized either for voltage matching or for current matching, but not for both !
For current matching keep overdrive voltage large (Current mirrors)
For voltage matching keep overdrive voltage smaller (Differential pair devices)
Route current a long way, not voltages. IR drops can cause big mismatches
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Check List for Matching
Place the transistors in close proximity
Orient transistors in the same direction
Place transistor’s segments in the area of low stress gradients
Place transistors away from the power devices
Make current or voltage matching
Use dummy devices if necessary
Use multiple contacts
Keep the layout of transistor compact
Use Common Centroid layouts for critical devices
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Corner Simulation
Some of the manufacturing limitations (some systematic mismatches) are captured in the spice transistor models
For example, two of the main parameters are DL and DW which show the differences between drawn and effective length and width of transistor, respectively.
Manufacturing process tolerances of these parameters are emulated in the corner case simulations
Narrower L and wider W Fast corner Wider L and smaller W Slow corner
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Corner Simulation
Some companies also provide models with fast NMOS and slow PMOS FS or with slow NMOS and fast PMOS SF
Some companies want that the circuit work within 3 sigma spread is applied to typical corners FF3, SS3.
0.13um and smaller technologies requires models for leakage. Faster process, maximum supply voltage and maximum temperature ML Maximum Leakage Typical process, typical supply voltage and typical temperature TL Typical Leakage
Monte Carlo Simulation can be run “to center the design”.
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TradeoffsIncreased channel length
Increased circuit area
Increased power dissipation
Reduced speed
Determine required level of matching
Minimal : 3σ 10mV, 3σ∆ 2%
Unit elements, matched orientation, compact layout
Moderate : 3σ 2mV, 3σ∆ 0.1%
Apply most of layout rules
Precise : Self calibration
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ReferencesA. Hastings, The Art of Analog Layout, 2nd Ed. Prentice‐Hall, 2006.
Lee Eng Han, et. Al., CMOS Transistor Layout Kung Fu, 2005. www.eda‐utilities.com
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw‐Hill, 2001.
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid‐ State Circuits, vol. 24, pp. 1433 ‐ 1439, October 1989.
B.Cheng et al., “The impact of random doping effects on CMOS SRAM cel1,” Proc. ESSCIRC, 2004, p219‐222
B. Hoeneisen and C. A. Mead, “Current‐voltage characteristics of small size MOS transistors,” IEEE Trans. Electron Devices, vol. ED‐19, pp. 382‐383, 1972
Jose Pineda de Gyvez and Hans P, Tuinhout, "Threshold Voltage Mismatch and Intra‐Die Leakage Current in Digital CMOS Circuits", JSSC, Vol. 39, no. I, pp157‐168, Jan. 2004
M. F. Lan et. al. , “Current Mirror Layout Strategies for Enhancing Matching Performance”, Kluwer AICSP, July 2001.
D. Clein, CMOS IC Layout ‐ Concepts, Methodologies, and Tools, Boston, 1999.D. Clein, CMOS IC Layout ‐ Concepts, Methodologies, and Tools, Boston, 1999.J. Franca and Y. Tsividis, editors, Design of Analog‐Digital VLSI Circuits For Telecommunications and Signal Processing, 2nd Ed., Prentice‐Hall, 1994.
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ReferencesM. Ismail and T. Fiez editors, Analog VLSI ‐ Signal and Information Processing, McGraw‐Hill, 1994.M. F. Lan et. al. , “Current Mirror Layout Strategies for Enhancing Matching Performance”, Kluwer AICSP, July 2001.F. Maloberti, “Analog Design for CMOS VLSI Systems”, Springer US
S. Palermo, “Analog VLSI Circuit Design Course Slides”
S. Hu, “Clock Network Synthesis Course Slides”
Delbruck, Indiveri, Liu, “Transistor Mismatch and Layout Techniques”
Mai, alon, Labonte, “Analog Layout”
H. Luong, “Analog Layout Techniques”
B. Boser, “Device Matching Mechanisms”
F. Yuan, “Analog CMOS Integrated Circuits Course, MOS Device Layout Techniques Slides”
J. Ghosh, “Advanced VLSI Design Lab, Layout of Analog Circuits Slides”
H. Aboushady, “CMOS Process Technology Course Slides”
G. Wang, “Layout for Analog Circuits”