Power Planning

POWER PLANNING USING EDI SYSTEM

COPYRIGHT © 2011, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED. 1

Cadence Design Systems, Inc.

Application Note

Power Planning

Encounter Digital Implementation (EDI) System

Rev – 1.0

June – 2011



Table of Contents

1. POWER CALCULATION ..................................................................................... 3

2. POWER NET CONNECT (GLOBAL NET CONNECTION) .......................................... 6

3. POWER RING .................................................................................................. 7

4. POWER STRIPES ............................................................................................. 8

5. STANDARD CELLS POWER ROUTE (FOLLOW-PIN CONNECTION) ........................ 10

6. TRIMMING OF STRIPES TO CONNECT THE CORE RINGS ....................................... 10

7. FINAL POWER ROUTING FOR ANY UNCONNECTED POWER NETS ......................... 11

8. WELL-TAP CELLS ......................................................................................... 11

9. POWER VIAS ................................................................................................. 12



Currently tools have the capability of creating the power network for the designers. In creating a power mesh, designers start from several approaches and reach a solution that prevent IR drop. This document explains how Encounter Digital Implementation (EDI) system software helps in achieving the best power network.

1. Power calculation Power routing calculations has to be done for determine ring and stripe widths needed for the implementation. To better understanding of calculation an example has been taken as below to show how the calculation of power grid can be done.

• Input for power calculation

The power network is mainly dependent on the process technology so from the technology DRM (Design rule Manufacture) EM (Electro Migration) Line Current Limits (High Density Backend) (Tj = 125C) has been taken out as below

Metal Level Idc (mA) M1 (Metal1) 0.759 * (W - 0.02) M2 (Metal2) 1.007 * (W - 0.02) M3 (Metal3) 1.007 * (W - 0.02) M4 (Metal4) 1.007 * (W - 0.02) M5 (Metal5) 1.007 * (W - 0.02) M6 (Metal6) 2.904 * (W - 0.02) M7 (Metal7) 2.904 * (W - 0.02)

Where, W is width of one pad finger.

CMOS90 spec indicates 110mA @125oc max continuous DC current per power pad

• How to do the power calculation

Total Estimated core power : 4W

Core supply voltage : 1.1v-1.2-v-1.3v

Operating temperature : 125oc

P=IV therefore current is : 4/1.1=3.64A (909mA per side) (1.1v is used to get the worst case scenario)

No of VDD pads : 24 (# of VDD pads decided from package)

Current per pad : 3.64/24 = 151mA

Exceeds power pad, finger spec, ring mesh width need recalculation

CMOS90 spec indicates 110mA @125oc max continuous DC current per power pad

• Pad Design

o Pad has 8x fingers which are available for connection into core



o Layer M4 to M7 is available for connection with 3.36um wide pin with 1.68um spacing

Below figure shows the structure of the pad.

• Calculating the Current through pad tracks

Now we have to calculate the max current we can pass through the pad tracks so that we can decide how to use the different metal layer

Current pre length*((width of finger-edge effect loss)*No. of fingers connected

Thin Metal (M4-M5) @125oc = 1.007*((3.36-0.02)*8) =26.9*2 layers=53.9mA ** 53.9mA current is calculated if we use both M4-M5 layers overlapping with each other

Thick Metal (M6-M7) @125oc = 2.904*((3.36-0.02)*8) =77.5*2 layers=155.1mA ** 155.18mA current is calculated if we use both M6-M7 layers overlapping with each other

CMOS90 spec indicates 110mA @125oc max continuous DC current. So above configuration cannot be used.

Since the above combination won’t work with the specification so to achieve the max mA in ring from pad through fingers if ring M6 vertical and M7 horizontal.

Horizontal connection using preferred routing direction would achieve current both VDD and VSS connection possible Thick (M7) + Thin (M5) fingers = 77.59+ 26.90= 104.5mA

Vertical connection using preferred routing direction would achieve current both VDD and VSS connection possible Thick (M6) + Thin (M4) fingers = 77.59+26.90=104.5mA

Finger of pad



• Calculating the density of Metal stripes

M7 core mesh - VDD/VSS 5.22um wide 6.72um pitch – straps in 100x100um 14.881*5.22=77.69% (38.84%per supply)

M6 core mesh - VDD/VSS 4.4um wide 12.32um pitch – straps in 100x100um 8.116*4.4=35.71% (17.85% per supply)

M5 core mesh - VDD/VSS 1.5um wide 13.44um pitch – straps in 100x100um 7.44*1.5=11.16% (5.58%per supply)

M4 core mesh - VDD/VSS 1.5um wide 24.64um pitch – straps in 100x100um 4.061*1.5um=6.092% (3%per supply)

M1 standard rows - VDD/VSS 1.2um wide 3.92um pitch – 25 rows in 100x100um 25*1.2um=30% (15%per supply)

• Calculating the ring width using current per pad distributed calculation

For Horizontal Ring: Pad Current: 104mA Current through M7 straps = (2.904 * (5.22 – 0.02) * 4) = 60.4032mA Current through ring = 104 – 60.4032 = 43.5968mA

Current in (left or right) ring branch = 43.5968/2 = 21.7984mA Certain width (W7) of ring has to drive this current, 21.7984 = 2.904* (W7– 0.02) W7 = 7.526um (this is for single M7 segment either VSS or VDD) ~7.56um (to make it multiple of 0.28, pitch of lower most H Layer M1)

For Vertical Ring: Pad Current: 104mA Current through M6 straps = (2.904 * (4.4 – 0.02) * 2) = 25.43904mA Current through ring = 104 – 25.43904 = 78.56096mA Current in ring branch = 78.56096/2 = 39.28mA Certain width (W6) of ring has to drive this current, 39.28 = 2.904* (W6 – 0.02) W6 = 13.54um (this is for single M6 segment either VSS or VDD) ~13.44um (to make it multiple of 0.28, pitch of lower most V Layer M1)



It is recommended that once power structure has been created then user should run a signoff analysis tool such as EPS to verify the power grids meeting the IR drop and EM requirements.

2. Power Net Connect (Global Net connection)

In a design global power and ground nets must be connected throughout the design in order to perform optimization and complete planning. The command used for doing the global connection is globalNetConnect. This command adds a new global or special net connection to the specific global net. This command should be run after design import and prior to power planning. It establishes the logical power connectivity. You would use globalNetCommand to:

• Connect pins in a single instance to a global net. • Connect multiple inst pins to a global net, either through wildcarding or by specifying

a region on the chip. • Connect one or more existing nets to the global net.

clearGlobalNets resets the global net and all tie-high and tie-low nets. encounter > globalNetConnect gnd -type pgpin -pin gnd encounter > globalNetConnect gnd -type pgpin -pin GND encounter > globalNetConnect vdd -type pgpin -pin vdd encounter > globalNetConnect vdd -type pgpin -pin VDD

This will connect all gnd and GND pins to the global gnd net and all vdd and VDD pins to the global vdd net, unless they are already explicitly connected to something else.

globalNetConnect only works for pins of type USE POWER or USE GROUND which is defined in LEF. The global nets must already have been defined in the configuration file. It is possible to connect all cells within a given module of the hierarchy to a different power net, e.g.: encounter > globalNetConnect vdd1 -type pgpin -pin vdd -module alu -override

This will connect all vdd pins in all instances below the module alu to the global net vdd1 regardless of current connection. To connect a specific instance, use the inst option. This does not take a hierarchical name, it is necessary to use it with the module option. To specify only the vdd pin of the instance alu1/i1/i2, use the following command encounter > globalNetConnect vdd -type pgpin -pin vdd -inst i2 -module alu1/i1 –override

Below example shows how to use the get_cells with globalNetConnect command

encounter > globalNetConnect HVDD -type pgpin -pin {VDD_P} -sinst [get_object_name [get_cells i_bs_block/PAD_*_HVDD -hierarchical]] -verbose -override

How to connect 1’b1/1’b0 to power nets with/without tie cells

When netlist has 1’b1 & 1’b0 and want to connect them directly to global power & ground nets respectively [say VDD & VSS] then the flow will be



encounter > loadConfig ./Default.conf 0 encounter > commitConfig encounter > globalNetConnect VDD -type tiehi encounter > globalNetConnect VSS -type tielo

Now the constant instance pin gets assigned to the global net [virtually] and during the signal route using the command globalDetailRoute it will connect physically.

When netlist has 1`b1 & 1`b0 and want to connect them to tie-hi and tie-lo cells respectively then the flow will be encounter > loadConfig ./Default.conf 0 encounter > commitConfig encounter > placeDesign encounter > setTieHiLoMode -cell {TIEHI TIELO} encounter > addTieHiLo # Tie-cells are only added after placement encounter > globalDetailRoute # Actual connections happen during signal routing

Therefore to connect constants with tie-cells it is not required to use "globalNetConnect -type tiehi/tielo" command. It's only when you need direct connections with power/ground global nets that you need this command.

To save the 1’b1'b0/1'b1 with the respective net names use the command saveNetlist -phys or saveNetlist -includePowerGround it will replace the net names only on the leaf cells. It will not replace them on hierarchical instantiations.

3. Power Ring The power ring has been created to all around the core to get the proper connection from the power pads. These rings can be specifying as planar rings, intermingled rings, overlapping rings, etc.

It was observed that the I/O core power supply cells have pins on higher metals (metal6 and metal7). In order to make good connections to the rings, same metal layers (metal6 and metal7) are used for power routing.

In overlapping rings scenario where a pair of dual power rings between I/O’s and the core is created. The power rings are created using metal7 through to metal4. The metal7 is on top of the metal5 and they are used for the horizontal edges, whilst the metal6 is on top of the metal4 and they are used for the vertical edges. The main reason behind having dual rings, i.e. two metal layers on each side of the core region, is to have stripes connected in those places where I/O core supply cells connect to the ring. If there was only a single ring, the I/O connections could block the stripes, which connect to the ring. By using the dual power rings, the width of the rings can be reduced, hence saving overall chip area. For other type of rings please see the solution linked.

The rings are created with the addRing command encounter > addRing -layer_bottom M7 -layer_top M7 -layer_left M6 -layer_right M6 -spacing_left spacing -spacing_top spacing -spacing_right spacing -spacing_bottom spacing -width_left width -width_top width -width_right width -width_bottom width -center 1 -nets "vdd gnd"



It is noted that the I/O connections are created before the stripe is inserted, so if there be any conflict then stripe will use the vias and joggings to connect to the ring instead of the I/O connections. From the power perspective, it is more important that the wide I/O connections have direct and straight connections to the power ring, so that the power can efficiently be distributed across the chip.VSS

I/

4. Power Stripes

Power mesh is created to supply the uniform power into the core. The density of the mesh can be determined using the core power consumption of the chip. While calculating the total power consumption of the core few assumptions has been taken

• The clock tree has not yet been created. This may increase power consumption by about 40%.

• Gate sizes are likely to increase (overall) in order to fix timing problems. • Additional buffers will be added to fix timing problems. • The power mesh is uniform.

In some scenario where noise is the major impact then creation of stripes positioned for optimal signal grid utilization so that signal tracks can be put adjacent to the power straps without wasting any space. Also, all the VDD-VSS stripe pairs allow a signal route to pass between them and in that way protect the susceptible signals from any noise.



The stripes are created using the addStripe command Encounter > addStripe -block_ring_top_layer_limit M7 -max_same_layer_jog_length 6 -padcore_ring_bottom_layer_limit M5 -set_to_set_distance 24.64 -stacked_via_top_layer AP -padcore_ring_top_layer_limit M7 -spacing {} -xleft_offset 0.0 -merge_stripes_value 0.21 -layer M6 -block_ring_bottom_layer_limit M5 -width 4.4 -nets vdd -stacked_via_bottom_layer M1

There are examples where we can tell the tool where to stop (complete to last target or first target, etc.) for completing the stripe connections to the rings. Encounter command "addStripe" has the "extend_to design_boundary", "extend_to first_padring" and "extend_to area_boundary" options to accomplish the above variations. Other options to the command lend flexibility in the methodology chosen by the user.

Example script to specify stop points for stripes

• Stop stripes at design boundary and create pins

Encounter > addStripe -extend_to design_boundary -set_to_set_distance 100 -stacked_via_top_layer metal5 -spacing 10 -merge_stripes_value 5.5 -layer metal2 -width 8 -switch_layer_for_padcorering 1 -nets {VSS VDD} -stacked_via_bottom_layer metal1

The parameter "extend_to design_boundary" cannot be used in conjunction with the "route_over_rows_only" parameter otherwise there will be spaces between rows and design boundary and the stripes will not extend to the design boundary.

• Stop stripes at first pad ring or pad pin

Encounter > addStripe -extend_to first_padring -set_to_set_distance 100 -stacked_via_top_layer metal5 -spacing 10 -merge_stripes_value 5.5 -layer metal2 -width 8 -switch_layer_for_padcorering 1 -nets {VSS VDD} -stacked_via_bottom_layer metal1

• Stop stripes at the selected area

Encounter > addStripe -extend_to area_boundary -set_to_set_distance 100 -stacked_via_top_layer metal5 -spacing 10 -merge_stripes_value 5.5 -layer metal2 -width 8 -area {5869.092 19961.153 9536.248 17725.561} -switch_layer_for_padcorering 1 -nets {VSS VDD} -stacked_via_bottom_layer metal1

If user has to control the extension of power routing to the design boundary and create pins to be used for connecting power to this block at the next level up use the below command. addStripe -extend_to design_boundary -create_pins 1



5. Standard cells Power Route (Follow-pin Connection) For single power supply, the following sroute command is used to route standard cell pins: encounter > sroute -noPadRings -noBlockPins -noStripes -noPadPins -straightConnections {straightWithDrcClean straightWithChanges} -layerChangeRange {bottomlayer toplayer} -viaConnectToShape {stripe} -deleteExistingRoutes -corePinMaxViaHeight <percentViaHeight> -stripeSCPinTarget none The –corePinMaxViaHeight option is used to control the width of vias at the crossover of core pins rails and stripes. This parameter is essential to prevent signal pin access problems due to complex spacing rules and the metal plates in via stack. The –layerChangeRange option is used to controls the minimum & maximum layer that the stack extends up to. This is useful when the power grid is on multiple layers and allows the connection to the lowest layer of the grid. The -stripeSCPinTarget none option is used for standard cell power routes to stop at the end of the row instead of terminating at the block ring or stripe.

In case of variable widths for power pins in standard cells then Sroute will picks the width based on the geometry at the edges of the cell. For ex. ff a standard cell has followpins on 2 layers, the followpin on the layer that has the largest total pin area is routed first. To change the width of the follow rail command sroute -corePinWidth 0.34 can be used.

In case user want the followpins routing through the standard cells to connect to the Metal2 power pins using Metal2 then sroute to connect to Metal2 pins when creating the followpins routing use the sroute option "-corePinLayer 2"

To make more control over snapping power routing to the grid, just as they now can snap signal routing to grid. Use the setSnapGrid command: setSnapGrid -layer { 2 3 4 5 } -pitch

setSnapGrid -layer { V12 V23 V34 V45 } -pitch

When all metal layers have been created and standard cells have been routed, it is advisable to check the design for any violations on the widths, spacing, and internal geometry of objects and the wiring between them. The power grid should be DRC clean and can be quickly verified by the verifyGeometry command.

6. Trimming of stripes to connect the core rings Some stripes may not be connected to the core rings. A straight stripe connection may not be possible if blocked by an I/O to ring connection of the opposite net. Connections can be made if jogs and layer changes are allowed. The following command is used encounter> sroute -noBlockPins -noCorePins -noPadPins -noPadRings \

-layerChangeBotLayer <metaltopVName> -layerChangeTopLayer <metaltopHName> \ -jogControl { preferWithChanges differentLayer } -nets "gnd vdd"



After stripes are created over the core area, some of them have to be removed or trimmed, for example, floating wires or wires that only have one connection. Both top layers have to be selected. encounter> editSelect -nets "gnd vdd" -layers "metalHName metalVName" -shapes STRIPE

When all stripes are selected, they are trimmed by the following command: encounter> editTrim –selected

In some circumstances the editTrim command has been observed to extend certain metal shapes as well as to trim them. This can create shorts. These shorts can be fixed by hand editing of the stripes in the affected areas.

7. Final Power routing for any unconnected power nets Once all the power structure is completed power routing features is used to make the final power connections. The sroute command is used to routes power and ground nets to the following power structures

• Block pins • Pad pins • Standard cell pins • Unconnected stripes

encounter > sroute -noBlockPins -noPadRings -noCorePins -noStripes -padPinMinLayer 6 -padPinMaxLayer 7 -layerChangeBotLayer 6 -layerChangeTopLayer 7 \ -straightConnections { straightWithDrcClean straightWithChanges } -nets "gnd vdd"

The pinMinLayerNumber variable, specifies the bottom-most pin layer to connect to the ring, whiles the pinMaxLayerNumber variable, specifies the top-most pin layer to connect to the ring.

To check the standard cell geometries in the design for any spacing violations between the power rail to power stripe vias and cell blockages we can use the command sroute –corePinCheckStdcellGeoms which detects the DRC violation and repairs these violations by trimming the via arrays as needed. Use this parameter after routing the power structures.

8. Well-Tap Cells The well-tap cells have to be inserted before the placement of the design. The well-tap cells are inserted with the following command: encounter > addWellTap -cell WTname -maxGap gap -inRowOffset offset -prefix WELLTAP

WTname is the name of the well-tap cell.

To verify the well-tap cells are placed to meet the required rules. The command can be run as soon as the well-taps are added and before the cells are placed as it checks all legal locations where a standard cell could be placed: encounter > verifyWellTap -rule WTrule -cells WTname



WTname is the same well-tap cell name used in the addWellTap command and WTrule is the distance to be checked.

9. Power Vias editPowerVia command is a powerful post-processing command to customize the via arrays to your needs. It can be accessed through the GUI using the menu tree Power -> Power Planning -> Edit Power Via...

editPowerVia provides many options (such as area, connection type, layers, etc.) for controlling which vias to modify. The vias can be scaled up or down, deleted, or you can enable options to fix minimum cut (minCut) and/or minimum step (minStep) violations.

For example, if you want to scale the height of all via56 arrays by 50% you would run: editPowerVia -via_scale_height 50 -modify_vias 1 -bottom_layer Metal5 -top_layer Metal6

Adding power vias to the design or performs one of the following actions to existing power vias can be done using the command editPowerVia.

• Modifies/Deletes the power vias, Converts virtual vias to real vias

Power Planning

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