Pipeline ADC’sPipeline ADC’s

February 2000February 2000

ELEN 689ELEN 689--603603

Content

• Interest of pipeline ADCs• The Origins of Pipeline ADCs

• Basic Architecture• Digital Correction• Detailed example

• Performance evaluation• Design-performance relations

Interest of the Pipeline ADCs

• A Figure-of-merit to evaluate the performance of an ADC is its information transfer capacity:

ITC=2NCS

where ITC is the Information Transfer Capacity in symbols/sec, N is the number of bits and CS is the Conversion Speed,

• For example, an 8-bit, 1GSPS ADC has an ITC of 2.56e11, whereas a 20-bit 44.1KSPS ADC has an ITC of 4.62e10,

• The state of the art in ADCs is presently given by a 14-bit, 80MSPS pipeline ADC, which provides an ITC of 1.3e12 symbols/sec.

Some Products and Performance Ref / Year Feature Technology Results Area (mm2) Power/Voltage

JSSC 12/1999 Pipelined delta-sigma

1.2u CMOS SNR74dB18Msps

48 324mW/3.3v

JSSC 12/1997 Pipelined delta-sigma

0.6u CMOS 16 bits20Msps

35 550Mw/5v

JSSC 12/1998 Self calibrating 0.5u CMOS 12bits 10Msps 15 335mW/3.3vJSSC 12/1996 Microcontroller

calibrating1u BiCMOS 16bits 1Msps 35 200mW/5v

ISSCC98 Analogcalibrating

1.0u CMOS 10 bits40Msps

47 650mW/5v

ISSCC98 2 channels 0.5u CMOS 8bits 75Msps 5.5 70mW/3.3vISSCC98 2 channels 1u CMOS 10bits,40Msps 42 565mW/5vISCAS98 Current mode 0.5u CMOS 8 bits 20Msps N/A 22mW/2.4vCAS II99 Good linearity 0.5u CMOS 12 bits3.3Msps N/A 300mW/5v

Device Resolution Conv.Rate(Msps)

Supply(v) SNR(dB) Power(mW)

Texas InstrumentsProductsTHS1206 pipeline 12 6 2.7-5.5 N/A 210TLV5580 pipeline 8 80 3.3 46 165TLC5540 semiflash 8 40 5 45 85Analog DevicesProductsAD9202 pipeline 10 32 3 N/A 90AD9203 pipeline 10 40 3 N/A 50MAXIM ProductsMAX1201 14 2.2 5 83 269

The Origins of Pipeline ADCs1- The Flash ADC

Encoder

Vref Vin

2n-1

Comparators

DigitalOutput

• Each comparator has its own threshold voltage, spaced by 1 LSB,

• The input is fed to all the comparators in parallel,

• The output of the comparators is in “thermometer” format,

• An encoder is used to convert to binary format.

2- Sub-Ranging ADCs

3 Bit A/DConverter

D/A Coverter

3 Bit A/DConverter

Gain

Sign

MSB

LSB

Vin

• The input is first converted by a simple 3-bits flash ADC,

• The digital value is converted back in analog format by a 3-bit DAC and subtracted from the input, this gives a residue,

• The residue is multiplied to get the full range, and then converted by a second flash.

More on Sub-Ranging

3bits 3bits+

First Stage Second Stage

l Very High Speedl 1 Conversion/Clock

l 1/2 Clock Latency l Higher Resolution with Less

Hardware: 2 X 3bit = 14 Comp.6bit = 63 Comp.

l Lower Power Dissipation

l Smaller Input Capacitancel Can be Interleavedl Requires High Precision Interstage

Processing

l Hardware Still Increases Exponentially within Each Flash

3- The Pipeline ADCBasic Architecture

The principle of sub-ranging ADC can be pushed to the limit of having only one bit per stage,At this point, each flash ADC is nothing more than a simple comparator,Also, the data is transferred in a pipeline fashion: when the data is sent to the second stage, another sampled data is fed to the first stage,The result is a latency delay equal to the number of stages.

AnalogStageVin

LSB

φ

AnalogStage

AnalogStage

AnalogStage

φ φ φ

MSB

Basic Block Architecture

2 bit A/D (Comparators)

2 bit D/A

Digital Out

Analog input(from previousstage)

Residue(to next stage)

+

-

Implemented by a single programmable amplifier

X2

The analog stage is formed of a 2 bits flash ADC, a 2 bits DAC and a adder/gain stage. The output is called the residue and issent to the next stage.

1 1

Functionality of the Basic Block

1 bit A/D 1 bit D/A

Digital Out

InResidue

+

-X2

1

Clock

In

Residue

midref VnStageVnStagenStage >−+−= )1( if ))1((2)(

midref VnStageVnStagenStage >−−−= )1( if ))1((2)(

Example

1bit 1bit

First Stage Second Stage

1bit1bit

1 10 1 Output=11

Third Stage Fourth Stage

0.5V (mid)

1V

0V

0.7V

0.4V

0.8V

0.6V0.2

-0.1

0.3

0.1

0.7/1=11.2/24

Effect of a Threshold ErrorWhat if we have an error on a comparator in the second stage?

1bit 1bit

First Stage Second Stage

1bit1bit

1 01 0 Output=9

Third Stage Fourth Stage

0.5V (mid)

1V

0V

0.7V

0.4V

0.2

-0.1

-0.5

0.7/1=11.2/24

Shift

0V

Saturation

-0.5

0V

Saturation

Effect on the Residue Plot

In

Residue

Ou

tpu

t ra

ng

e

Input range

ThresholdError

In

Residue

Out

put r

ange

Input range

SaturatedInput

In

Residue

Out

put

rang

e

Input range

SaturatedInput

Second Stage Third Stage Fourth Stage

• The input of the second stage falls within the threshold error range,• The output gets saturated because it is added instead of subtracted,• Since we are now at the maximum of the range, all other stages get

saturated.

Effect on a Residue PlotWith Wider Range

• What if we add some Input and Output Overhead Range?• The output will not get saturated at the next stage, but it will

since the level diverges instead of converging,• As a result, the true 1-bit/stage pipeline ADC is not practical.

In

Residue

Ou

tpu

t ra

ng

e

Input range

ThresholdError

In

Residue

Out

put r

ange

Input range

Second Stage Third Stage Fourth Stage

In

Residue

Out

put r

ange

Input range Saturation

Digital Redundancy

φ

Basic Block Basic Block Basic Block Basic BlockIn

φ φ φ

2 bit A/D 2 bit D/A

Digital Out

InResidue

+

-X2

2

Clock

Carry Carry Carry

D3 (MSB) D2 D1 D0 (LSB)

DDDDDD

DDDD

DD

Residue Plot with Redundancy

Vinmax

Residue

Vinmin

Vinmax

4

Vinmin

4

Out=00 Out=01 Out=10

2 bit A/D 2 bit D/A

Digital Out

InResidue

+

-X2

2

Clock

−+ <−+−= compref VnStageVnStagenStage )1( if ))1((2)(

+− >−<−= compcomp VnStageVnStagenStage )1( if ))1((2)(

+−>−+−= compref VnStageVnStagenStage )1( if ))1((2)(

Example of Digital Correction

0

0.5

-0.5

-0.125

0.125Vcomp+

Vcomp-

0.3Vin

0.1

0.2

-0.1

-0.2

0.1

0.2

10 01 10 01 00 01

1 0 0 1 11

102

10

0

0.3+0.5=0.8=102.4/26

Error Correction with Threshold Error on the Second Stage

0

0.5

-0.5

-0.125

0.125Vcomp+

V comp-

0.3V in

0.1

-0.3

-0.1

-0.2

0.1

10 10 00 01 00 01

1 0 0 1 11

102!

0.2

10

0

Detailed Example1.5-bit/stage with Digital Correction

Vin+ Vout+

Vref+ Vref-Vmid

φ1

φ1'φ2su

b

noop

add

C1

C2 φ2

Vin- Vout-

Vref- Vref+Vmid

φ1

φ1'φ2su

b

noop

add

C1

C2 φ2

• The Gain, DAC and Adder blocks can be implemented by a simple MDAC SC circuit,

Vout=2Vin+[Vref+, Vmid , Vin-]

2 bit A/D 2 bit D/A

Digital Out

InResidue

+

-X2

2

Clock

Precise X2 Block

+

-

+

-

C1 C2

C3

S1

S2 S3

S4 S5

S6

S7

S8

S9

S10

S11

VIN

VOUTOP1

OP2

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

VOUT

C 1*2*V IN

C2

C1*2*V IN +C

2

C2*2*V IN

C1

2*V IN

ININOUT VVCC

CC

V ×=×××= 222

1

2

1

Op-Amp StructureBasic Folded Cascode Amplifier

Used for Common-Mode Feed-back

• Good output and input dynamic ranges,

• High gain provided by the cascode structure.

The Flash ADC

+

-

+

-

Vin

Vref+

Vref-

Thermometerto MDACConverter

Thermometerto BinaryConverter

MSB LSB

ADD

NOOP

SUB • Each comparator has its own threshold,

• These threshold are the same for all the stages,

• The thermometer code has to be converted for the MDAC and for the Digital Correction circuit.

2 bit A/D 2 bit D/A

Digital Out

InResidue

+

-X2

2

Clock

Non-Overlapping Clock Generator

clock inphi 1

phi 2

Modeling of Pipeline ADCs

• Each analog block is identical,• Modeling is easy with a high-level

language (Matlab, SpectreHDL, etc).• Digital correction can be modeled by

ideal computations or basic digital modeling in Verilog. It is assumed ideal.

Pseudo-Code for a Fully-Differential Basic Block

In+=VinIn-=-VinWhile simulation is not finished, do

Repeat for each stageDiff_in=(In+)-(In-)If Diffin < Vcomp-, then

Digital_out = 00Diffout = 2(Diffin+Vref+)

If Vcomp- < Diffin < Vcomp+, thenDigital_out = 01Diffout = 2(Diffin)

If Diffin > Vcomp+, thenDigital_out = 10Diffout = 2(Diffin+Vref-)

Out+ = Diffout/2Out- = -Diffout/2

Compute Digital CorrectionReturn

0

Vin

0

In+

0

In-

MATLAB SimulationDNL with a 5% Gain Error on First Stage

MATLAB SimulationDNL with a 20% Threshold Error on the Comparator

Measurement examplesINL of Uncalibrated ADC

INL of Calibrated ADC

Measurement examples